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3ccacc4e44afa66f20dd6430bc7ff966cc670708
clang-p2996/llvm/test/CodeGen/AMDGPU/GlobalISel
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Matt Arsenault 91aac7c379 AMDGPU: Handle s_add_u32 in eliminateFrameIndex (#129628) 
We can fold frame indexes directly into existing immediate operands,
just like is already done for s_add_i32. We happen to use s_add_i32 in
the 32-bit add case, but s_add_u32 appears in the a 64-bit add sequence
of a flat pointer if an addrpacecast source is a frame index.

This avoids, but does not address a failure exposed after
a3165398db where two literal operands
end up in the final instruction. The underlying issue still exists for
some instructions without special handling in eliminateFrameIndex.
2025-03-05 08:09:46 +07:00
..
add_shl.ll
…
add.v2i16.ll
…
add.vni16.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
addo.ll
…
addsubu64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
amdgpu-irtranslator.ll
…
amdgpu-prelegalizer-combiner-crash.mir
…
andn2.i1.ll
AMDGPU/GlobalISel: Add test showing s_andn2_b32/b64 is not formed from booleans (#115537)
2024-11-08 13:09:58 -08:00
andn2.ll
AMDGPU: Fix overly conservative immediate operand check (#127563)
2025-02-27 08:42:09 +07:00
artifact-combiner-anyext.mir
…
artifact-combiner-asserts.ll
AMDGPU/GlobalISel: Run redundant_and combine in RegBankCombiner (#112353)
2024-10-16 09:43:16 +02:00
artifact-combiner-build-vector.mir
…
artifact-combiner-concat-vectors.mir
…
artifact-combiner-cse-leaves-dead-cast.mir
…
artifact-combiner-extract.mir
…
artifact-combiner-sext.mir
…
artifact-combiner-trunc.mir
…
artifact-combiner-unmerge-values.mir
[GlobalISel] Combine unmerge(unmerge()) if the result is legal. (#109606)
2024-09-25 07:04:09 +01:00
artifact-combiner-zext.mir
…
ashr.ll
Recommit "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C) (#114309)"
2024-11-08 10:21:46 -08:00
assert-align.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
atomic_load_flat.ll
GlobalISel: Fix combine duplicating atomic loads (#111730)
2024-10-31 07:55:12 -07:00
atomic_load_global.ll
GlobalISel: Fix combine duplicating atomic loads (#111730)
2024-10-31 07:55:12 -07:00
atomic_load_local_2.ll
GlobalISel: Fix combine duplicating atomic loads (#111730)
2024-10-31 07:55:12 -07:00
atomic_load_local.ll
…
atomic_optimizations_mul_one.ll
[GlobalISel] Combine G_MERGE_VALUES of x and zero (#116283)
2024-11-16 08:00:21 +01:00
atomic_store_local.ll
…
atomicrmw_fmax.ll
Revert "AMDGPU: Don't canonicalize fminnum/fmaxnum if targets support IEEE fminimum(maximum)_num (#127711)"
2025-02-20 10:19:14 +07:00
atomicrmw_fmin.ll
Revert "AMDGPU: Don't canonicalize fminnum/fmaxnum if targets support IEEE fminimum(maximum)_num (#127711)"
2025-02-20 10:19:14 +07:00
atomicrmw_udec_wrap.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
atomicrmw_uinc_wrap.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
bitcast_38_i16.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
bool-legalization.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
br-constant-invalid-sgpr-copy.ll
…
bswap.ll
…
buffer-atomic-fadd.f32-no-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
buffer-atomic-fadd.f32-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
buffer-atomic-fadd.f64.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
buffer-atomic-fadd.v2f16-no-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
buffer-atomic-fadd.v2f16-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
buffer-load-store-pointers.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
buffer-schedule.ll
…
bug-legalization-artifact-combiner-dead-def.ll
…
bug-legalization-artifact-combiner-dead-def.mir
…
call-outgoing-stack-args.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
clamp-fmed3-const-combine.ll
Revert "AMDGPU: Don't canonicalize fminnum/fmaxnum if targets support IEEE fminimum(maximum)_num (#127711)"
2025-02-20 10:19:14 +07:00
clamp-minmax-const-combine.ll
…
combine-add-nullptr.mir
…
combine-add-to-ptradd.mir
…
combine-amdgpu-cvt-f32-ubyte.mir
Revert "[GlobalISel] Combine [s,z]ext of undef into 0" (#118746)
2024-12-05 07:48:20 +01:00
combine-ashr-narrow.mir
…
combine-ext-legalizer.mir
…
combine-extract-vector-load.mir
…
combine-fabs-fneg.mir
…
combine-fcanonicalize.mir
…
combine-fdiv-sqrt-to-rsq.mir
…
combine-fma-add-ext-fma.ll
…
combine-fma-add-ext-mul.ll
[AMDGPU][GlobalISel] Align selectVOP3PMadMixModsImpl with the SelectionDAG counterpart (#110168)
2024-10-08 09:41:24 -04:00
combine-fma-add-fma-mul.ll
…
combine-fma-add-mul-post-legalize.mir
…
combine-fma-add-mul-pre-legalize.mir
…
combine-fma-add-mul.ll
…
combine-fma-sub-ext-mul.ll
…
combine-fma-sub-ext-neg-mul.ll
…
combine-fma-sub-mul.ll
…
combine-fma-sub-neg-mul.ll
…
combine-fma-unmerge-values.mir
…
combine-fold-binop-into-select.mir
…
combine-foldable-fneg.mir
…
combine-fpneg-one-fneg.mir
…
combine-fsh.mir
…
combine-fsub-fneg.mir
…
combine-itofp.mir
[GlobalIsel] Combine trunc of binop (#107721)
2024-09-11 15:04:55 +02:00
combine-lshr-narrow.mir
[GlobalISel] Combine G_MERGE_VALUES of x and zero (#116283)
2024-11-16 08:00:21 +01:00
combine-or-redundant.mir
…
combine-redundant-and.mir
…
combine-redundant-neg.mir
…
combine-rot.mir
…
combine-rsq.ll
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combine-rsq.mir
…
combine-sext-inreg.mir
…
combine-shift-imm-chain-illegal-types.mir
…
combine-shift-imm-chain-shlsat.mir
…
combine-shift-imm-chain.ll
…
combine-shift-of-shifted-logic-shlsat.mir
…
combine-shift-of-shifted-logic.ll
…
combine-shifts.mir
[GISel] Fold shifts to constant result. (#123510)
2025-01-21 05:10:45 -08:00
combine-shl-from-extend-narrow.postlegal.mir
[GISel] Fold shifts to constant result. (#123510)
2025-01-21 05:10:45 -08:00
combine-shl-from-extend-narrow.prelegal.mir
[GISel] Fold shifts to constant result. (#123510)
2025-01-21 05:10:45 -08:00
combine-shl-narrow.mir
…
combine-short-clamp.ll
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combine-trunc-shift.mir
…
combine-urem-pow-2.mir
…
combine-zext-trunc.mir
[GlobalIsel] Combine trunc of binop (#107721)
2024-09-11 15:04:55 +02:00
combiner-crash.ll
…
compute-num-sign-bits-med3.mir
…
constant-bus-restriction.ll
…
crash-stack-address-O0.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
cvt_f32_ubyte.ll
[GISel] Fold shifts to constant result. (#123510)
2025-01-21 05:10:45 -08:00
dereferenceable-declaration.ll
…
divergence-divergent-i1-phis-no-lane-mask-merging.ll
AMDGPU: Fix implicit vcc def to vcc_lo on wave32 targets (#109514)
2024-09-23 13:20:21 +04:00
divergence-divergent-i1-phis-no-lane-mask-merging.mir
…
divergence-divergent-i1-used-outside-loop.ll
[Utils][UnifyLoopExits] Avoid costly updates if nothing changed (#129179)
2025-02-28 10:14:31 -08:00
divergence-divergent-i1-used-outside-loop.mir
[AMDGPU] Skip non-wwm reg implicit-def from bb prolog (#115834)
2024-11-12 23:30:57 +05:30
divergence-structurizer.ll
…
divergence-structurizer.mir
MachineUniformityAnalysis: Improve isConstantOrUndefValuePhi (#112866)
2025-01-24 12:43:40 +01:00
divergence-temporal-divergent-i1.ll
…
divergence-temporal-divergent-i1.mir
…
divergence-temporal-divergent-reg.ll
…
divergence-temporal-divergent-reg.mir
…
divergent-control-flow.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
dropped_debug_info_assert.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
dummy-target.ll
…
dynamic-alloca-uniform.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
extractelement-stack-lower.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
extractelement.i8.ll
…
extractelement.i16.ll
…
extractelement.i128.ll
…
extractelement.ll
PeepholeOpt: Handle subregister compose when looking through reg_sequence (#127051)
2025-02-18 08:07:29 +07:00
fdiv.f16.ll
[AMDGPU] Adopt new lowering sequence for fdiv16 (#109295)
2024-10-08 09:49:20 -04:00
fdiv.f32.ll
Recommit "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C) (#114309)"
2024-11-08 10:21:46 -08:00
fdiv.f64.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
flat-atomic-fadd.f32.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
flat-atomic-fadd.f64.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
flat-atomic-fadd.v2f16.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
flat-scratch-init.gfx.ll
…
flat-scratch-init.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
flat-scratch.ll
AMDGPU: Fix overly conservative immediate operand check (#127563)
2025-02-27 08:42:09 +07:00
floor.f64.ll
…
fma.ll
[AMDGPU][True16][CodeGen] true16 codegen pattern for fma (#127240)
2025-02-19 11:37:24 -05:00
fmamix-constant-bus-violation.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fmamix-constant-bus-violation.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
fmax_legacy.ll
…
fmed3-min-max-const-combine.ll
Revert "AMDGPU: Don't canonicalize fminnum/fmaxnum if targets support IEEE fminimum(maximum)_num (#127711)"
2025-02-20 10:19:14 +07:00
fmin_legacy.ll
…
fmul.v2f16.ll
…
fp64-atomics-gfx90a.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
fp-atomics-gfx942.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
fpow.ll
[AMDGPU][True16][CodeGen] fix test for true16 codegen valu op (#128905)
2025-02-26 23:55:29 +07:00
frem.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
fshl.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
fshr.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
function-returns.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
function-returns.v2i65.ll
…
global-atomic-fadd.f32-no-rtn.ll
[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)
2025-02-26 14:13:39 +01:00
global-atomic-fadd.f32-rtn.ll
[AMDGPU] Do not allow M0 as v_readlane_b32 dst (#128867)
2025-02-26 14:13:39 +01:00
global-atomic-fadd.f64.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
global-atomic-fadd.v2f16-no-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
global-atomic-fadd.v2f16-rtn.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
global-value.illegal.ll
…
global-value.ll
…
hip.extern.shared.array.ll
…
i1-copy.ll
…
image-waterfall-loop-O0.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
implicit-kernarg-backend-usage-global-isel.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
inline-asm-mismatched-size.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
inline-asm.ll
…
insertelement-stack-lower.ll
AMDGPU: Handle s_add_u32 in eliminateFrameIndex (#129628)
2025-03-05 08:09:46 +07:00
insertelement.i8.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
insertelement.i16.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
insertelement.large.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
insertelement.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
inst-select-abs.mir
…
inst-select-add.mir
…
inst-select-add.s16.mir
[AMDGPU][True16][MC] VOP3 profile in True16 format (#109031)
2024-10-16 10:27:44 -04:00
inst-select-amdgcn.class.mir
…
inst-select-amdgcn.class.s16.mir
…
inst-select-amdgcn.cos.mir
…
inst-select-amdgcn.cos.s16.mir
…
inst-select-amdgcn.cvt.pk.i16.mir
…
inst-select-amdgcn.cvt.pk.u16.mir
…
inst-select-amdgcn.cvt.pknorm.i16.mir
…
inst-select-amdgcn.cvt.pknorm.u16.mir
…
inst-select-amdgcn.cvt.pkrtz.mir
…
inst-select-amdgcn.ds.swizzle.mir
…
inst-select-amdgcn.exp.compr.mir
…
inst-select-amdgcn.exp.mir
…
inst-select-amdgcn.fcmp.constants.w32.mir
[AMDGPU][True16][CodeGen] true16 codegen for icmp and is_fpclass (#124757)
2025-01-30 12:18:00 -05:00
inst-select-amdgcn.fcmp.constants.w64.mir
[AMDGPU][True16][CodeGen] true16 codegen for icmp and is_fpclass (#124757)
2025-01-30 12:18:00 -05:00
inst-select-amdgcn.fmad.ftz.mir
…
inst-select-amdgcn.fmed3.mir
…
inst-select-amdgcn.fmed3.s16.mir
…
inst-select-amdgcn.fract.mir
…
inst-select-amdgcn.fract.s16.mir
…
inst-select-amdgcn.groupstaticsize.mir
…
inst-select-amdgcn.mbcnt.lo.mir
…
inst-select-amdgcn.mul.u24.mir
…
inst-select-amdgcn.mulhi.i24.mir
…
inst-select-amdgcn.mulhi.u24.mir
…
inst-select-amdgcn.rcp.legacy.mir
…
inst-select-amdgcn.rcp.mir
…
inst-select-amdgcn.rcp.s16.mir
…
inst-select-amdgcn.readfirstlane.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
inst-select-amdgcn.reloc.constant.mir
…
inst-select-amdgcn.rsq.clamp.mir
…
inst-select-amdgcn.rsq.legacy.mir
…
inst-select-amdgcn.rsq.mir
…
inst-select-amdgcn.rsq.s16.mir
…
inst-select-amdgcn.s.barrier.mir
…
inst-select-amdgcn.s.sendmsg.mir
…
inst-select-amdgcn.sffbh.mir
…
inst-select-amdgcn.sin.mir
…
inst-select-amdgcn.sin.s16.mir
…
inst-select-amdgpu-atomic-cmpxchg-flat.mir
…
inst-select-amdgpu-atomic-cmpxchg-global.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
inst-select-amdgpu-ffbh-u32.mir
…
inst-select-amdgpu-ffbl-b32.mir
…
inst-select-amdgpu-wave-address.mir
…
inst-select-and.mir
…
inst-select-anyext.mir
…
inst-select-ashr.mir
…
inst-select-ashr.s16.mir
[TableGen][GISel] Import more "multi-level" patterns (#120332)
2024-12-18 14:44:55 +03:00
inst-select-ashr.v2s16.mir
…
inst-select-atomic-cmpxchg-local.mir
…
inst-select-atomic-cmpxchg-region.mir
…
inst-select-atomicrmw-add-flat.mir
…
inst-select-atomicrmw-add-global.mir
…
inst-select-atomicrmw-fadd-local.mir
…
inst-select-atomicrmw-fadd-region.mir
…
inst-select-atomicrmw-xchg-local.mir
…
inst-select-atomicrmw-xchg-region.mir
…
inst-select-bitcast.mir
…
inst-select-bitreverse.mir
…
inst-select-br.mir
…
inst-select-brcond.mir
…
inst-select-bswap.mir
…
inst-select-build-vector-trunc.v2s16.mir
…
inst-select-build-vector.mir
…
inst-select-concat-vectors.mir
…
inst-select-constant.mir
…
inst-select-copy.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
inst-select-ctlz-zero-undef.mir
…
inst-select-ctpop.mir
[TableGen][GISel] Import more "multi-level" patterns (#120332)
2024-12-18 14:44:55 +03:00
inst-select-cttz-zero-undef.mir
…
inst-select-extract-vector-elt.mir
…
inst-select-extract.mir
…
inst-select-fabs.mir
…
inst-select-fadd.s16.mir
…
inst-select-fadd.s32.mir
…
inst-select-fadd.s64.mir
…
inst-select-fcanonicalize.mir
[AMDGPU][True16][CodeGen] true16 codegen pattern for f16 canonicalize (#122000)
2025-01-24 10:44:00 -05:00
inst-select-fceil.mir
…
inst-select-fceil.s16.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-fcmp.mir
…
inst-select-fcmp.s16.gfx11plus-fake16.mir
[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)
2025-02-04 11:20:40 -05:00
inst-select-fcmp.s16.gfx11plus.mir
[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)
2025-02-04 11:20:40 -05:00
inst-select-fcmp.s16.mir
[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)
2025-02-04 11:20:40 -05:00
inst-select-fconstant.mir
…
inst-select-fexp2.mir
…
inst-select-ffloor.s16.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-ffloor.s32.mir
…
inst-select-ffloor.s64.mir
…
inst-select-fma.s32.mir
…
inst-select-fmad.s32.mir
…
inst-select-fmaxnum-ieee.mir
…
inst-select-fmaxnum-ieee.s16.mir
…
inst-select-fmaxnum-ieee.v2s16.mir
…
inst-select-fmaxnum.mir
…
inst-select-fmaxnum.s16.mir
…
inst-select-fmaxnum.v2s16.mir
…
inst-select-fminnum-ieee.mir
…
inst-select-fminnum-ieee.s16.mir
…
inst-select-fminnum-ieee.v2s16.mir
…
inst-select-fminnum.mir
…
inst-select-fminnum.s16.mir
…
inst-select-fminnum.v2s16.mir
…
inst-select-fmul.mir
…
inst-select-fmul.v2s16.mir
…
inst-select-fneg.mir
…
inst-select-fptosi.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-fptoui.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-fract.f64.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
inst-select-frame-index.mir
…
inst-select-freeze.mir
…
inst-select-fshr.mir
[AMDGPU][True16][MC] true16 for v_alignbit_b32 (#119409)
2025-02-27 11:00:01 -05:00
inst-select-i1-copy.mir
…
inst-select-icmp.mir
…
inst-select-icmp.s16.mir
[AMDGPU][True16][MC] VOPC profile fake16 pseudo update (#113175)
2024-11-22 12:12:13 -05:00
inst-select-icmp.s64.mir
…
inst-select-implicit-def.mir
…
inst-select-insert-vector-elt.mir
…
inst-select-insert.mir
…
inst-select-intrinsic-trunc.mir
…
inst-select-intrinsic-trunc.s16.mir
…
inst-select-inttoptr.mir
…
inst-select-load-atomic-flat.mir
…
inst-select-load-atomic-global.mir
…
inst-select-load-atomic-local.mir
…
inst-select-load-constant.mir
…
inst-select-load-flat.mir
…
inst-select-load-global-old-legalization.mir
Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v3 (#114443)
2024-11-01 11:13:29 -05:00
inst-select-load-global-saddr.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
inst-select-load-global.mir
…
inst-select-load-global.s96.mir
…
inst-select-load-local-128.mir
…
inst-select-load-local.mir
Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v3 (#114443)
2024-11-01 11:13:29 -05:00
inst-select-load-private.mir
…
inst-select-load-smrd.mir
…
inst-select-lshr.mir
…
inst-select-lshr.s16.mir
[TableGen][GISel] Import more "multi-level" patterns (#120332)
2024-12-18 14:44:55 +03:00
inst-select-lshr.v2s16.mir
…
inst-select-mad_64_32.mir
…
inst-select-merge-values.mir
…
inst-select-mul.mir
…
inst-select-or.mir
…
inst-select-pattern-add3.mir
…
inst-select-pattern-and-or.mir
…
inst-select-pattern-or3.mir
…
inst-select-pattern-smed3.mir
…
inst-select-pattern-smed3.s16.mir
[AMDGPU][True16][MC] V_MED3_I/U16_fake16 CodeGen pattern (#120600)
2024-12-20 10:53:58 +07:00
inst-select-pattern-umed3.mir
…
inst-select-pattern-umed3.s16.mir
[AMDGPU][True16][MC] V_MED3_I/U16_fake16 CodeGen pattern (#120600)
2024-12-20 10:53:58 +07:00
inst-select-pattern-xor3.mir
…
inst-select-phi.mir
…
inst-select-pseudo-scalar-transcendental.mir
…
inst-select-ptr-add.mir
…
inst-select-ptrmask.mir
…
inst-select-ptrtoint.mir
…
inst-select-returnaddress.mir
…
inst-select-sbfx.mir
…
inst-select-scalar-float-sop1.mir
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
inst-select-scalar-float-sop2.mir
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
inst-select-scalar-float-sopc.mir
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
inst-select-scalar-packed.xfail.mir
…
inst-select-select.mir
…
inst-select-sext-inreg.mir
…
inst-select-sext.mir
[TableGen][GISel] Extract helper function for constraining operands (#115148)
2024-11-07 07:16:54 +03:00
inst-select-sextload-local.mir
AMDGPU/GlobalISel: Insert m0 initialization before sextload/zextload (#111720)
2024-10-10 14:01:49 +04:00
inst-select-shl.mir
…
inst-select-shl.s16.mir
[TableGen][GISel] Import more "multi-level" patterns (#120332)
2024-12-18 14:44:55 +03:00
inst-select-shl.v2s16.mir
…
inst-select-sitofp.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-smax.mir
…
inst-select-smin.mir
…
inst-select-smulh.mir
…
inst-select-stacksave-stackrestore.invalid.mir
…
inst-select-stacksave-stackrestore.mir
…
inst-select-store-atomic-flat.mir
…
inst-select-store-atomic-local.mir
…
inst-select-store-flat.mir
…
inst-select-store-global.mir
…
inst-select-store-global.s96.mir
…
inst-select-store-local.mir
…
inst-select-store-private.mir
…
inst-select-sub.mir
…
inst-select-trunc.mir
…
inst-select-trunc.v2s16.mir
…
inst-select-uadde.gfx10.mir
…
inst-select-uadde.mir
…
inst-select-uaddo.mir
…
inst-select-ubfx.mir
…
inst-select-uitofp.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-umax.mir
…
inst-select-umin.mir
…
inst-select-umulh.mir
…
inst-select-unmerge-values.mir
[AMDGPU] Fix failing test after #109958 (#109964)
2024-09-25 15:02:23 +02:00
inst-select-usube.gfx10.mir
…
inst-select-usube.mir
…
inst-select-usubo.mir
…
inst-select-xor.mir
…
inst-select-zext.mir
[TableGen][GISel] Extract helper function for constraining operands (#115148)
2024-11-07 07:16:54 +03:00
inst-select-zextload-local.mir
AMDGPU/GlobalISel: Insert m0 initialization before sextload/zextload (#111720)
2024-10-10 14:01:49 +04:00
irtranslate-bf16.ll
…
irtranslator-amdgcn-cs-chain.ll
[AMDGPU] Fix @llvm.amdgcn.cs.chain with SGPR args not provably uniform (#114232)
2024-10-30 16:12:37 +00:00
irtranslator-amdgcn-sendmsg.ll
…
irtranslator-amdgpu_kernel-system-sgprs.ll
…
irtranslator-amdgpu_kernel.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
irtranslator-amdgpu_ps.ll
…
irtranslator-amdgpu_vs.ll
…
irtranslator-assert-align.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
irtranslator-atomicrmw.ll
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
irtranslator-call-abi-attribute-hints.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
irtranslator-call-implicit-args.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
irtranslator-call-non-fixed.ll
[AMDGPU] Fix @llvm.amdgcn.cs.chain with SGPR args not provably uniform (#114232)
2024-10-30 16:12:37 +00:00
irtranslator-call-return-values.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
irtranslator-call-sret.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
irtranslator-call.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
irtranslator-constant-fold-vector-op.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
irtranslator-constantexpr.ll
…
irtranslator-constrained-fp.ll
…
irtranslator-fast-math-flags.ll
…
irtranslator-fence.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
irtranslator-fixed-function-abi-vgpr-args.ll
…
irtranslator-function-args.ll
…
irtranslator-function-args.v2i65.ll
…
irtranslator-getelementptr.ll
…
irtranslator-indirect-call.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
irtranslator-inline-asm.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
irtranslator-invariant.ll
…
irtranslator-memory-intrinsics.ll
…
irtranslator-metadata.ll
…
irtranslator-non-integral-address-spaces-vectors.ll
…
irtranslator-non-integral-address-spaces.ll
…
irtranslator-prefetch.ll
…
irtranslator-ptrmask.ll
…
irtranslator-readnone-intrinsic-callsite.ll
…
irtranslator-sat.ll
…
irtranslator-sibling-call.ll
…
irtranslator-struct-return-intrinsics.ll
…
irtranslator-tail-call.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
irtranslator-zext-vec-index.ll
…
is-safe-to-sink-bug.ll
…
lds-global-value.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
lds-misaligned-bug.ll
…
lds-relocs.ll
…
lds-zero-initializer.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
legalize-abs.mir
…
legalize-add.mir
…
legalize-addrspacecast.mir
[AMDGPU][GlobalISel] Save a copy in one case of addrspacecast (#104789)
2024-08-19 18:22:29 +01:00
legalize-amdgcn.if-invalid.mir
…
legalize-amdgcn.if.xfail.mir
…
legalize-amdgcn.rsq.clamp.mir
…
legalize-amdgcn.wavefrontsize.mir
…
legalize-amdgcn.workitem.id.mir
…
legalize-and.mir
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)
2024-12-16 05:57:11 +00:00
legalize-anyext.mir
…
legalize-ashr.mir
…
legalize-atomic-cmpxchg-with-success.mir
…
legalize-atomic-cmpxchg.mir
…
legalize-atomicrmw-add.mir
…
legalize-atomicrmw-and.mir
…
legalize-atomicrmw-fadd-global.mir
…
legalize-atomicrmw-fadd-local.mir
…
legalize-atomicrmw-max.mir
…
legalize-atomicrmw-min.mir
…
legalize-atomicrmw-nand.mir
…
legalize-atomicrmw-or.mir
…
legalize-atomicrmw-sub.mir
…
legalize-atomicrmw-umax.mir
…
legalize-atomicrmw-umin.mir
…
legalize-atomicrmw-xchg-flat.mir
…
legalize-atomicrmw-xchg.mir
…
legalize-atomicrmw-xor.mir
…
legalize-bitcast.mir
…
legalize-bitreverse.mir
…
legalize-block-addr.mir
…
legalize-brcond.mir
…
legalize-bswap.mir
…
legalize-build-vector-splat.mir
…
legalize-build-vector-trunc.mir
…
legalize-build-vector.mir
…
legalize-build-vector.s16.mir
…
legalize-concat-vectors.mir
…
legalize-constant.mir
…
legalize-ctlz-zero-undef.mir
…
legalize-ctlz.mir
…
legalize-ctpop.mir
…
legalize-cttz-zero-undef.mir
…
legalize-cttz.mir
…
legalize-extract-vector-elt.mir
…
legalize-extract.mir
…
legalize-extractelement-crash.mir
…
legalize-fabs.mir
…
legalize-fadd.mir
…
legalize-fcanonicalize.mir
…
legalize-fceil.mir
…
legalize-fcmp-s32.mir
…
legalize-fcmp.mir
…
legalize-fconstant.mir
…
legalize-fcopysign.mir
…
legalize-fcos.mir
…
legalize-fdiv.mir
[AMDGPU] Adopt new lowering sequence for fdiv16 (#109295)
2024-10-08 09:49:20 -04:00
legalize-fexp2.mir
…
legalize-fexp.mir
…
legalize-ffloor.mir
…
legalize-flog2.mir
…
legalize-flog10.mir
…
legalize-flog.mir
…
legalize-fma.mir
…
legalize-fmad.s16.mir
…
legalize-fmad.s32.mir
…
legalize-fmad.s64.mir
…
legalize-fmaxnum.mir
…
legalize-fminnum.mir
…
legalize-fmul.mir
…
legalize-fneg.mir
…
legalize-fpext.mir
…
legalize-fpow.mir
…
legalize-fpowi.mir
…
legalize-fptosi.mir
…
legalize-fptoui.mir
…
legalize-fptrunc.mir
…
legalize-freeze.mir
Reland "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)" (#109958)
2024-09-25 13:02:29 +02:00
legalize-fshl.mir
[AArch64][GlobalISel] Add disjoint handling for add_and_or_is_add. (#123594)
2025-02-02 21:01:49 +00:00
legalize-fshr.mir
[AArch64][GlobalISel] Add disjoint handling for add_and_or_is_add. (#123594)
2025-02-02 21:01:49 +00:00
legalize-fsin.mir
…
legalize-fsqrt.mir
…
legalize-fsub.mir
…
legalize-icmp.mir
…
legalize-implicit-def-s1025.mir
…
legalize-implicit-def.mir
Reland "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)" (#109958)
2024-09-25 13:02:29 +02:00
legalize-insert-vector-elt.mir
Reland "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)" (#109958)
2024-09-25 13:02:29 +02:00
legalize-insert.mir
…
legalize-intrinsic-amdgcn-fdiv-fast.mir
…
legalize-intrinsic-round.mir
…
legalize-intrinsic-trunc.mir
…
legalize-inttoptr.mir
…
legalize-jump-table.mir
…
legalize-llvm.amdgcn.image.atomic.dim.a16.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
legalize-llvm.amdgcn.image.dim.a16.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
legalize-llvm.amdgcn.image.load.2d.d16.ll
…
legalize-llvm.amdgcn.image.load.2d.ll
…
legalize-llvm.amdgcn.image.load.2darraymsaa.ll
…
legalize-llvm.amdgcn.image.load.3d.ll
…
legalize-llvm.amdgcn.image.sample.a16.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
legalize-llvm.amdgcn.image.sample.d.ll
…
legalize-llvm.amdgcn.image.sample.g16.a16.ll
…
legalize-llvm.amdgcn.image.sample.g16.ll
…
legalize-llvm.amdgcn.image.store.2d.d16.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
legalize-llvm.amdgcn.s.buffer.load.mir
…
legalize-load-constant-32bit.mir
…
legalize-load-constant.mir
Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v3 (#114443)
2024-11-01 11:13:29 -05:00
legalize-load-flat.mir
Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v3 (#114443)
2024-11-01 11:13:29 -05:00
legalize-load-global.mir
Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v3 (#114443)
2024-11-01 11:13:29 -05:00
legalize-load-local.mir
Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v3 (#114443)
2024-11-01 11:13:29 -05:00
legalize-load-memory-metadata.mir
MachineVerifier: Fix check for range type (#124894)
2025-01-30 10:56:12 +07:00
legalize-load-private.mir
Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v3 (#114443)
2024-11-01 11:13:29 -05:00
legalize-lshr.mir
…
legalize-memcpy.mir
…
legalize-memcpyinline.mir
…
legalize-memmove.mir
…
legalize-memset.mir
…
legalize-merge-values-build-vector.mir
…
legalize-merge-values.mir
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)
2024-12-16 05:57:11 +00:00
legalize-mul.mir
…
legalize-or.mir
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)
2024-12-16 05:57:11 +00:00
legalize-phi.mir
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)
2024-12-16 05:57:11 +00:00
legalize-ptr-add.mir
…
legalize-ptrmask.mir
…
legalize-ptrtoint.mir
…
legalize-rotl-rotr.mir
…
legalize-sadde.mir
…
legalize-saddo.mir
…
legalize-saddsat.mir
…
legalize-sbfx.mir
…
legalize-sdiv.mir
…
legalize-select.mir
…
legalize-sext-inreg.mir
…
legalize-sext.mir
…
legalize-sextload-constant-32bit.mir
…
legalize-sextload-flat.mir
…
legalize-sextload-global.mir
…
legalize-sextload-local.mir
…
legalize-sextload-private.mir
…
legalize-shl.mir
…
legalize-shuffle-vector.mir
…
legalize-shuffle-vector.s16.mir
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)
2024-12-16 05:57:11 +00:00
legalize-sitofp.mir
…
legalize-smax.mir
…
legalize-smin.mir
…
legalize-smulh.mir
…
legalize-smulo.mir
…
legalize-srem.mir
…
legalize-sshlsat.mir
…
legalize-ssube.mir
…
legalize-ssubo.mir
…
legalize-ssubsat.mir
…
legalize-store-global.mir
Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v3 (#114443)
2024-11-01 11:13:29 -05:00
legalize-store.mir
…
legalize-strict_fsub.mir
…
legalize-sub.mir
…
legalize-trap-gfx11.mir
…
legalize-trap.mir
…
legalize-trunc.mir
[GlobalISel] Combine unmerge(unmerge()) if the result is legal. (#109606)
2024-09-25 07:04:09 +01:00
legalize-uadde.mir
…
legalize-uaddo.mir
…
legalize-uaddsat.mir
…
legalize-ubfx.mir
…
legalize-udiv.mir
…
legalize-uitofp.mir
…
legalize-umax.mir
…
legalize-umin.mir
…
legalize-umulh.mir
…
legalize-umulo.mir
…
legalize-unmerge-values.mir
…
legalize-urem.mir
…
legalize-ushlsat.mir
…
legalize-usube.mir
…
legalize-usubo.mir
…
legalize-usubsat.mir
…
legalize-vector-args-gfx7.mir
…
legalize-vector-args-gfx8-plus.mir
…
legalize-xor.mir
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)
2024-12-16 05:57:11 +00:00
legalize-zext.mir
[GlobalISel] Use replaceRegOrBuildCopy when legalizer-combining s/zext(undef) (#119850)
2024-12-16 05:57:11 +00:00
legalize-zextload-constant-32bit.mir
…
legalize-zextload-flat.mir
…
legalize-zextload-global.mir
…
legalize-zextload-local.mir
…
legalize-zextload-private.mir
…
llvm.abs.ll
…
llvm.amdgcn.ballot.i32.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.ballot.i64.ll
AMDGPU/GlobalISel: Fix inst-selection of ballot (#109986)
2024-10-11 11:40:27 +02:00
llvm.amdgcn.dispatch.ptr.ll
…
llvm.amdgcn.div.fmas.ll
AMDGPU/GlobalISel: Restore disabled test (#129001)
2025-02-28 17:24:28 +07:00
llvm.amdgcn.div.scale.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.end.cf.i32.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.end.cf.i64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.fdot2.ll
…
llvm.amdgcn.fmul.legacy.ll
…
llvm.amdgcn.global.atomic.csub.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.if.break.i32.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.if.break.i64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.image.atomic.dim.a16.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
llvm.amdgcn.image.atomic.dim.ll
…
llvm.amdgcn.image.atomic.dim.mir
[AMDGPU][MC] Fix disassembler problem for image_atomic with TFE (#112622)
2024-10-24 16:19:18 -07:00
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
llvm.amdgcn.image.gather4.dim.ll
…
llvm.amdgcn.image.gather4.o.dim.ll
…
llvm.amdgcn.image.getresinfo.a16.ll
…
llvm.amdgcn.image.getresinfo.ll
…
llvm.amdgcn.image.load.1d.d16.ll
…
llvm.amdgcn.image.load.1d.ll
…
llvm.amdgcn.image.load.2d.ll
…
llvm.amdgcn.image.load.2darraymsaa.a16.ll
…
llvm.amdgcn.image.load.2darraymsaa.ll
…
llvm.amdgcn.image.load.3d.a16.ll
[AMDGPU] Decrease default NSA threshold from 3 to 2 (#116624)
2024-11-19 15:54:27 +00:00
llvm.amdgcn.image.load.3d.ll
…
llvm.amdgcn.image.sample.cd.g16.ll
…
llvm.amdgcn.image.sample.g16.ll
…
llvm.amdgcn.image.store.2d.d16.ll
…
llvm.amdgcn.image.store.2d.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.implicit.ptr.buffer.ll
…
llvm.amdgcn.interp.inreg.ll
[AMDGPU] Add some more GFX12 test coverage (#120581)
2024-12-23 09:42:52 +00:00
llvm.amdgcn.interp.p1.f16.ll
…
llvm.amdgcn.intersect_ray.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.kernarg.segment.ptr.ll
…
llvm.amdgcn.make.buffer.rsrc.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.mfma.gfx90a.ll
AMDGPU: Try to perform copy to agpr from reg_sequence at the copy (#129463)
2025-03-04 14:41:56 +07:00
llvm.amdgcn.mov.dpp.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.queue.ptr.ll
…
llvm.amdgcn.raw.buffer.atomic.add.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
…
llvm.amdgcn.raw.buffer.atomic.fadd.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.buffer.load.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.buffer.load.format.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.buffer.load.tfe.ll
…
llvm.amdgcn.raw.buffer.store.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.buffer.store.format.f32.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.buffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
…
llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.load.format.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.buffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.tbuffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.ptr.tbuffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.tbuffer.load.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.tbuffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.tbuffer.store.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.tbuffer.store.i8.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.raw.tbuffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.rsq.clamp.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
llvm.amdgcn.s.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.s.setreg.ll
…
llvm.amdgcn.s.sleep.ll
…
llvm.amdgcn.sbfe.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.sdot2.ll
…
llvm.amdgcn.sdot4.ll
…
llvm.amdgcn.sdot8.ll
…
llvm.amdgcn.set.inactive.ll
[GISel] Explicitly disable BF16 tablegen patterns. (#124113)
2025-01-27 22:21:12 +00:00
llvm.amdgcn.softwqm.ll
…
llvm.amdgcn.struct.buffer.atomic.add.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
…
llvm.amdgcn.struct.buffer.atomic.fadd.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.buffer.load.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.buffer.load.format.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.buffer.load.tfe.ll
…
llvm.amdgcn.struct.buffer.store.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.buffer.store.format.f32.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.buffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
…
llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.load.format.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.buffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.ptr.tbuffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.tbuffer.load.f16.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.struct.tbuffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
llvm.amdgcn.sudot4.ll
…
llvm.amdgcn.sudot8.ll
…
llvm.amdgcn.trig.preop.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.ubfe.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.udot2.ll
…
llvm.amdgcn.udot4.ll
…
llvm.amdgcn.udot8.ll
…
llvm.amdgcn.update.dpp.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
llvm.amdgcn.wmma_32.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.wmma_64.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.workgroup.id.ll
…
llvm.amdgcn.workitem.id.ll
…
llvm.amdgcn.wqm.demote.ll
[AMDGPU] Fix computed kill mask (#122736)
2025-01-14 10:00:40 +01:00
llvm.amdgcn.wqm.ll
…
llvm.amdgcn.writelane.ll
…
llvm.amdgcn.wwm.ll
…
llvm.memcpy.inline.ll
…
llvm.memcpy.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
llvm.memmove.ll
…
llvm.memset.ll
…
llvm.powi.ll
[AMDGPU] [GlobalIsel] Combine Fmul with Select into ldexp instruction. (#120104)
2025-01-06 17:42:38 +05:30
load-constant32bit.ll
…
load-constant.96.ll
…
load-legalize-range-metadata.ll
…
load-local.96.ll
AMDGPU/GlobalISel: Insert m0 initialization before sextload/zextload (#111720)
2024-10-10 14:01:49 +04:00
load-local.128.ll
AMDGPU/GlobalISel: Insert m0 initialization before sextload/zextload (#111720)
2024-10-10 14:01:49 +04:00
load-unaligned.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
localizer-wrong-insert-point.mir
…
localizer.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
lshr.ll
[GISel] Fold shifts to constant result. (#123510)
2025-01-21 05:10:45 -08:00
madmix-constant-bus-violation.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
madmix-constant-bus-violation.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
memory-legalizer-atomic-fence.ll
…
merge-buffer-stores.ll
…
minmaxabs.ll
…
mmra.ll
[AMDGPU,test] Change llc -march= to -mtriple=
2024-12-15 10:54:21 -08:00
mubuf-global.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
mul-known-bits.i64.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
mul-known-bits.i64.mir
…
mul.ll
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
mul.v2i16.ll
…
no-cse-nonlocal-convergent-instrs.mir
[CodeGen][NewPM] Port MachineCSE pass to new pass manager. (#106605)
2024-09-04 18:54:07 +05:30
no-ctlz-from-umul-to-lshr-in-postlegalizer.ll
[GlobalISel] Check whether G_CTLZ is legal in matchUMulHToLShr (#126457)
2025-02-10 00:11:09 -05:00
no-ctlz-from-umul-to-lshr-in-postlegalizer.mir
[GlobalISel] Check whether G_CTLZ is legal in matchUMulHToLShr (#126457)
2025-02-10 00:11:09 -05:00
no-legalize-atomic.mir
…
non-entry-alloca.ll
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
orn2.ll
AMDGPU: Fix overly conservative immediate operand check (#127563)
2025-02-27 08:42:09 +07:00
postlegalizer-combiner-buildvector-identities.mir
…
postlegalizer-combiner-divrem.mir
…
postlegalizer-combiner-fcanonicalize.mir
…
postlegalizer-combiner-freeze.mir
…
postlegalizer-combiner-reassoc.mir
…
postlegalizer-combiner-sextload-from-sextinreg.mir
GlobalISel: Fix combine duplicating atomic loads (#111730)
2024-10-31 07:55:12 -07:00
postlegalizer-combiner-trunc-bitcast-buildvector.mir
…
postlegalizer-combiner-unmerge-undef.mir
…
postlegalizer-combiner-zextload-from-and.mir
…
postlegalizercombiner-and.mir
[AMDGPU][GlobalISel] Disable fixed-point iteration in all Combiners (#105517)
2024-08-22 17:14:53 +01:00
postlegalizercombiner-ashr.mir
…
postlegalizercombiner-load-and-mask.mir
…
postlegalizercombiner-lshr.mir
…
postlegalizercombiner-mul.mir
…
postlegalizercombiner-sbfx.mir
…
postlegalizercombiner-select.mir
…
postlegalizercombiner-shl.mir
…
postlegalizercombiner-ubfx.mir
…
prelegalizer-combiner-divrem.mir
…
prelegalizer-combiner-fptrunc_fpext.mir
…
prelegalizer-combiner-redundant-bitcast.mir
…
prelegalizer-combiner-sext_inreg-to-and.mir
…
promote-dependency-on-invariant-result.ll
GlobalISel: Fix defined register of invariant.start (#125664)
2025-02-04 23:59:03 +07:00
regbankcombiner-clamp-fmed3-const.mir
…
regbankcombiner-clamp-minmax-const.mir
…
regbankcombiner-fmed3-minmax-const.mir
…
regbankcombiner-redundant-and.mir
AMDGPU/GlobalISel: Run redundant_and combine in RegBankCombiner (#112353)
2024-10-16 09:43:16 +02:00
regbankcombiner-smed3.mir
…
regbankcombiner-umed3.mir
…
regbankselect-abs.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-add.s16.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-add.s32.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-add.v2s16.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn-exp-compr.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn-exp.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn-s-buffer-load.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ballot.i64.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.class.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.cvt.pkrtz.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.div.fmas.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.div.scale.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.ds.append.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.bpermute.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.ds.consume.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.gws.init.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.gws.sema.v.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.ordered.add.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.ordered.swap.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.ds.permute.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.ds.swizzle.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.else.32.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.else.64.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.fcmp.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.fmul.legacy.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.groupstaticsize.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.icmp.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.image.load.1d.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.image.sample.1d.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.interp.mov.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.interp.p1.f16.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.interp.p1.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.interp.p2.f16.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.interp.p2.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.kernarg.segment.ptr.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.kill.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.lds.direct.load.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.lds.param.load.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.live.mask.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.mfma.gfx90a.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.mfma.gfx942.mir
[AMDGPU][NFC] Replace gfx940 and gfx941 with gfx942 in llvm/test (#125711)
2025-02-13 15:17:12 +01:00
regbankselect-amdgcn.mfma.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.ps.live.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.raw.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.raw.ptr.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.readfirstlane.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.readlane.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.s.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.s.buffer.load.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.s.getpc.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.s.getreg.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.s.memrealtime.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.s.memtime.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.s.sendmsg.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.s.sendmsghalt.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.struct.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.struct.buffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.struct.ptr.buffer.load.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.struct.ptr.buffer.store.ll
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.update.dpp.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.wqm.demote.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.wqm.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.wqm.vote.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgcn.writelane.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-amdgcn.wwm.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgpu-ffbh-u32.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgpu-ffbl-b32.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-amdgpu-wave-address.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-and-s1.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-and.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-anyext.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-ashr.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-assert-align.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-assert-zext.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomic-cmpxchg.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-add.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-and.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-fadd.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-max.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-min.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-or.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-sub.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-umax.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-umin.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-xchg.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-atomicrmw-xor.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-bitcast.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-bitreverse.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-block-addr.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-brcond.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-bswap.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-build-vector.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-concat-vector.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-constant.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-copy.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-ctlz-zero-undef.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-ctpop.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-cttz-zero-undef.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-default.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-dyn-stackalloc.mir
[AMDGPU] Support divergent sized dynamic alloca (#121148)
2025-01-06 12:28:24 +07:00
regbankselect-extract-vector-elt.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-extract.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fabs.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fadd.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fcanonicalize.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fceil.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fcmp.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fexp2.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-flog2.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fma.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fmul.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fneg.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fpext.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fptosi.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fptoui.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fptrunc.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-frame-index.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-freeze.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fshr.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fsqrt.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-fsub.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-icmp.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-icmp.s16.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-illegal-copy.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-implicit-def.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-insert-vector-elt.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-insert.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-intrinsic-trunc.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-inttoptr.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-load.mir
AMDGPU/GlobalISel: RegBankLegalize rules for load (#112882)
2025-01-24 12:36:41 +01:00
regbankselect-lshr.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-mad_64_32.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-merge-values.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-mui-regbanklegalize.mir
MachineUniformityAnalysis: Improve isConstantOrUndefValuePhi (#112866)
2025-01-24 12:43:40 +01:00
regbankselect-mui-regbankselect.mir
MachineUniformityAnalysis: Improve isConstantOrUndefValuePhi (#112866)
2025-01-24 12:43:40 +01:00
regbankselect-mui-salu-float.ll
AMDGPU/GlobalISel: AMDGPURegBankLegalize (#112864)
2025-01-24 12:12:45 +01:00
regbankselect-mui-salu-float.mir
AMDGPU/GlobalISel: AMDGPURegBankLegalize (#112864)
2025-01-24 12:12:45 +01:00
regbankselect-mui.ll
[MachineScheduler] Fix physreg dependencies of ExitSU (#123541)
2025-02-01 20:40:50 +03:00
regbankselect-mui.mir
MachineUniformityAnalysis: Improve isConstantOrUndefValuePhi (#112866)
2025-01-24 12:43:40 +01:00
regbankselect-mul.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-or.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-phi-s1.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-phi.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-pseudo-scalar-transcendental.mir
…
regbankselect-ptr-add.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-ptrmask.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-ptrtoint.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-reg-sequence.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-sadde.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-salu-float.mir
…
regbankselect-sbfx.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-select.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-sext-inreg.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-sext.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-sextload.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-shl.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-sitofp.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-smax.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-smin.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-smulh.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-split-scalar-load-metadata.mir
[GlobalISel] Catching inconsistencies in load memory, result, and range metadata type (#121247)
2025-01-28 20:54:34 +07:00
regbankselect-ssube.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-sub.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-trunc.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-uadde.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-uaddo.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-ubfx.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-uitofp.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-umax.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-umin.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-umulh.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-uniform-load-noclobber.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-unmerge-values.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-usube.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-usubo.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-waterfall-agpr.mir
[AMDGPU] Do not allow M0 as v_readfirstlane_b32 dst (#128851)
2025-02-26 13:14:03 +01:00
regbankselect-widen-scalar-loads.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-xor.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-zext.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
regbankselect-zextload.mir
AMDGPU/GlobalISel: RegBankLegalize rules for load (#112882)
2025-01-24 12:36:41 +01:00
regbankselect.mir
Revert "AMDGPU/GlobalISel: Add stub custom regbankselect pass" (#113913)
2024-11-27 13:16:22 -05:00
saddsat.ll
[AMDGPU] Account for existing SDWA selections (#123221)
2025-03-03 17:07:28 +01:00
sbfx.ll
…
sdiv.i32.ll
[GISel] Fold shifts to constant result. (#123510)
2025-01-21 05:10:45 -08:00
sdiv.i64.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
sdivrem.ll
PeepholeOpt: Allow introducing subregister uses on reg_sequence (#127052)
2025-02-22 09:16:14 +07:00
select-to-fmin-fmax.ll
…
sext_inreg.ll
…
shader-epilogs.ll
…
shl-ext-reduce.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
shl.ll
Recommit "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C) (#114309)"
2024-11-08 10:21:46 -08:00
shlN_add.ll
…
smed3.ll
…
smrd.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
srem.i32.ll
[GISel] Fold shifts to constant result. (#123510)
2025-01-21 05:10:45 -08:00
srem.i64.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
ssubsat.ll
[AMDGPU] Account for existing SDWA selections (#123221)
2025-03-03 17:07:28 +01:00
store-local.96.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
store-local.128.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
strict_fma.f16.ll
…
strict_fma.f32.ll
…
strict_fma.f64.ll
…
sub.v2i16.ll
Recommit "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C) (#114309)"
2024-11-08 10:21:46 -08:00
subo.ll
…
trunc.ll
…
twoaddr-extract-dyn-v7f64.mir
[llc] Provide opt like verifier options (#106665)
2024-09-04 17:37:34 +08:00
uaddsat.ll
[AMDGPU] Account for existing SDWA selections (#123221)
2025-03-03 17:07:28 +01:00
ubfx.ll
…
udiv.i32.ll
…
udiv.i64.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
udivrem.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
umed3.ll
…
unsupported-load.ll
…
unsupported-ptr-add.ll
…
urem.i32.ll
Recommit "[GISel][AArch64][AMDGPU][RISCV] Canonicalize (sub X, C) -> (add X, -C) (#114309)"
2024-11-08 10:21:46 -08:00
urem.i64.ll
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
usubsat.ll
[AMDGPU] Account for existing SDWA selections (#123221)
2025-03-03 17:07:28 +01:00
v_bfe_i32.ll
…
vni8-across-blocks.ll
Reapply "[AMDGPU] Still set up the two SGPRs for queue ptr even it is COV5 (#112403)"
2024-11-08 20:21:16 -05:00
widen-i8-i16-scalar-loads.ll
[GISel] Fold shifts to constant result. (#123510)
2025-01-21 05:10:45 -08:00
wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w32-imm.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w32-iu-modifiers.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w32-swmmac-index_key.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w32.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64-imm.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64-iu-modifiers.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64-swmmac-index_key.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
xnor.ll
AMDGPU: Fix overly conservative immediate operand check (#127563)
2025-02-27 08:42:09 +07:00
zextload.ll
…