3e53aeae94
This adds handling of s_add_u32, which is handled and removes handling of
s_or_b32 and s_and_b32, which are not. I was working on handling them
in #102345, but need to finish that patch. This fixes a regression
exposed by a3165398db where the
final instruction would use two literals.
98 lines
4.3 KiB
LLVM
98 lines
4.3 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SCRATCH128K %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SCRATCH128K %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SCRATCH256K %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -mattr=+wavefrontsize64 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SCRATCH128K %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SCRATCH256K %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -mattr=+wavefrontsize64 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SCRATCH1024K %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -amdgpu-enable-vopd=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SCRATCH2048K %s
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; GCN-LABEL: {{^}}scratch_buffer_known_high_masklo16:
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; GCN: s_mov_b32 [[FI:s[0-9]+]], 0{{$}}
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; GCN: s_and_b32 s{{[0-9]+}}, [[FI]], 0xfffc
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; GCN: v_mov_b32_e32 [[VFI:v[0-9]+]], [[FI]]{{$}}
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; GCN: {{flat|global}}_store_{{dword|b32}} v[{{[0-9]+:[0-9]+}}], [[VFI]]
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define amdgpu_kernel void @scratch_buffer_known_high_masklo16() {
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%alloca = alloca i32, align 4, addrspace(5)
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store volatile i32 15, ptr addrspace(5) %alloca
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%toint = ptrtoint ptr addrspace(5) %alloca to i32
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%masked = and i32 %toint, 65535
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store volatile i32 %masked, ptr addrspace(1) undef
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ret void
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}
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; GCN-LABEL: {{^}}scratch_buffer_known_high_masklo17:
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; SCRATCH256K: s_mov_b32 [[FI:s[0-9]+]], 0{{$}}
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; SCRATCH256K: s_and_b32 s{{[0-9]+}}, [[FI]], 0x1fffc
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; SCRATCH1024K: s_mov_b32 [[FI:s[0-9]+]], 0{{$}}
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; SCRATCH1024K: s_and_b32 s{{[0-9]+}}, [[FI]], 0x1fffc
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; SCRATCH2048K: s_mov_b32 [[FI:s[0-9]+]], 0{{$}}
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; SCRATCH2048K: s_and_b32 s{{[0-9]+}}, [[FI]], 0x1fffc
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; GCN: {{flat|global}}_store_{{dword|b32}} v[{{[0-9]+:[0-9]+}}],
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define amdgpu_kernel void @scratch_buffer_known_high_masklo17() {
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%alloca = alloca i32, align 4, addrspace(5)
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store volatile i32 15, ptr addrspace(5) %alloca
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%toint = ptrtoint ptr addrspace(5) %alloca to i32
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%masked = and i32 %toint, 131071
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store volatile i32 %masked, ptr addrspace(1) undef
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ret void
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}
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; GCN-LABEL: {{^}}scratch_buffer_known_high_masklo18:
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; SCRATCH128K: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
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; SCRATCH256K: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
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; SCRATCH128K-NOT: and_b32
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; SCRATCH256K-NOT: and_b32
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; SCRATCH1024K: s_mov_b32 [[FI:s[0-9]+]], 0{{$}}
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; SCRATCH1024K: s_and_b32 s{{[0-9]+}}, [[FI]], 0x3fffc
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; SCRATCH2048K: s_mov_b32 [[FI:s[0-9]+]], 0{{$}}
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; SCRATCH2048K: s_and_b32 s{{[0-9]+}}, [[FI]], 0x3fffc
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; GCN: {{flat|global}}_store_{{dword|b32}} v[{{[0-9]+:[0-9]+}}],
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define amdgpu_kernel void @scratch_buffer_known_high_masklo18() {
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%alloca = alloca i32, align 4, addrspace(5)
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store volatile i32 15, ptr addrspace(5) %alloca
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%toint = ptrtoint ptr addrspace(5) %alloca to i32
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%masked = and i32 %toint, 262143
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store volatile i32 %masked, ptr addrspace(1) undef
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ret void
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}
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; GCN-LABEL: {{^}}scratch_buffer_known_high_masklo20:
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; SCRATCH128K: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
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; SCRATCH256K: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
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; SCRATCH1024K: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
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; SCRATCH128K-NOT: and_b32
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; SCRATCH256K-NOT: and_b32
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; SCRATCH1024K-NOT: and_b32
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; SCRATCH2048K: s_mov_b32 [[FI:s[0-9]+]], 0{{$}}
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; SCRATCH2048K: s_and_b32 s{{[0-9]+}}, [[FI]], 0xffffc
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; GCN: {{flat|global}}_store_{{dword|b32}} v[{{[0-9]+:[0-9]+}}],
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define amdgpu_kernel void @scratch_buffer_known_high_masklo20() {
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%alloca = alloca i32, align 4, addrspace(5)
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store volatile i32 15, ptr addrspace(5) %alloca
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%toint = ptrtoint ptr addrspace(5) %alloca to i32
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%masked = and i32 %toint, 1048575
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store volatile i32 %masked, ptr addrspace(1) undef
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ret void
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}
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; GCN-LABEL: {{^}}scratch_buffer_known_high_masklo21:
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; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 0{{$}}
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; GCN-NOT: and_b32
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; GCN: {{flat|global}}_store_{{dword|b32}} v[{{[0-9]+:[0-9]+}}],
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define amdgpu_kernel void @scratch_buffer_known_high_masklo21() {
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%alloca = alloca i32, align 4, addrspace(5)
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store volatile i32 15, ptr addrspace(5) %alloca
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%toint = ptrtoint ptr addrspace(5) %alloca to i32
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%masked = and i32 %toint, 2097151
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store volatile i32 %masked, ptr addrspace(1) undef
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ret void
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}
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