c8ea114741
In gfx90a-gfx950, it's possible to emit MFMAs which use AGPRs or VGPRs
for vdst and src2. We do not want to do use the AGPR form, unless
required by register pressure as it requires cross bank register
copies from most other instructions. Currently we select the AGPR
or VGPR version depending on a crude heuristic for whether it's possible
AGPRs will be required. We really need the register allocation to
be complete to make a good decision, which is what this pass is for.
This adds the pass, but does not yet remove the selection patterns
for AGPRs. This is a WIP, and NFC-ish. It should be a no-op on any
currently selected code. It also does not yet trigger on the real
examples of interest, which require handling batches of MFMAs at
once.
220 lines
6.1 KiB
CMake
220 lines
6.1 KiB
CMake
add_llvm_component_group(AMDGPU)
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set(LLVM_TARGET_DEFINITIONS AMDGPU.td)
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tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)
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tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM AMDGPUGenCallingConv.inc -gen-callingconv)
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tablegen(LLVM AMDGPUGenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler)
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tablegen(LLVM AMDGPUGenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering)
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tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank)
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tablegen(LLVM AMDGPUGenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM AMDGPUGenSearchableTables.inc -gen-searchable-tables)
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tablegen(LLVM AMDGPUGenSubtargetInfo.inc -gen-subtarget)
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set(LLVM_TARGET_DEFINITIONS AMDGPUGISel.td)
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tablegen(LLVM AMDGPUGenGlobalISel.inc -gen-global-isel)
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tablegen(LLVM AMDGPUGenPreLegalizeGICombiner.inc -gen-global-isel-combiner
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-combiners="AMDGPUPreLegalizerCombiner")
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tablegen(LLVM AMDGPUGenPostLegalizeGICombiner.inc -gen-global-isel-combiner
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-combiners="AMDGPUPostLegalizerCombiner")
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tablegen(LLVM AMDGPUGenRegBankGICombiner.inc -gen-global-isel-combiner
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-combiners="AMDGPURegBankCombiner")
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set(LLVM_TARGET_DEFINITIONS R600.td)
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tablegen(LLVM R600GenAsmWriter.inc -gen-asm-writer)
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tablegen(LLVM R600GenCallingConv.inc -gen-callingconv)
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tablegen(LLVM R600GenDAGISel.inc -gen-dag-isel)
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tablegen(LLVM R600GenDFAPacketizer.inc -gen-dfa-packetizer)
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tablegen(LLVM R600GenInstrInfo.inc -gen-instr-info)
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tablegen(LLVM R600GenMCCodeEmitter.inc -gen-emitter)
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tablegen(LLVM R600GenRegisterInfo.inc -gen-register-info)
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tablegen(LLVM R600GenSubtargetInfo.inc -gen-subtarget)
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add_public_tablegen_target(AMDGPUCommonTableGen)
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set(LLVM_TARGET_DEFINITIONS InstCombineTables.td)
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tablegen(LLVM InstCombineTables.inc -gen-searchable-tables)
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add_public_tablegen_target(InstCombineTableGen)
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add_llvm_target(AMDGPUCodeGen
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AMDGPUAliasAnalysis.cpp
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AMDGPUAlwaysInlinePass.cpp
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AMDGPUAnnotateUniformValues.cpp
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AMDGPUArgumentUsageInfo.cpp
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AMDGPUAsanInstrumentation.cpp
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AMDGPUAsmPrinter.cpp
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AMDGPUAtomicOptimizer.cpp
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AMDGPUAttributor.cpp
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AMDGPUCallLowering.cpp
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AMDGPUCodeGenPrepare.cpp
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AMDGPUCombinerHelper.cpp
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AMDGPUCtorDtorLowering.cpp
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AMDGPUExportClustering.cpp
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AMDGPUExportKernelRuntimeHandles.cpp
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AMDGPUFrameLowering.cpp
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AMDGPUGlobalISelDivergenceLowering.cpp
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AMDGPUGlobalISelUtils.cpp
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AMDGPUHSAMetadataStreamer.cpp
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AMDGPUInsertDelayAlu.cpp
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AMDGPUInstCombineIntrinsic.cpp
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AMDGPUInstrInfo.cpp
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AMDGPUInstructionSelector.cpp
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AMDGPUISelDAGToDAG.cpp
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AMDGPUISelLowering.cpp
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AMDGPULateCodeGenPrepare.cpp
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AMDGPULegalizerInfo.cpp
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AMDGPULibCalls.cpp
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AMDGPUImageIntrinsicOptimizer.cpp
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AMDGPULibFunc.cpp
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AMDGPULowerBufferFatPointers.cpp
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AMDGPULowerKernelArguments.cpp
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AMDGPULowerKernelAttributes.cpp
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AMDGPULowerModuleLDSPass.cpp
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AMDGPUSwLowerLDS.cpp
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AMDGPUMachineFunction.cpp
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AMDGPUMachineModuleInfo.cpp
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AMDGPUMacroFusion.cpp
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AMDGPUMCInstLower.cpp
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AMDGPUMemoryUtils.cpp
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AMDGPUIGroupLP.cpp
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AMDGPUMCResourceInfo.cpp
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AMDGPUMarkLastScratchLoad.cpp
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AMDGPUMIRFormatter.cpp
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AMDGPUPerfHintAnalysis.cpp
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AMDGPUPostLegalizerCombiner.cpp
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AMDGPUPreLegalizerCombiner.cpp
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AMDGPUPreloadKernArgProlog.cpp
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AMDGPUPreloadKernelArguments.cpp
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AMDGPUPrintfRuntimeBinding.cpp
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AMDGPUPromoteAlloca.cpp
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AMDGPUPromoteKernelArguments.cpp
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AMDGPURegBankCombiner.cpp
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AMDGPURegBankLegalize.cpp
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AMDGPURegBankLegalizeHelper.cpp
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AMDGPURegBankLegalizeRules.cpp
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AMDGPURegBankSelect.cpp
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AMDGPURegisterBankInfo.cpp
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AMDGPURemoveIncompatibleFunctions.cpp
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AMDGPUReserveWWMRegs.cpp
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AMDGPUResourceUsageAnalysis.cpp
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AMDGPURewriteAGPRCopyMFMA.cpp
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AMDGPURewriteOutArguments.cpp
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AMDGPURewriteUndefForPHI.cpp
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AMDGPUSelectionDAGInfo.cpp
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AMDGPUSetWavePriority.cpp
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AMDGPUSplitModule.cpp
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AMDGPUSubtarget.cpp
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AMDGPUTargetMachine.cpp
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AMDGPUTargetObjectFile.cpp
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AMDGPUTargetTransformInfo.cpp
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AMDGPUWaitSGPRHazards.cpp
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AMDGPUUnifyDivergentExitNodes.cpp
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AMDGPUUnifyMetadata.cpp
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R600MachineCFGStructurizer.cpp
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GCNCreateVOPD.cpp
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GCNDPPCombine.cpp
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GCNHazardRecognizer.cpp
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GCNILPSched.cpp
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GCNIterativeScheduler.cpp
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GCNMinRegStrategy.cpp
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GCNNSAReassign.cpp
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GCNPreRAOptimizations.cpp
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GCNPreRALongBranchReg.cpp
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GCNRegPressure.cpp
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GCNRewritePartialRegUses.cpp
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GCNSchedStrategy.cpp
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GCNSubtarget.cpp
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GCNVOPDUtils.cpp
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R600AsmPrinter.cpp
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R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600FrameLowering.cpp
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R600InstrInfo.cpp
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R600ISelDAGToDAG.cpp
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R600ISelLowering.cpp
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R600MachineFunctionInfo.cpp
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R600MachineScheduler.cpp
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R600MCInstLower.cpp
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R600OpenCLImageTypeLoweringPass.cpp
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R600OptimizeVectorRegisters.cpp
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R600Packetizer.cpp
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R600RegisterInfo.cpp
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R600Subtarget.cpp
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R600TargetMachine.cpp
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R600TargetTransformInfo.cpp
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SIAnnotateControlFlow.cpp
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SIFixSGPRCopies.cpp
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SIFixVGPRCopies.cpp
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SIFoldOperands.cpp
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SIFormMemoryClauses.cpp
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SIFrameLowering.cpp
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SIInsertHardClauses.cpp
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SIInsertWaitcnts.cpp
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SIInstrInfo.cpp
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SIISelLowering.cpp
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SILateBranchLowering.cpp
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SILoadStoreOptimizer.cpp
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SILowerControlFlow.cpp
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SILowerI1Copies.cpp
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SILowerWWMCopies.cpp
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SILowerSGPRSpills.cpp
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SIMachineFunctionInfo.cpp
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SIMachineScheduler.cpp
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SIMemoryLegalizer.cpp
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SIModeRegister.cpp
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SIModeRegisterDefaults.cpp
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SIOptimizeExecMasking.cpp
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SIOptimizeExecMaskingPreRA.cpp
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SIOptimizeVGPRLiveRange.cpp
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SIPeepholeSDWA.cpp
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SIPostRABundler.cpp
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SIPreAllocateWWMRegs.cpp
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SIPreEmitPeephole.cpp
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SIProgramInfo.cpp
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SIRegisterInfo.cpp
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SIShrinkInstructions.cpp
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SIWholeQuadMode.cpp
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LINK_COMPONENTS
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AMDGPUDesc
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AMDGPUInfo
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AMDGPUUtils
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Analysis
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AsmPrinter
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BinaryFormat
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CodeGen
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CodeGenTypes
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Core
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GlobalISel
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HipStdPar
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IPO
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IRPrinter
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Instrumentation
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MC
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MIRParser
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Passes
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Scalar
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SelectionDAG
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Support
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Target
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TargetParser
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TransformUtils
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Vectorize
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ADD_TO_COMPONENT
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AMDGPU
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)
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add_subdirectory(AsmParser)
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add_subdirectory(Disassembler)
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add_subdirectory(MCA)
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add_subdirectory(MCTargetDesc)
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add_subdirectory(TargetInfo)
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add_subdirectory(Utils)
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