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clang-p2996/llvm/lib/Target/AMDGPU
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Jay Foad ad715beca1 [AMDGPU] Remove HasSampler variable. NFC. (#146682) 
Putting the complex condition in a variable does not help readability.
It is simpler to use separate `if`s.
2025-07-02 15:44:32 +01:00
..
AsmParser
MCParsedAsmOperand::print: Add MCAsmInfo parameter
2025-06-28 12:05:33 -07:00
Disassembler
[AMDGPU] Add the support for v_cvt_f32_bf16 on gfx1250 (#145632)
2025-06-25 16:02:40 -04:00
MCA
[llvm] annotate interfaces in llvm/Target for DLL export (#143615)
2025-06-17 13:28:45 -07:00
MCTargetDesc
MC: Rename initializeVariantKinds to initializeAtSpecifiers
2025-06-26 22:46:20 -07:00
TargetInfo
[llvm] annotate interfaces in llvm/Target for DLL export (#143615)
2025-06-17 13:28:45 -07:00
Utils
[AMDGPU] Remove an unnecessary cast (NFC) (#146548)
2025-07-01 10:42:22 -07:00
AMDGPU.h
AMDGPU: Introduce a pass to replace VGPR MFMAs with AGPR (#145024)
2025-06-27 21:05:03 +09:00
AMDGPU.td
AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive_rtn_b64 (#146409)
2025-07-01 11:08:49 -07:00
AMDGPUAliasAnalysis.cpp
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
AMDGPUAliasAnalysis.h
…
AMDGPUAlwaysInlinePass.cpp
[NFC][AMDGPU] Replace direct arch comparison with isAMDGCN() (#131357)
2025-03-14 14:21:44 -04:00
AMDGPUAnnotateUniformValues.cpp
…
AMDGPUArgumentUsageInfo.cpp
…
AMDGPUArgumentUsageInfo.h
[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)
2025-01-10 11:39:02 -08:00
AMDGPUAsanInstrumentation.cpp
[IRBuilder] Add new overload for CreateIntrinsic (#131942)
2025-03-31 08:10:34 -07:00
AMDGPUAsanInstrumentation.h
…
AMDGPUAsmPrinter.cpp
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
AMDGPUAsmPrinter.h
Register assembly printer passes (#138348)
2025-05-06 18:01:17 -07:00
AMDGPUAtomicOptimizer.cpp
[IRBuilder] Add new overload for CreateIntrinsic (#131942)
2025-03-31 08:10:34 -07:00
AMDGPUAttributes.def
Reapply "[AMDGPU] Infer amdgpu-no-flat-scratch-init attribute in AMDGPUAttributor (#94647)" (#118907)
2024-12-09 16:44:48 -08:00
AMDGPUAttributor.cpp
AMDGPU: Remove legacy pass manager version of AMDGPUAttributor (#145262)
2025-06-23 16:49:46 +09:00
AMDGPUCallingConv.td
[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)
2025-03-08 09:28:20 -05:00
AMDGPUCallLowering.cpp
[AMDGPU] Remove duplicated/confusing helpers. NFCI (#142598)
2025-06-05 11:19:20 +02:00
AMDGPUCallLowering.h
…
AMDGPUCodeGenPrepare.cpp
[ValueTracking] Make Depth last default arg (NFC) (#142384)
2025-06-03 17:12:24 +01:00
AMDGPUCombine.td
[AMDGPU] Canonicalize G_ZEXT of the shift amount in RegBankCombiner (#131792)
2025-05-14 10:48:51 +02:00
AMDGPUCombinerHelper.cpp
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
2025-03-29 11:51:29 +01:00
AMDGPUCombinerHelper.h
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
2025-03-29 11:51:29 +01:00
AMDGPUCtorDtorLowering.cpp
…
AMDGPUCtorDtorLowering.h
…
AMDGPUExportClustering.cpp
[AMDGPU] Remove unused includes (NFC) (#141376)
2025-05-24 14:48:46 -07:00
AMDGPUExportClustering.h
…
AMDGPUExportKernelRuntimeHandles.cpp
AMDGPU: Move enqueued block handling into clang (#128519)
2025-03-10 19:54:04 +07:00
AMDGPUExportKernelRuntimeHandles.h
AMDGPU: Move enqueued block handling into clang (#128519)
2025-03-10 19:54:04 +07:00
AMDGPUFeatures.td
…
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
…
AMDGPUGenRegisterBankInfo.def
…
AMDGPUGISel.td
…
AMDGPUGlobalISelDivergenceLowering.cpp
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
AMDGPUGlobalISelUtils.cpp
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
2025-03-29 11:51:29 +01:00
AMDGPUGlobalISelUtils.h
[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)
2025-03-29 11:51:29 +01:00
AMDGPUHSAMetadataStreamer.cpp
AMDGPU: Move enqueued block handling into clang (#128519)
2025-03-10 19:54:04 +07:00
AMDGPUHSAMetadataStreamer.h
AMDGPU: Move enqueued block handling into clang (#128519)
2025-03-10 19:54:04 +07:00
AMDGPUIGroupLP.cpp
Revert "[llvm][NFC] Use llvm::sort()" (#140668)
2025-05-20 11:27:03 +08:00
AMDGPUIGroupLP.h
…
AMDGPUImageIntrinsicOptimizer.cpp
[AMDGPU] Change placeholder from undef to poison (#130853)
2025-03-12 12:52:38 +00:00
AMDGPUInsertDelayAlu.cpp
[AMDGPU] Fix bad removal of s_delay_alu (#145728)
2025-06-27 16:15:10 +02:00
AMDGPUInstCombineIntrinsic.cpp
[AMDGPU] Fold fmed3 when inputs include infinity (#144824)
2025-06-24 21:44:17 +09:00
AMDGPUInstrInfo.cpp
AMDGPU: Remove AMDGPUInstrInfo class (#144984)
2025-06-20 18:26:56 +09:00
AMDGPUInstrInfo.h
AMDGPU: Remove AMDGPUInstrInfo class (#144984)
2025-06-20 18:26:56 +09:00
AMDGPUInstrInfo.td
[AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain (#130094)
2025-03-20 08:38:04 +01:00
AMDGPUInstructions.td
AMDGPU: Directly select minimumnum/maximumnum with ieee_mode=0 (#141903)
2025-06-18 00:27:41 +09:00
AMDGPUInstructionSelector.cpp
AMDGPU: Avoid report_fatal_error on ds ordered intrinsics (#145202)
2025-06-23 13:09:09 +09:00
AMDGPUInstructionSelector.h
Revert "[AMDGPU] Implement vop3p complex pattern optmization for gisel" (#136249)
2025-04-17 23:45:30 -04:00
AMDGPUISelDAGToDAG.cpp
AMDGPU: Remove AMDGPUInstrInfo class (#144984)
2025-06-20 18:26:56 +09:00
AMDGPUISelDAGToDAG.h
[AMDGPU] Add intrinsics and MIs for ds_bvh_stack_* (#130007)
2025-03-17 09:13:20 +01:00
AMDGPUISelLowering.cpp
[AMDGPU] Convert 64-bit sra to 32-bit if shift amt >= 32 (#144421)
2025-06-26 14:22:59 -04:00
AMDGPUISelLowering.h
AMDGPU][True16][CodeGen] FP_Round f64 to f16 in true16 (#128911)
2025-05-08 13:30:09 -04:00
AMDGPULateCodeGenPrepare.cpp
[ValueTracking] Make Depth last default arg (NFC) (#142384)
2025-06-03 17:12:24 +01:00
AMDGPULegalizerInfo.cpp
AMDGPU: Directly select minimumnum/maximumnum with ieee_mode=0 (#141903)
2025-06-18 00:27:41 +09:00
AMDGPULegalizerInfo.h
[AMDGPU] Support image_bvh8_intersect_ray instruction and intrinsic. (#130041)
2025-03-19 16:08:08 +01:00
AMDGPULibCalls.cpp
[ValueTracking] Make Depth last default arg (NFC) (#142384)
2025-06-03 17:12:24 +01:00
AMDGPULibFunc.cpp
[AMDGPU] Provide default value in get intrinsic param type (#122448)
2025-01-10 15:29:42 +01:00
AMDGPULibFunc.h
AMDGPU: Verify function type matches when matching libcalls (#119043)
2024-12-16 15:01:48 +09:00
AMDGPULowerBufferFatPointers.cpp
AMDGPU: Use reportFatalUsageError in AMDGPULowerBufferFatPointers (#145132)
2025-06-21 14:24:30 +09:00
AMDGPULowerKernelArguments.cpp
[AMDGPU] Move kernarg preload logic to separate pass (#130434)
2025-05-11 21:18:11 -07:00
AMDGPULowerKernelAttributes.cpp
[AMDGPU] Add a new function getIntegerPairAttribute (#133271)
2025-03-27 15:38:54 -04:00
AMDGPULowerModuleLDSPass.cpp
AMDGPU: Use reportFatalUsageError in AMDGPULowerModuleLDS (#145130)
2025-06-21 12:18:25 +09:00
AMDGPUMachineFunction.cpp
…
AMDGPUMachineFunction.h
…
AMDGPUMachineModuleInfo.cpp
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
AMDGPUMachineModuleInfo.h
…
AMDGPUMacroFusion.cpp
…
AMDGPUMacroFusion.h
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
2025-02-05 11:41:37 +05:30
AMDGPUMarkLastScratchLoad.cpp
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
AMDGPUMCInstLower.cpp
Reland [AMDGPU] Support block load/store for CSR #130013 (#137169)
2025-04-25 11:29:27 +02:00
AMDGPUMCInstLower.h
[AMDGPU][True16][CodeGen] reopen "FLAT_load using D16 pseudo instruction" (#127673)
2025-02-18 18:16:23 -05:00
AMDGPUMCResourceInfo.cpp
[AMDGPU] Flatten recursive register resource info propagation (#142766)
2025-06-12 14:35:28 +01:00
AMDGPUMCResourceInfo.h
[AMDGPU] Flatten recursive register resource info propagation (#142766)
2025-06-12 14:35:28 +01:00
AMDGPUMemoryUtils.cpp
AMDGPU: Use reportFatalUsageError for LDS mixed absolute addresses (#145135)
2025-06-21 23:54:27 +09:00
AMDGPUMemoryUtils.h
…
AMDGPUMIRFormatter.cpp
…
AMDGPUMIRFormatter.h
…
AMDGPUPassRegistry.def
AMDGPU: Introduce a pass to replace VGPR MFMAs with AGPR (#145024)
2025-06-27 21:05:03 +09:00
AMDGPUPerfHintAnalysis.cpp
…
AMDGPUPerfHintAnalysis.h
…
AMDGPUPostLegalizerCombiner.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
AMDGPUPredicateControl.td
…
AMDGPUPreLegalizerCombiner.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
AMDGPUPreloadKernArgProlog.cpp
[AMDGPU][NPM] Cleanup AMDGPUPassRegistry.def (#130071)
2025-04-17 10:08:22 +05:30
AMDGPUPreloadKernArgProlog.h
[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)
2025-01-10 11:39:02 -08:00
AMDGPUPreloadKernelArguments.cpp
[DebugInfo][RemoveDIs] Delete debug-info-format flag (#143746)
2025-06-12 11:51:58 +01:00
AMDGPUPrintfRuntimeBinding.cpp
Warn on misuse of DiagnosticInfo classes that hold Twines (#137397)
2025-05-28 12:26:39 -07:00
AMDGPUPromoteAlloca.cpp
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
AMDGPUPromoteKernelArguments.cpp
…
AMDGPUPTNote.h
…
AMDGPURegBankCombiner.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
AMDGPURegBankLegalize.cpp
AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)
2025-05-26 12:16:46 +02:00
AMDGPURegBankLegalizeHelper.cpp
[AMDGPU] Drop const from return types (NFC) (#145640)
2025-06-25 07:58:25 -07:00
AMDGPURegBankLegalizeHelper.h
[AMDGPU] Drop const from return types (NFC) (#145640)
2025-06-25 07:58:25 -07:00
AMDGPURegBankLegalizeRules.cpp
AMDGPU: Remove AMDGPUInstrInfo class (#144984)
2025-06-20 18:26:56 +09:00
AMDGPURegBankLegalizeRules.h
[AMDGPU] New RegBankSelect: Add Ptr32/Ptr64/Ptr128 (#142602)
2025-06-19 10:06:38 +02:00
AMDGPURegBankSelect.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
AMDGPURegisterBankInfo.cpp
AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive_rtn_b64 (#146409)
2025-07-01 11:08:49 -07:00
AMDGPURegisterBankInfo.h
…
AMDGPURegisterBanks.td
[AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)
2025-02-25 17:09:34 -05:00
AMDGPURemoveIncompatibleFunctions.cpp
[AMDGPU][NewPM] Port AMDGPURemoveIncompatibleFunctions to NPM (#122261)
2025-01-13 10:11:40 +05:30
AMDGPURemoveIncompatibleFunctions.h
[AMDGPU][NewPM] Port AMDGPURemoveIncompatibleFunctions to NPM (#122261)
2025-01-13 10:11:40 +05:30
AMDGPUReserveWWMRegs.cpp
[AMDGPU] Remove unused includes (NFC) (#141376)
2025-05-24 14:48:46 -07:00
AMDGPUReserveWWMRegs.h
[AMDGPU][NewPM] Port AMDGPUReserveWWMRegs to NPM (#123722)
2025-03-10 17:36:35 +05:30
AMDGPUResourceUsageAnalysis.cpp
Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)
2025-06-13 12:48:24 +02:00
AMDGPUResourceUsageAnalysis.h
…
AMDGPURewriteAGPRCopyMFMA.cpp
AMDGPU: Introduce a pass to replace VGPR MFMAs with AGPR (#145024)
2025-06-27 21:05:03 +09:00
AMDGPURewriteOutArguments.cpp
[DebugInfo][RemoveDIs] Delete debug-info-format flag (#143746)
2025-06-12 11:51:58 +01:00
AMDGPURewriteUndefForPHI.cpp
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
AMDGPUSearchableTables.td
AMDGPU: Implement intrinsic/builtins for gfx1250 load transpose instructions (#146289)
2025-06-29 14:33:31 -07:00
AMDGPUSelectionDAGInfo.cpp
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
AMDGPUSelectionDAGInfo.h
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
AMDGPUSetWavePriority.cpp
[AMDGPU] AMDGPUSetWavePriority: Remove unused variable NFC (#134069)
2025-04-02 16:52:05 +05:30
AMDGPUSplitModule.cpp
[AMDGPU][SplitModule] Do not create empty modules (#135761)
2025-04-25 09:36:41 +02:00
AMDGPUSplitModule.h
…
AMDGPUSubtarget.cpp
[AMDGPU] Fix computation of waves/EU maximum (#140921)
2025-05-22 02:45:59 +02:00
AMDGPUSubtarget.h
Triple: Forward declare Twine and remove include (#145685)
2025-06-26 15:26:04 +09:00
AMDGPUSwLowerLDS.cpp
[AMDGPU] Remove unused includes (NFC) (#141376)
2025-05-24 14:48:46 -07:00
AMDGPUTargetMachine.cpp
AMDGPU: Introduce a pass to replace VGPR MFMAs with AGPR (#145024)
2025-06-27 21:05:03 +09:00
AMDGPUTargetMachine.h
[CodeGen][NPM] Port VirtRegRewriter to NPM (#130564)
2025-04-30 14:10:46 +05:30
AMDGPUTargetObjectFile.cpp
…
AMDGPUTargetObjectFile.h
…
AMDGPUTargetTransformInfo.cpp
[AMDGPU] Enable vectorization of i8 values. (#134934)
2025-06-26 19:15:31 -04:00
AMDGPUTargetTransformInfo.h
[AMDGPU] Enable vectorization of i8 values. (#134934)
2025-06-26 19:15:31 -04:00
AMDGPUUnifyDivergentExitNodes.cpp
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
AMDGPUUnifyDivergentExitNodes.h
…
AMDGPUUnifyMetadata.cpp
AMDGPU: Remove legacy pass manager version of AMDGPUUnifyMetadata (#144985)
2025-06-20 16:44:06 +09:00
AMDGPUWaitSGPRHazards.cpp
[llvm] Use llvm::any_of (NFC) (#141444)
2025-05-26 09:13:21 -07:00
AMDGPUWaitSGPRHazards.h
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
AMDKernelCodeT.h
…
BUFInstructions.td
AMDGPU: Remove Formatted MUBUF instructions from gfx1250 support (#145590)
2025-06-24 14:17:13 -07:00
CaymanInstructions.td
…
CMakeLists.txt
AMDGPU: Introduce a pass to replace VGPR MFMAs with AGPR (#145024)
2025-06-27 21:05:03 +09:00
DSDIRInstructions.td
AMDGPU: Remove LDS-direct(param)-loads and VINTERP ops from gfx1250 support (#145631)
2025-06-24 22:44:35 -07:00
DSInstructions.td
AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive_rtn_b64 (#146409)
2025-07-01 11:08:49 -07:00
EvergreenInstructions.td
…
EXPInstructions.td
AMDGPU: Remove export and related instructions from gfx1250 support (#145624)
2025-06-24 19:59:26 -07:00
FLATInstructions.td
AMDGPU: Implement tensor_save and tensor_stop for gfx1250 (#146590)
2025-07-01 14:28:38 -07:00
GCNCreateVOPD.cpp
[AMDGPU][NPM] Port GCNCreateVOPD to NPM (#130059)
2025-03-14 10:22:45 +05:30
GCNDPPCombine.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
GCNDPPCombine.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
GCNHazardRecognizer.cpp
[AMDGPU] Add a debug option -amdgpu-snop-padding for GCNHazardRecognizer (#146587)
2025-07-02 08:16:38 -04:00
GCNHazardRecognizer.h
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
GCNILPSched.cpp
…
GCNIterativeScheduler.cpp
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
GCNIterativeScheduler.h
[AMDGPU] Teach iterative schedulers about IGLP (#134953)
2025-04-11 15:34:49 -07:00
GCNMinRegStrategy.cpp
…
GCNNSAReassign.cpp
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
GCNNSAReassign.h
[AMDGPU][NewPM] Port GCNNSAReassign pass to new pass manager (#125034)
2025-02-18 11:13:31 +05:30
GCNPreRALongBranchReg.cpp
[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)
2025-02-05 18:46:27 +05:30
GCNPreRALongBranchReg.h
[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)
2025-02-05 18:46:27 +05:30
GCNPreRAOptimizations.cpp
[AMDGPU][True16][CodeGen] update test for buildbot failure (#131028)
2025-03-12 16:59:48 -04:00
GCNPreRAOptimizations.h
[AMDGPU][NewPM] Port "GCNPreRAOptimizations" pass to NPM (#126040)
2025-02-11 11:09:38 +05:30
GCNProcessors.td
[AMDGPU] Baseline gfx1250 speed model. (#145217)
2025-06-22 20:26:06 -07:00
GCNRegPressure.cpp
[AMDGPU] Add GCNRPTarget to track register pressure against a target (#145765)
2025-06-26 13:11:20 +02:00
GCNRegPressure.h
[AMDGPU] Add GCNRPTarget to track register pressure against a target (#145765)
2025-06-26 13:11:20 +02:00
GCNRewritePartialRegUses.cpp
[AMDGPU] Simplify GCNRewritePartialRegUses pass. (#135199)
2025-04-11 15:45:24 +02:00
GCNRewritePartialRegUses.h
[AMDGPU][NewPM] Port "GCNRewritePartialRegUses" pass to NPM (#126024)
2025-02-12 11:21:40 +05:30
GCNSchedStrategy.cpp
[AMDGPU] Add GCNRPTarget to track register pressure against a target (#145765)
2025-06-26 13:11:20 +02:00
GCNSchedStrategy.h
[AMDGPU][Scheduler] Support for rematerializing SGPRs and AGPRs (#140036)
2025-06-24 19:30:27 +02:00
GCNSubtarget.cpp
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
GCNSubtarget.h
AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive_rtn_b64 (#146409)
2025-07-01 11:08:49 -07:00
GCNVOPDUtils.cpp
…
GCNVOPDUtils.h
…
InstCombineTables.td
…
MIMGInstructions.td
[AMDGPU] Add support for point sample accel out of order returns (#127991)
2025-04-10 15:33:48 +01:00
R600.h
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
R600.td
…
R600AsmPrinter.cpp
…
R600AsmPrinter.h
[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel
2025-03-29 11:08:13 -07:00
R600ClauseMergePass.cpp
…
R600ControlFlowFinalizer.cpp
…
R600Defines.h
…
R600EmitClauseMarkers.cpp
[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)
2025-04-07 17:27:50 -07:00
R600ExpandSpecialInstrs.cpp
[TableGen] Emit OpName as an enum class instead of a namespace (#125313)
2025-02-12 08:19:30 -08:00
R600FrameLowering.cpp
…
R600FrameLowering.h
…
R600InstrFormats.td
…
R600InstrInfo.cpp
[MC] Return MCRegister from MCRegisterClass::getRegister. NFC (#132126)
2025-03-20 07:24:53 -07:00
R600InstrInfo.h
[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister. (#128473)
2025-02-24 09:55:34 -08:00
R600InstrInfo.td
…
R600Instructions.td
…
R600ISelDAGToDAG.cpp
[AMDGPU] Remove unused includes (NFC) (#141376)
2025-05-24 14:48:46 -07:00
R600ISelLowering.cpp
AMDGPU: Use reportFatalUsageError for unhandled calling conventions (#145261)
2025-06-23 15:30:13 +09:00
R600ISelLowering.h
…
R600MachineCFGStructurizer.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
…
R600MachineScheduler.h
…
R600MCInstLower.cpp
[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel
2025-03-29 11:08:13 -07:00
R600OpenCLImageTypeLoweringPass.cpp
…
R600OptimizeVectorRegisters.cpp
[AMDGPU] Use MachineRegisterInfo::def_instructions (NFC) (#142782)
2025-06-04 12:30:56 -07:00
R600Packetizer.cpp
[TableGen] Emit OpName as an enum class instead of a namespace (#125313)
2025-02-12 08:19:30 -08:00
R600Processors.td
…
R600RegisterInfo.cpp
…
R600RegisterInfo.h
…
R600RegisterInfo.td
…
R600Schedule.td
…
R600Subtarget.cpp
[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)
2024-12-16 15:13:46 +03:00
R600Subtarget.h
[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)
2024-12-16 15:13:46 +03:00
R600TargetMachine.cpp
[TTI] Simplify implementation (NFCI) (#136674)
2025-04-26 15:25:40 +03:00
R600TargetMachine.h
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
2025-02-05 11:41:37 +05:30
R600TargetTransformInfo.cpp
[CostModel] Make Op0 and Op1 const in getVectorInstrCost. NFC (#137631)
2025-05-01 15:55:08 +01:00
R600TargetTransformInfo.h
[CostModel] Make Op0 and Op1 const in getVectorInstrCost. NFC (#137631)
2025-05-01 15:55:08 +01:00
R700Instructions.td
…
SIAnnotateControlFlow.cpp
AMDGPU: Rename variable from undef to poison (#130460)
2025-03-10 22:18:36 +07:00
SIDefines.h
AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive_rtn_b64 (#146409)
2025-07-01 11:08:49 -07:00
SIFixSGPRCopies.cpp
[AMDGPU] Fix SIFixSGPRCopies handling of STRICT_WWM and friends (#142122)
2025-05-30 16:32:56 +01:00
SIFixSGPRCopies.h
…
SIFixVGPRCopies.cpp
[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM (#123592)
2025-01-21 15:27:46 +05:30
SIFixVGPRCopies.h
[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM (#123592)
2025-01-21 15:27:46 +05:30
SIFoldOperands.cpp
AMDGPU: Handle folding vector splats of inline split f64 inline immediates (#140878)
2025-06-26 07:45:49 +09:00
SIFoldOperands.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SIFormMemoryClauses.cpp
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
SIFormMemoryClauses.h
[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)
2025-02-17 11:07:17 +05:30
SIFrameLowering.cpp
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
SIFrameLowering.h
Reland [AMDGPU] Support block load/store for CSR #130013 (#137169)
2025-04-25 11:29:27 +02:00
SIInsertHardClauses.cpp
[AMDGPU] SIInsertHardClause: add configurable clause length limit (#142343)
2025-06-04 15:00:34 +09:00
SIInsertWaitcnts.cpp
[AMDGPU] Remove HasSampler variable. NFC. (#146682)
2025-07-02 15:44:32 +01:00
SIInstrFormats.td
AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive_rtn_b64 (#146409)
2025-07-01 11:08:49 -07:00
SIInstrInfo.cpp
AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive_rtn_b64 (#146409)
2025-07-01 11:08:49 -07:00
SIInstrInfo.h
[AMDGPU][True16][CodeGen] legalize 16bit and 32bit use-def chain for moveToVALU in si-fix-sgpr-lowering (#138734)
2025-06-04 09:53:10 -04:00
SIInstrInfo.td
[AMDGPU] Add s_setprio_inc_wg gfx1250 instruction (#145152)
2025-06-22 12:52:05 -07:00
SIInstructions.td
[AMDGPU][True16][CodeGen] fix a predicate bug in VGPRImm with f16/bf16 (#144942)
2025-06-23 10:46:59 -04:00
SIISelLowering.cpp
AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive_rtn_b64 (#146409)
2025-07-01 11:08:49 -07:00
SIISelLowering.h
[AMDGPU][SDAG] Add ISD::PTRADD DAG combines (#142739)
2025-06-26 09:40:04 +02:00
SILateBranchLowering.cpp
[AMDGPU][NPM] Port SILateBranchLowering to NPM (#130063)
2025-03-26 19:28:19 +05:30
SILoadStoreOptimizer.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SILoadStoreOptimizer.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SILowerControlFlow.cpp
[AMDGPU][NewPM] Port SILowerControlFlow pass into NPM. (#123045)
2025-01-16 11:06:38 +05:30
SILowerControlFlow.h
[AMDGPU][NewPM] Port SILowerControlFlow pass into NPM. (#123045)
2025-01-16 11:06:38 +05:30
SILowerI1Copies.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SILowerI1Copies.h
AMDGPU/GlobalISel: Temporal divergence lowering (non i1) (#124298)
2025-03-12 12:09:37 +01:00
SILowerSGPRSpills.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SILowerSGPRSpills.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SILowerWWMCopies.cpp
[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695)
2025-01-22 14:54:01 +05:30
SILowerWWMCopies.h
[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695)
2025-01-22 14:54:01 +05:30
SIMachineFunctionInfo.cpp
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
SIMachineFunctionInfo.h
[AMDGPU] Replace dynamic VGPR feature with attribute (#133444)
2025-06-24 11:09:36 +02:00
SIMachineScheduler.cpp
[AMDGPU] Use MachineRegisterInfo::def_instructions (NFC) (#142782)
2025-06-04 12:30:56 -07:00
SIMachineScheduler.h
[AMDGPU] Replace unsigned with Register in SIMachineScheduler. NFC
2025-01-26 00:26:00 -08:00
SIMemoryLegalizer.cpp
[AMDGPU] Don't insert wait instructions that are not supported by gfx1250 (#145084)
2025-06-20 12:21:45 -07:00
SIModeRegister.cpp
[AMDGPU][NPM] Port SIModeRegister to NPM (#129014)
2025-03-04 10:51:03 +05:30
SIModeRegisterDefaults.cpp
…
SIModeRegisterDefaults.h
…
SIOptimizeExecMasking.cpp
[AMDGPU][True16][CodeGen] True16 Add OpSel when optimizing exec mask (#128928)
2025-02-28 09:41:05 -05:00
SIOptimizeExecMasking.h
[AMDGPU][NewPM] Port SIOptimizeExecMasking to NPM (#123572)
2025-01-20 16:34:01 +05:30
SIOptimizeExecMaskingPreRA.cpp
[AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (#125351)
2025-02-20 17:35:56 +05:30
SIOptimizeExecMaskingPreRA.h
[AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (#125351)
2025-02-20 17:35:56 +05:30
SIOptimizeVGPRLiveRange.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SIOptimizeVGPRLiveRange.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SIPeepholeSDWA.cpp
[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)
2025-06-26 14:08:13 -07:00
SIPeepholeSDWA.h
…
SIPostRABundler.cpp
AMDGPU: VIMAGE/VSAMPLE are bundle candidates (#140854)
2025-05-28 08:47:05 +08:00
SIPostRABundler.h
[AMDGPU][NewPM] Port SIPostRABundler to NPM (#123717)
2025-02-21 16:05:58 +05:30
SIPreAllocateWWMRegs.cpp
…
SIPreAllocateWWMRegs.h
…
SIPreEmitPeephole.cpp
[AMDGPU][NPM] Port SIPreEmitPeephole to NPM (#130065)
2025-04-08 17:58:48 +05:30
SIProgramInfo.cpp
[llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (#128367)
2025-03-17 23:17:46 +00:00
SIProgramInfo.h
[llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (#128367)
2025-03-17 23:17:46 +00:00
SIRegisterInfo.cpp
AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive_rtn_b64 (#146409)
2025-07-01 11:08:49 -07:00
SIRegisterInfo.h
AMDGPU: Introduce a pass to replace VGPR MFMAs with AGPR (#145024)
2025-06-27 21:05:03 +09:00
SIRegisterInfo.td
AMDGPU: Implement ds_atomic_async_barrier_arrive_b64/ds_atomic_barrier_arrive_rtn_b64 (#146409)
2025-07-01 11:08:49 -07:00
SISchedule.td
[AMDGPU] Baseline gfx1250 speed model. (#145217)
2025-06-22 20:26:06 -07:00
SIShrinkInstructions.cpp
[Target] Use range-based for loops (NFC) (#146198)
2025-06-27 22:07:58 -07:00
SIShrinkInstructions.h
…
SIWholeQuadMode.cpp
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SIWholeQuadMode.h
[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)
2025-05-23 08:30:29 -07:00
SMInstructions.td
[AMDGPU] Disallow null for more resource operands (#121941)
2025-01-08 08:02:10 +00:00
SOPInstructions.td
AMDGPU: support s_monitor_sleep on gfx1250 (#146293)
2025-06-29 21:01:47 -07:00
VIInstrFormats.td
…
VINTERPInstructions.td
[AMDGPU][True16][CodeGen] support for true16 for vinterp 16bit instructions (#116702)
2024-12-09 11:52:05 -05:00
VOP1Instructions.td
[AMDGPU] Add support for v_cvt_f16_bf8 on gfx1250 (#146305)
2025-06-30 07:54:55 -04:00
VOP2Instructions.td
[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)
2025-06-26 14:08:13 -07:00
VOP3Instructions.td
[AMDGPU][MC] Allow opsel for v_max_i16 etc in GFX10 (#143982)
2025-06-26 14:08:13 -07:00
VOP3PInstructions.td
[AMDGPU][MC] Allow dpp in v_dot2_f32_bf16 for GFX11 and 12 (#142451)
2025-06-05 09:55:12 -07:00
VOPCInstructions.td
[AMDGPU] Fix wrong reverse operations for v_cmpx_le_u32 (#146398)
2025-07-01 11:48:08 -04:00
VOPDInstructions.td
[AMDGPU][NFC] Remove _DEFERRED operands. (#139123)
2025-05-09 10:10:53 +01:00
VOPInstructions.td
[AMDGPU] Add support for v_cvt_f16_fp8 on gfx1250 (#146302)
2025-06-30 07:51:00 -04:00