6307b496f8
This adds the `GCNRPTarget` class which models a register pressure target (i.e., maximum number of SGPRs/VGPRS) that one can track register savings against. The only current use of this class is in the scheduler's rematerialization stage. It replaces the more ad-hoc (and now deleted) `ExcessRP` class which used to serve the same purpose. This is only NFC~ish because `GCNRPTarget` tracks VGPR usage more accurately than `ExcessRP` used to. To estimate required combined VGPR savings we now additionally take into account the number of available VGPRs in both banks (ArchVGPR and AGPR) at the time where the RP target is created, whereas we used to only consider explicit savings made from the starting RP. This makes VGPR savings estimations more accurate in cases where we allow for savings in one VGPR bank to help towards reducing pressure in another VGPR bank (see `GCNRPTarget::CombineVGPRSavings`). This is the cause for unit test changes.
983 lines
34 KiB
C++
983 lines
34 KiB
C++
//===- GCNRegPressure.cpp -------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the GCNRegPressure class.
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///
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//===----------------------------------------------------------------------===//
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#include "GCNRegPressure.h"
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#include "AMDGPU.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/RegisterPressure.h"
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using namespace llvm;
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#define DEBUG_TYPE "machine-scheduler"
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bool llvm::isEqual(const GCNRPTracker::LiveRegSet &S1,
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const GCNRPTracker::LiveRegSet &S2) {
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if (S1.size() != S2.size())
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return false;
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for (const auto &P : S1) {
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auto I = S2.find(P.first);
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if (I == S2.end() || I->second != P.second)
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return false;
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}
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return true;
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}
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///////////////////////////////////////////////////////////////////////////////
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// GCNRegPressure
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unsigned GCNRegPressure::getRegKind(const TargetRegisterClass *RC,
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const SIRegisterInfo *STI) {
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return STI->isSGPRClass(RC) ? SGPR : (STI->isAGPRClass(RC) ? AGPR : VGPR);
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}
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void GCNRegPressure::inc(unsigned Reg,
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LaneBitmask PrevMask,
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LaneBitmask NewMask,
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const MachineRegisterInfo &MRI) {
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unsigned NewNumCoveredRegs = SIRegisterInfo::getNumCoveredRegs(NewMask);
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unsigned PrevNumCoveredRegs = SIRegisterInfo::getNumCoveredRegs(PrevMask);
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if (NewNumCoveredRegs == PrevNumCoveredRegs)
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return;
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int Sign = 1;
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if (NewMask < PrevMask) {
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std::swap(NewMask, PrevMask);
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std::swap(NewNumCoveredRegs, PrevNumCoveredRegs);
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Sign = -1;
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}
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assert(PrevMask < NewMask && PrevNumCoveredRegs < NewNumCoveredRegs &&
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"prev mask should always be lesser than new");
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const TargetRegisterClass *RC = MRI.getRegClass(Reg);
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const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
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const SIRegisterInfo *STI = static_cast<const SIRegisterInfo *>(TRI);
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unsigned RegKind = getRegKind(RC, STI);
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if (TRI->getRegSizeInBits(*RC) != 32) {
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// Reg is from a tuple register class.
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if (PrevMask.none()) {
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unsigned TupleIdx = TOTAL_KINDS + RegKind;
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Value[TupleIdx] += Sign * TRI->getRegClassWeight(RC).RegWeight;
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}
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// Pressure scales with number of new registers covered by the new mask.
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// Note when true16 is enabled, we can no longer safely use the following
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// approach to calculate the difference in the number of 32-bit registers
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// between two masks:
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//
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// Sign *= SIRegisterInfo::getNumCoveredRegs(~PrevMask & NewMask);
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//
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// The issue is that the mask calculation `~PrevMask & NewMask` doesn't
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// properly account for partial usage of a 32-bit register when dealing with
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// 16-bit registers.
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//
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// Consider this example:
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// Assume PrevMask = 0b0010 and NewMask = 0b1111. Here, the correct register
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// usage difference should be 1, because even though PrevMask uses only half
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// of a 32-bit register, it should still be counted as a full register use.
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// However, the mask calculation yields `~PrevMask & NewMask = 0b1101`, and
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// calling `getNumCoveredRegs` returns 2 instead of 1. This incorrect
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// calculation can lead to integer overflow when Sign = -1.
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Sign *= NewNumCoveredRegs - PrevNumCoveredRegs;
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}
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Value[RegKind] += Sign;
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}
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bool GCNRegPressure::less(const MachineFunction &MF, const GCNRegPressure &O,
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unsigned MaxOccupancy) const {
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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unsigned DynamicVGPRBlockSize =
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MF.getInfo<SIMachineFunctionInfo>()->getDynamicVGPRBlockSize();
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const auto SGPROcc = std::min(MaxOccupancy,
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ST.getOccupancyWithNumSGPRs(getSGPRNum()));
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const auto VGPROcc = std::min(
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MaxOccupancy, ST.getOccupancyWithNumVGPRs(getVGPRNum(ST.hasGFX90AInsts()),
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DynamicVGPRBlockSize));
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const auto OtherSGPROcc = std::min(MaxOccupancy,
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ST.getOccupancyWithNumSGPRs(O.getSGPRNum()));
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const auto OtherVGPROcc =
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std::min(MaxOccupancy,
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ST.getOccupancyWithNumVGPRs(O.getVGPRNum(ST.hasGFX90AInsts()),
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DynamicVGPRBlockSize));
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const auto Occ = std::min(SGPROcc, VGPROcc);
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const auto OtherOcc = std::min(OtherSGPROcc, OtherVGPROcc);
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// Give first precedence to the better occupancy.
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if (Occ != OtherOcc)
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return Occ > OtherOcc;
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unsigned MaxVGPRs = ST.getMaxNumVGPRs(MF);
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unsigned MaxSGPRs = ST.getMaxNumSGPRs(MF);
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// SGPR excess pressure conditions
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unsigned ExcessSGPR = std::max(static_cast<int>(getSGPRNum() - MaxSGPRs), 0);
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unsigned OtherExcessSGPR =
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std::max(static_cast<int>(O.getSGPRNum() - MaxSGPRs), 0);
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auto WaveSize = ST.getWavefrontSize();
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// The number of virtual VGPRs required to handle excess SGPR
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unsigned VGPRForSGPRSpills = (ExcessSGPR + (WaveSize - 1)) / WaveSize;
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unsigned OtherVGPRForSGPRSpills =
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(OtherExcessSGPR + (WaveSize - 1)) / WaveSize;
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unsigned MaxArchVGPRs = ST.getAddressableNumArchVGPRs();
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// Unified excess pressure conditions, accounting for VGPRs used for SGPR
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// spills
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unsigned ExcessVGPR =
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std::max(static_cast<int>(getVGPRNum(ST.hasGFX90AInsts()) +
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VGPRForSGPRSpills - MaxVGPRs),
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0);
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unsigned OtherExcessVGPR =
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std::max(static_cast<int>(O.getVGPRNum(ST.hasGFX90AInsts()) +
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OtherVGPRForSGPRSpills - MaxVGPRs),
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0);
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// Arch VGPR excess pressure conditions, accounting for VGPRs used for SGPR
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// spills
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unsigned ExcessArchVGPR = std::max(
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static_cast<int>(getVGPRNum(false) + VGPRForSGPRSpills - MaxArchVGPRs),
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0);
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unsigned OtherExcessArchVGPR =
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std::max(static_cast<int>(O.getVGPRNum(false) + OtherVGPRForSGPRSpills -
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MaxArchVGPRs),
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0);
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// AGPR excess pressure conditions
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unsigned ExcessAGPR = std::max(
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static_cast<int>(ST.hasGFX90AInsts() ? (getAGPRNum() - MaxArchVGPRs)
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: (getAGPRNum() - MaxVGPRs)),
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0);
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unsigned OtherExcessAGPR = std::max(
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static_cast<int>(ST.hasGFX90AInsts() ? (O.getAGPRNum() - MaxArchVGPRs)
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: (O.getAGPRNum() - MaxVGPRs)),
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0);
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bool ExcessRP = ExcessSGPR || ExcessVGPR || ExcessArchVGPR || ExcessAGPR;
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bool OtherExcessRP = OtherExcessSGPR || OtherExcessVGPR ||
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OtherExcessArchVGPR || OtherExcessAGPR;
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// Give second precedence to the reduced number of spills to hold the register
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// pressure.
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if (ExcessRP || OtherExcessRP) {
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// The difference in excess VGPR pressure, after including VGPRs used for
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// SGPR spills
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int VGPRDiff = ((OtherExcessVGPR + OtherExcessArchVGPR + OtherExcessAGPR) -
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(ExcessVGPR + ExcessArchVGPR + ExcessAGPR));
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int SGPRDiff = OtherExcessSGPR - ExcessSGPR;
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if (VGPRDiff != 0)
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return VGPRDiff > 0;
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if (SGPRDiff != 0) {
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unsigned PureExcessVGPR =
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std::max(static_cast<int>(getVGPRNum(ST.hasGFX90AInsts()) - MaxVGPRs),
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0) +
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std::max(static_cast<int>(getVGPRNum(false) - MaxArchVGPRs), 0);
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unsigned OtherPureExcessVGPR =
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std::max(
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static_cast<int>(O.getVGPRNum(ST.hasGFX90AInsts()) - MaxVGPRs),
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0) +
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std::max(static_cast<int>(O.getVGPRNum(false) - MaxArchVGPRs), 0);
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// If we have a special case where there is a tie in excess VGPR, but one
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// of the pressures has VGPR usage from SGPR spills, prefer the pressure
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// with SGPR spills.
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if (PureExcessVGPR != OtherPureExcessVGPR)
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return SGPRDiff < 0;
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// If both pressures have the same excess pressure before and after
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// accounting for SGPR spills, prefer fewer SGPR spills.
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return SGPRDiff > 0;
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}
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}
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bool SGPRImportant = SGPROcc < VGPROcc;
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const bool OtherSGPRImportant = OtherSGPROcc < OtherVGPROcc;
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// If both pressures disagree on what is more important compare vgprs.
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if (SGPRImportant != OtherSGPRImportant) {
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SGPRImportant = false;
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}
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// Give third precedence to lower register tuple pressure.
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bool SGPRFirst = SGPRImportant;
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for (int I = 2; I > 0; --I, SGPRFirst = !SGPRFirst) {
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if (SGPRFirst) {
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auto SW = getSGPRTuplesWeight();
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auto OtherSW = O.getSGPRTuplesWeight();
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if (SW != OtherSW)
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return SW < OtherSW;
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} else {
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auto VW = getVGPRTuplesWeight();
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auto OtherVW = O.getVGPRTuplesWeight();
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if (VW != OtherVW)
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return VW < OtherVW;
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}
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}
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// Give final precedence to lower general RP.
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return SGPRImportant ? (getSGPRNum() < O.getSGPRNum()):
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(getVGPRNum(ST.hasGFX90AInsts()) <
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O.getVGPRNum(ST.hasGFX90AInsts()));
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}
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Printable llvm::print(const GCNRegPressure &RP, const GCNSubtarget *ST,
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unsigned DynamicVGPRBlockSize) {
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return Printable([&RP, ST, DynamicVGPRBlockSize](raw_ostream &OS) {
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OS << "VGPRs: " << RP.getArchVGPRNum() << ' '
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<< "AGPRs: " << RP.getAGPRNum();
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if (ST)
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OS << "(O"
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<< ST->getOccupancyWithNumVGPRs(RP.getVGPRNum(ST->hasGFX90AInsts()),
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DynamicVGPRBlockSize)
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<< ')';
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OS << ", SGPRs: " << RP.getSGPRNum();
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if (ST)
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OS << "(O" << ST->getOccupancyWithNumSGPRs(RP.getSGPRNum()) << ')';
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OS << ", LVGPR WT: " << RP.getVGPRTuplesWeight()
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<< ", LSGPR WT: " << RP.getSGPRTuplesWeight();
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if (ST)
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OS << " -> Occ: " << RP.getOccupancy(*ST, DynamicVGPRBlockSize);
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OS << '\n';
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});
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}
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static LaneBitmask getDefRegMask(const MachineOperand &MO,
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const MachineRegisterInfo &MRI) {
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assert(MO.isDef() && MO.isReg() && MO.getReg().isVirtual());
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// We don't rely on read-undef flag because in case of tentative schedule
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// tracking it isn't set correctly yet. This works correctly however since
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// use mask has been tracked before using LIS.
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return MO.getSubReg() == 0 ?
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MRI.getMaxLaneMaskForVReg(MO.getReg()) :
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MRI.getTargetRegisterInfo()->getSubRegIndexLaneMask(MO.getSubReg());
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}
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static void
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collectVirtualRegUses(SmallVectorImpl<VRegMaskOrUnit> &VRegMaskOrUnits,
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const MachineInstr &MI, const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI) {
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auto &TRI = *MRI.getTargetRegisterInfo();
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for (const auto &MO : MI.operands()) {
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if (!MO.isReg() || !MO.getReg().isVirtual())
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continue;
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if (!MO.isUse() || !MO.readsReg())
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continue;
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Register Reg = MO.getReg();
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auto I = llvm::find_if(VRegMaskOrUnits, [Reg](const VRegMaskOrUnit &RM) {
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return RM.RegUnit == Reg;
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});
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auto &P = I == VRegMaskOrUnits.end()
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? VRegMaskOrUnits.emplace_back(Reg, LaneBitmask::getNone())
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: *I;
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P.LaneMask |= MO.getSubReg() ? TRI.getSubRegIndexLaneMask(MO.getSubReg())
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: MRI.getMaxLaneMaskForVReg(Reg);
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}
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SlotIndex InstrSI;
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for (auto &P : VRegMaskOrUnits) {
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auto &LI = LIS.getInterval(P.RegUnit);
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if (!LI.hasSubRanges())
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continue;
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// For a tentative schedule LIS isn't updated yet but livemask should
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// remain the same on any schedule. Subreg defs can be reordered but they
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// all must dominate uses anyway.
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if (!InstrSI)
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InstrSI = LIS.getInstructionIndex(MI).getBaseIndex();
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P.LaneMask = getLiveLaneMask(LI, InstrSI, MRI, P.LaneMask);
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}
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}
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/// Mostly copy/paste from CodeGen/RegisterPressure.cpp
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static LaneBitmask getLanesWithProperty(
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const LiveIntervals &LIS, const MachineRegisterInfo &MRI,
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bool TrackLaneMasks, Register RegUnit, SlotIndex Pos,
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LaneBitmask SafeDefault,
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function_ref<bool(const LiveRange &LR, SlotIndex Pos)> Property) {
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if (RegUnit.isVirtual()) {
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const LiveInterval &LI = LIS.getInterval(RegUnit);
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LaneBitmask Result;
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if (TrackLaneMasks && LI.hasSubRanges()) {
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for (const LiveInterval::SubRange &SR : LI.subranges()) {
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if (Property(SR, Pos))
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Result |= SR.LaneMask;
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}
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} else if (Property(LI, Pos)) {
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Result = TrackLaneMasks ? MRI.getMaxLaneMaskForVReg(RegUnit)
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: LaneBitmask::getAll();
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}
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return Result;
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}
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const LiveRange *LR = LIS.getCachedRegUnit(RegUnit);
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if (LR == nullptr)
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return SafeDefault;
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return Property(*LR, Pos) ? LaneBitmask::getAll() : LaneBitmask::getNone();
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}
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/// Mostly copy/paste from CodeGen/RegisterPressure.cpp
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/// Helper to find a vreg use between two indices {PriorUseIdx, NextUseIdx}.
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/// The query starts with a lane bitmask which gets lanes/bits removed for every
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/// use we find.
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static LaneBitmask findUseBetween(unsigned Reg, LaneBitmask LastUseMask,
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SlotIndex PriorUseIdx, SlotIndex NextUseIdx,
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const MachineRegisterInfo &MRI,
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const SIRegisterInfo *TRI,
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const LiveIntervals *LIS,
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bool Upward = false) {
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for (const MachineOperand &MO : MRI.use_nodbg_operands(Reg)) {
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if (MO.isUndef())
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continue;
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const MachineInstr *MI = MO.getParent();
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SlotIndex InstSlot = LIS->getInstructionIndex(*MI).getRegSlot();
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bool InRange = Upward ? (InstSlot > PriorUseIdx && InstSlot <= NextUseIdx)
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: (InstSlot >= PriorUseIdx && InstSlot < NextUseIdx);
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if (!InRange)
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continue;
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unsigned SubRegIdx = MO.getSubReg();
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LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
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LastUseMask &= ~UseMask;
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if (LastUseMask.none())
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return LaneBitmask::getNone();
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}
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return LastUseMask;
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}
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////////////////////////////////////////////////////////////////////////////////
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// GCNRPTarget
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GCNRPTarget::GCNRPTarget(const MachineFunction &MF, const GCNRegPressure &RP,
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bool CombineVGPRSavings)
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: RP(RP), CombineVGPRSavings(CombineVGPRSavings) {
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const Function &F = MF.getFunction();
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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setRegLimits(ST.getMaxNumSGPRs(F), ST.getMaxNumVGPRs(F), MF);
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}
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GCNRPTarget::GCNRPTarget(unsigned NumSGPRs, unsigned NumVGPRs,
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const MachineFunction &MF, const GCNRegPressure &RP,
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bool CombineVGPRSavings)
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: RP(RP), CombineVGPRSavings(CombineVGPRSavings) {
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setRegLimits(NumSGPRs, NumVGPRs, MF);
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}
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GCNRPTarget::GCNRPTarget(unsigned Occupancy, const MachineFunction &MF,
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const GCNRegPressure &RP, bool CombineVGPRSavings)
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: RP(RP), CombineVGPRSavings(CombineVGPRSavings) {
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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unsigned DynamicVGPRBlockSize =
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MF.getInfo<SIMachineFunctionInfo>()->getDynamicVGPRBlockSize();
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setRegLimits(ST.getMaxNumSGPRs(Occupancy, /*Addressable=*/false),
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ST.getMaxNumVGPRs(Occupancy, DynamicVGPRBlockSize), MF);
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}
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void GCNRPTarget::setRegLimits(unsigned NumSGPRs, unsigned NumVGPRs,
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const MachineFunction &MF) {
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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unsigned DynamicVGPRBlockSize =
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MF.getInfo<SIMachineFunctionInfo>()->getDynamicVGPRBlockSize();
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MaxSGPRs = std::min(ST.getAddressableNumSGPRs(), NumSGPRs);
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MaxVGPRs = std::min(ST.getAddressableNumArchVGPRs(), NumVGPRs);
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MaxUnifiedVGPRs =
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ST.hasGFX90AInsts()
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? std::min(ST.getAddressableNumVGPRs(DynamicVGPRBlockSize), NumVGPRs)
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: 0;
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}
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bool GCNRPTarget::isSaveBeneficial(Register Reg,
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const MachineRegisterInfo &MRI) const {
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const TargetRegisterClass *RC = MRI.getRegClass(Reg);
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const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
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const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo *>(TRI);
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if (SRI->isSGPRClass(RC))
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return RP.getSGPRNum() > MaxSGPRs;
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unsigned NumVGPRs =
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SRI->isAGPRClass(RC) ? RP.getAGPRNum() : RP.getArchVGPRNum();
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return isVGPRBankSaveBeneficial(NumVGPRs);
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}
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bool GCNRPTarget::satisfied() const {
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if (RP.getSGPRNum() > MaxSGPRs)
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return false;
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if (RP.getVGPRNum(false) > MaxVGPRs &&
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(!CombineVGPRSavings || !satisifiesVGPRBanksTarget()))
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return false;
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return satisfiesUnifiedTarget();
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}
|
|
|
|
///////////////////////////////////////////////////////////////////////////////
|
|
// GCNRPTracker
|
|
|
|
LaneBitmask llvm::getLiveLaneMask(unsigned Reg, SlotIndex SI,
|
|
const LiveIntervals &LIS,
|
|
const MachineRegisterInfo &MRI,
|
|
LaneBitmask LaneMaskFilter) {
|
|
return getLiveLaneMask(LIS.getInterval(Reg), SI, MRI, LaneMaskFilter);
|
|
}
|
|
|
|
LaneBitmask llvm::getLiveLaneMask(const LiveInterval &LI, SlotIndex SI,
|
|
const MachineRegisterInfo &MRI,
|
|
LaneBitmask LaneMaskFilter) {
|
|
LaneBitmask LiveMask;
|
|
if (LI.hasSubRanges()) {
|
|
for (const auto &S : LI.subranges())
|
|
if ((S.LaneMask & LaneMaskFilter).any() && S.liveAt(SI)) {
|
|
LiveMask |= S.LaneMask;
|
|
assert(LiveMask == (LiveMask & MRI.getMaxLaneMaskForVReg(LI.reg())));
|
|
}
|
|
} else if (LI.liveAt(SI)) {
|
|
LiveMask = MRI.getMaxLaneMaskForVReg(LI.reg());
|
|
}
|
|
LiveMask &= LaneMaskFilter;
|
|
return LiveMask;
|
|
}
|
|
|
|
GCNRPTracker::LiveRegSet llvm::getLiveRegs(SlotIndex SI,
|
|
const LiveIntervals &LIS,
|
|
const MachineRegisterInfo &MRI) {
|
|
GCNRPTracker::LiveRegSet LiveRegs;
|
|
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
|
|
auto Reg = Register::index2VirtReg(I);
|
|
if (!LIS.hasInterval(Reg))
|
|
continue;
|
|
auto LiveMask = getLiveLaneMask(Reg, SI, LIS, MRI);
|
|
if (LiveMask.any())
|
|
LiveRegs[Reg] = LiveMask;
|
|
}
|
|
return LiveRegs;
|
|
}
|
|
|
|
void GCNRPTracker::reset(const MachineInstr &MI,
|
|
const LiveRegSet *LiveRegsCopy,
|
|
bool After) {
|
|
const MachineFunction &MF = *MI.getMF();
|
|
MRI = &MF.getRegInfo();
|
|
if (LiveRegsCopy) {
|
|
if (&LiveRegs != LiveRegsCopy)
|
|
LiveRegs = *LiveRegsCopy;
|
|
} else {
|
|
LiveRegs = After ? getLiveRegsAfter(MI, LIS)
|
|
: getLiveRegsBefore(MI, LIS);
|
|
}
|
|
|
|
MaxPressure = CurPressure = getRegPressure(*MRI, LiveRegs);
|
|
}
|
|
|
|
void GCNRPTracker::reset(const MachineRegisterInfo &MRI_,
|
|
const LiveRegSet &LiveRegs_) {
|
|
MRI = &MRI_;
|
|
LiveRegs = LiveRegs_;
|
|
LastTrackedMI = nullptr;
|
|
MaxPressure = CurPressure = getRegPressure(MRI_, LiveRegs_);
|
|
}
|
|
|
|
/// Mostly copy/paste from CodeGen/RegisterPressure.cpp
|
|
LaneBitmask GCNRPTracker::getLastUsedLanes(Register RegUnit,
|
|
SlotIndex Pos) const {
|
|
return getLanesWithProperty(
|
|
LIS, *MRI, true, RegUnit, Pos.getBaseIndex(), LaneBitmask::getNone(),
|
|
[](const LiveRange &LR, SlotIndex Pos) {
|
|
const LiveRange::Segment *S = LR.getSegmentContaining(Pos);
|
|
return S != nullptr && S->end == Pos.getRegSlot();
|
|
});
|
|
}
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// GCNUpwardRPTracker
|
|
|
|
void GCNUpwardRPTracker::recede(const MachineInstr &MI) {
|
|
assert(MRI && "call reset first");
|
|
|
|
LastTrackedMI = &MI;
|
|
|
|
if (MI.isDebugInstr())
|
|
return;
|
|
|
|
// Kill all defs.
|
|
GCNRegPressure DefPressure, ECDefPressure;
|
|
bool HasECDefs = false;
|
|
for (const MachineOperand &MO : MI.all_defs()) {
|
|
if (!MO.getReg().isVirtual())
|
|
continue;
|
|
|
|
Register Reg = MO.getReg();
|
|
LaneBitmask DefMask = getDefRegMask(MO, *MRI);
|
|
|
|
// Treat a def as fully live at the moment of definition: keep a record.
|
|
if (MO.isEarlyClobber()) {
|
|
ECDefPressure.inc(Reg, LaneBitmask::getNone(), DefMask, *MRI);
|
|
HasECDefs = true;
|
|
} else
|
|
DefPressure.inc(Reg, LaneBitmask::getNone(), DefMask, *MRI);
|
|
|
|
auto I = LiveRegs.find(Reg);
|
|
if (I == LiveRegs.end())
|
|
continue;
|
|
|
|
LaneBitmask &LiveMask = I->second;
|
|
LaneBitmask PrevMask = LiveMask;
|
|
LiveMask &= ~DefMask;
|
|
CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
|
|
if (LiveMask.none())
|
|
LiveRegs.erase(I);
|
|
}
|
|
|
|
// Update MaxPressure with defs pressure.
|
|
DefPressure += CurPressure;
|
|
if (HasECDefs)
|
|
DefPressure += ECDefPressure;
|
|
MaxPressure = max(DefPressure, MaxPressure);
|
|
|
|
// Make uses alive.
|
|
SmallVector<VRegMaskOrUnit, 8> RegUses;
|
|
collectVirtualRegUses(RegUses, MI, LIS, *MRI);
|
|
for (const VRegMaskOrUnit &U : RegUses) {
|
|
LaneBitmask &LiveMask = LiveRegs[U.RegUnit];
|
|
LaneBitmask PrevMask = LiveMask;
|
|
LiveMask |= U.LaneMask;
|
|
CurPressure.inc(U.RegUnit, PrevMask, LiveMask, *MRI);
|
|
}
|
|
|
|
// Update MaxPressure with uses plus early-clobber defs pressure.
|
|
MaxPressure = HasECDefs ? max(CurPressure + ECDefPressure, MaxPressure)
|
|
: max(CurPressure, MaxPressure);
|
|
|
|
assert(CurPressure == getRegPressure(*MRI, LiveRegs));
|
|
}
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// GCNDownwardRPTracker
|
|
|
|
bool GCNDownwardRPTracker::reset(const MachineInstr &MI,
|
|
const LiveRegSet *LiveRegsCopy) {
|
|
MRI = &MI.getParent()->getParent()->getRegInfo();
|
|
LastTrackedMI = nullptr;
|
|
MBBEnd = MI.getParent()->end();
|
|
NextMI = &MI;
|
|
NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
|
|
if (NextMI == MBBEnd)
|
|
return false;
|
|
GCNRPTracker::reset(*NextMI, LiveRegsCopy, false);
|
|
return true;
|
|
}
|
|
|
|
bool GCNDownwardRPTracker::advanceBeforeNext(MachineInstr *MI,
|
|
bool UseInternalIterator) {
|
|
assert(MRI && "call reset first");
|
|
SlotIndex SI;
|
|
const MachineInstr *CurrMI;
|
|
if (UseInternalIterator) {
|
|
if (!LastTrackedMI)
|
|
return NextMI == MBBEnd;
|
|
|
|
assert(NextMI == MBBEnd || !NextMI->isDebugInstr());
|
|
CurrMI = LastTrackedMI;
|
|
|
|
SI = NextMI == MBBEnd
|
|
? LIS.getInstructionIndex(*LastTrackedMI).getDeadSlot()
|
|
: LIS.getInstructionIndex(*NextMI).getBaseIndex();
|
|
} else { //! UseInternalIterator
|
|
SI = LIS.getInstructionIndex(*MI).getBaseIndex();
|
|
CurrMI = MI;
|
|
}
|
|
|
|
assert(SI.isValid());
|
|
|
|
// Remove dead registers or mask bits.
|
|
SmallSet<Register, 8> SeenRegs;
|
|
for (auto &MO : CurrMI->operands()) {
|
|
if (!MO.isReg() || !MO.getReg().isVirtual())
|
|
continue;
|
|
if (MO.isUse() && !MO.readsReg())
|
|
continue;
|
|
if (!UseInternalIterator && MO.isDef())
|
|
continue;
|
|
if (!SeenRegs.insert(MO.getReg()).second)
|
|
continue;
|
|
const LiveInterval &LI = LIS.getInterval(MO.getReg());
|
|
if (LI.hasSubRanges()) {
|
|
auto It = LiveRegs.end();
|
|
for (const auto &S : LI.subranges()) {
|
|
if (!S.liveAt(SI)) {
|
|
if (It == LiveRegs.end()) {
|
|
It = LiveRegs.find(MO.getReg());
|
|
if (It == LiveRegs.end())
|
|
llvm_unreachable("register isn't live");
|
|
}
|
|
auto PrevMask = It->second;
|
|
It->second &= ~S.LaneMask;
|
|
CurPressure.inc(MO.getReg(), PrevMask, It->second, *MRI);
|
|
}
|
|
}
|
|
if (It != LiveRegs.end() && It->second.none())
|
|
LiveRegs.erase(It);
|
|
} else if (!LI.liveAt(SI)) {
|
|
auto It = LiveRegs.find(MO.getReg());
|
|
if (It == LiveRegs.end())
|
|
llvm_unreachable("register isn't live");
|
|
CurPressure.inc(MO.getReg(), It->second, LaneBitmask::getNone(), *MRI);
|
|
LiveRegs.erase(It);
|
|
}
|
|
}
|
|
|
|
MaxPressure = max(MaxPressure, CurPressure);
|
|
|
|
LastTrackedMI = nullptr;
|
|
|
|
return UseInternalIterator && (NextMI == MBBEnd);
|
|
}
|
|
|
|
void GCNDownwardRPTracker::advanceToNext(MachineInstr *MI,
|
|
bool UseInternalIterator) {
|
|
if (UseInternalIterator) {
|
|
LastTrackedMI = &*NextMI++;
|
|
NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
|
|
} else {
|
|
LastTrackedMI = MI;
|
|
}
|
|
|
|
const MachineInstr *CurrMI = LastTrackedMI;
|
|
|
|
// Add new registers or mask bits.
|
|
for (const auto &MO : CurrMI->all_defs()) {
|
|
Register Reg = MO.getReg();
|
|
if (!Reg.isVirtual())
|
|
continue;
|
|
auto &LiveMask = LiveRegs[Reg];
|
|
auto PrevMask = LiveMask;
|
|
LiveMask |= getDefRegMask(MO, *MRI);
|
|
CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
|
|
}
|
|
|
|
MaxPressure = max(MaxPressure, CurPressure);
|
|
}
|
|
|
|
bool GCNDownwardRPTracker::advance(MachineInstr *MI, bool UseInternalIterator) {
|
|
if (UseInternalIterator && NextMI == MBBEnd)
|
|
return false;
|
|
|
|
advanceBeforeNext(MI, UseInternalIterator);
|
|
advanceToNext(MI, UseInternalIterator);
|
|
if (!UseInternalIterator) {
|
|
// We must remove any dead def lanes from the current RP
|
|
advanceBeforeNext(MI, true);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
bool GCNDownwardRPTracker::advance(MachineBasicBlock::const_iterator End) {
|
|
while (NextMI != End)
|
|
if (!advance()) return false;
|
|
return true;
|
|
}
|
|
|
|
bool GCNDownwardRPTracker::advance(MachineBasicBlock::const_iterator Begin,
|
|
MachineBasicBlock::const_iterator End,
|
|
const LiveRegSet *LiveRegsCopy) {
|
|
reset(*Begin, LiveRegsCopy);
|
|
return advance(End);
|
|
}
|
|
|
|
Printable llvm::reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
|
|
const GCNRPTracker::LiveRegSet &TrackedLR,
|
|
const TargetRegisterInfo *TRI, StringRef Pfx) {
|
|
return Printable([&LISLR, &TrackedLR, TRI, Pfx](raw_ostream &OS) {
|
|
for (auto const &P : TrackedLR) {
|
|
auto I = LISLR.find(P.first);
|
|
if (I == LISLR.end()) {
|
|
OS << Pfx << printReg(P.first, TRI) << ":L" << PrintLaneMask(P.second)
|
|
<< " isn't found in LIS reported set\n";
|
|
} else if (I->second != P.second) {
|
|
OS << Pfx << printReg(P.first, TRI)
|
|
<< " masks doesn't match: LIS reported " << PrintLaneMask(I->second)
|
|
<< ", tracked " << PrintLaneMask(P.second) << '\n';
|
|
}
|
|
}
|
|
for (auto const &P : LISLR) {
|
|
auto I = TrackedLR.find(P.first);
|
|
if (I == TrackedLR.end()) {
|
|
OS << Pfx << printReg(P.first, TRI) << ":L" << PrintLaneMask(P.second)
|
|
<< " isn't found in tracked set\n";
|
|
}
|
|
}
|
|
});
|
|
}
|
|
|
|
GCNRegPressure
|
|
GCNDownwardRPTracker::bumpDownwardPressure(const MachineInstr *MI,
|
|
const SIRegisterInfo *TRI) const {
|
|
assert(!MI->isDebugOrPseudoInstr() && "Expect a nondebug instruction.");
|
|
|
|
SlotIndex SlotIdx;
|
|
SlotIdx = LIS.getInstructionIndex(*MI).getRegSlot();
|
|
|
|
// Account for register pressure similar to RegPressureTracker::recede().
|
|
RegisterOperands RegOpers;
|
|
RegOpers.collect(*MI, *TRI, *MRI, true, /*IgnoreDead=*/false);
|
|
RegOpers.adjustLaneLiveness(LIS, *MRI, SlotIdx);
|
|
GCNRegPressure TempPressure = CurPressure;
|
|
|
|
for (const VRegMaskOrUnit &Use : RegOpers.Uses) {
|
|
Register Reg = Use.RegUnit;
|
|
if (!Reg.isVirtual())
|
|
continue;
|
|
LaneBitmask LastUseMask = getLastUsedLanes(Reg, SlotIdx);
|
|
if (LastUseMask.none())
|
|
continue;
|
|
// The LastUseMask is queried from the liveness information of instruction
|
|
// which may be further down the schedule. Some lanes may actually not be
|
|
// last uses for the current position.
|
|
// FIXME: allow the caller to pass in the list of vreg uses that remain
|
|
// to be bottom-scheduled to avoid searching uses at each query.
|
|
SlotIndex CurrIdx;
|
|
const MachineBasicBlock *MBB = MI->getParent();
|
|
MachineBasicBlock::const_iterator IdxPos = skipDebugInstructionsForward(
|
|
LastTrackedMI ? LastTrackedMI : MBB->begin(), MBB->end());
|
|
if (IdxPos == MBB->end()) {
|
|
CurrIdx = LIS.getMBBEndIdx(MBB);
|
|
} else {
|
|
CurrIdx = LIS.getInstructionIndex(*IdxPos).getRegSlot();
|
|
}
|
|
|
|
LastUseMask =
|
|
findUseBetween(Reg, LastUseMask, CurrIdx, SlotIdx, *MRI, TRI, &LIS);
|
|
if (LastUseMask.none())
|
|
continue;
|
|
|
|
auto It = LiveRegs.find(Reg);
|
|
LaneBitmask LiveMask = It != LiveRegs.end() ? It->second : LaneBitmask(0);
|
|
LaneBitmask NewMask = LiveMask & ~LastUseMask;
|
|
TempPressure.inc(Reg, LiveMask, NewMask, *MRI);
|
|
}
|
|
|
|
// Generate liveness for defs.
|
|
for (const VRegMaskOrUnit &Def : RegOpers.Defs) {
|
|
Register Reg = Def.RegUnit;
|
|
if (!Reg.isVirtual())
|
|
continue;
|
|
auto It = LiveRegs.find(Reg);
|
|
LaneBitmask LiveMask = It != LiveRegs.end() ? It->second : LaneBitmask(0);
|
|
LaneBitmask NewMask = LiveMask | Def.LaneMask;
|
|
TempPressure.inc(Reg, LiveMask, NewMask, *MRI);
|
|
}
|
|
|
|
return TempPressure;
|
|
}
|
|
|
|
bool GCNUpwardRPTracker::isValid() const {
|
|
const auto &SI = LIS.getInstructionIndex(*LastTrackedMI).getBaseIndex();
|
|
const auto LISLR = llvm::getLiveRegs(SI, LIS, *MRI);
|
|
const auto &TrackedLR = LiveRegs;
|
|
|
|
if (!isEqual(LISLR, TrackedLR)) {
|
|
dbgs() << "\nGCNUpwardRPTracker error: Tracked and"
|
|
" LIS reported livesets mismatch:\n"
|
|
<< print(LISLR, *MRI);
|
|
reportMismatch(LISLR, TrackedLR, MRI->getTargetRegisterInfo());
|
|
return false;
|
|
}
|
|
|
|
auto LISPressure = getRegPressure(*MRI, LISLR);
|
|
if (LISPressure != CurPressure) {
|
|
dbgs() << "GCNUpwardRPTracker error: Pressure sets different\nTracked: "
|
|
<< print(CurPressure) << "LIS rpt: " << print(LISPressure);
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
Printable llvm::print(const GCNRPTracker::LiveRegSet &LiveRegs,
|
|
const MachineRegisterInfo &MRI) {
|
|
return Printable([&LiveRegs, &MRI](raw_ostream &OS) {
|
|
const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
|
|
for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
|
|
Register Reg = Register::index2VirtReg(I);
|
|
auto It = LiveRegs.find(Reg);
|
|
if (It != LiveRegs.end() && It->second.any())
|
|
OS << ' ' << printVRegOrUnit(Reg, TRI) << ':'
|
|
<< PrintLaneMask(It->second);
|
|
}
|
|
OS << '\n';
|
|
});
|
|
}
|
|
|
|
void GCNRegPressure::dump() const { dbgs() << print(*this); }
|
|
|
|
static cl::opt<bool> UseDownwardTracker(
|
|
"amdgpu-print-rp-downward",
|
|
cl::desc("Use GCNDownwardRPTracker for GCNRegPressurePrinter pass"),
|
|
cl::init(false), cl::Hidden);
|
|
|
|
char llvm::GCNRegPressurePrinter::ID = 0;
|
|
char &llvm::GCNRegPressurePrinterID = GCNRegPressurePrinter::ID;
|
|
|
|
INITIALIZE_PASS(GCNRegPressurePrinter, "amdgpu-print-rp", "", true, true)
|
|
|
|
// Return lanemask of Reg's subregs that are live-through at [Begin, End] and
|
|
// are fully covered by Mask.
|
|
static LaneBitmask
|
|
getRegLiveThroughMask(const MachineRegisterInfo &MRI, const LiveIntervals &LIS,
|
|
Register Reg, SlotIndex Begin, SlotIndex End,
|
|
LaneBitmask Mask = LaneBitmask::getAll()) {
|
|
|
|
auto IsInOneSegment = [Begin, End](const LiveRange &LR) -> bool {
|
|
auto *Segment = LR.getSegmentContaining(Begin);
|
|
return Segment && Segment->contains(End);
|
|
};
|
|
|
|
LaneBitmask LiveThroughMask;
|
|
const LiveInterval &LI = LIS.getInterval(Reg);
|
|
if (LI.hasSubRanges()) {
|
|
for (auto &SR : LI.subranges()) {
|
|
if ((SR.LaneMask & Mask) == SR.LaneMask && IsInOneSegment(SR))
|
|
LiveThroughMask |= SR.LaneMask;
|
|
}
|
|
} else {
|
|
LaneBitmask RegMask = MRI.getMaxLaneMaskForVReg(Reg);
|
|
if ((RegMask & Mask) == RegMask && IsInOneSegment(LI))
|
|
LiveThroughMask = RegMask;
|
|
}
|
|
|
|
return LiveThroughMask;
|
|
}
|
|
|
|
bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
|
|
const MachineRegisterInfo &MRI = MF.getRegInfo();
|
|
const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
|
|
const LiveIntervals &LIS = getAnalysis<LiveIntervalsWrapperPass>().getLIS();
|
|
|
|
auto &OS = dbgs();
|
|
|
|
// Leading spaces are important for YAML syntax.
|
|
#define PFX " "
|
|
|
|
OS << "---\nname: " << MF.getName() << "\nbody: |\n";
|
|
|
|
auto printRP = [](const GCNRegPressure &RP) {
|
|
return Printable([&RP](raw_ostream &OS) {
|
|
OS << format(PFX " %-5d", RP.getSGPRNum())
|
|
<< format(" %-5d", RP.getVGPRNum(false));
|
|
});
|
|
};
|
|
|
|
auto ReportLISMismatchIfAny = [&](const GCNRPTracker::LiveRegSet &TrackedLR,
|
|
const GCNRPTracker::LiveRegSet &LISLR) {
|
|
if (LISLR != TrackedLR) {
|
|
OS << PFX " mis LIS: " << llvm::print(LISLR, MRI)
|
|
<< reportMismatch(LISLR, TrackedLR, TRI, PFX " ");
|
|
}
|
|
};
|
|
|
|
// Register pressure before and at an instruction (in program order).
|
|
SmallVector<std::pair<GCNRegPressure, GCNRegPressure>, 16> RP;
|
|
|
|
for (auto &MBB : MF) {
|
|
RP.clear();
|
|
RP.reserve(MBB.size());
|
|
|
|
OS << PFX;
|
|
MBB.printName(OS);
|
|
OS << ":\n";
|
|
|
|
SlotIndex MBBStartSlot = LIS.getSlotIndexes()->getMBBStartIdx(&MBB);
|
|
SlotIndex MBBEndSlot = LIS.getSlotIndexes()->getMBBEndIdx(&MBB);
|
|
|
|
GCNRPTracker::LiveRegSet LiveIn, LiveOut;
|
|
GCNRegPressure RPAtMBBEnd;
|
|
|
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if (UseDownwardTracker) {
|
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if (MBB.empty()) {
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LiveIn = LiveOut = getLiveRegs(MBBStartSlot, LIS, MRI);
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RPAtMBBEnd = getRegPressure(MRI, LiveIn);
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} else {
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GCNDownwardRPTracker RPT(LIS);
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RPT.reset(MBB.front());
|
|
|
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LiveIn = RPT.getLiveRegs();
|
|
|
|
while (!RPT.advanceBeforeNext()) {
|
|
GCNRegPressure RPBeforeMI = RPT.getPressure();
|
|
RPT.advanceToNext();
|
|
RP.emplace_back(RPBeforeMI, RPT.getPressure());
|
|
}
|
|
|
|
LiveOut = RPT.getLiveRegs();
|
|
RPAtMBBEnd = RPT.getPressure();
|
|
}
|
|
} else {
|
|
GCNUpwardRPTracker RPT(LIS);
|
|
RPT.reset(MRI, MBBEndSlot);
|
|
|
|
LiveOut = RPT.getLiveRegs();
|
|
RPAtMBBEnd = RPT.getPressure();
|
|
|
|
for (auto &MI : reverse(MBB)) {
|
|
RPT.resetMaxPressure();
|
|
RPT.recede(MI);
|
|
if (!MI.isDebugInstr())
|
|
RP.emplace_back(RPT.getPressure(), RPT.getMaxPressure());
|
|
}
|
|
|
|
LiveIn = RPT.getLiveRegs();
|
|
}
|
|
|
|
OS << PFX " Live-in: " << llvm::print(LiveIn, MRI);
|
|
if (!UseDownwardTracker)
|
|
ReportLISMismatchIfAny(LiveIn, getLiveRegs(MBBStartSlot, LIS, MRI));
|
|
|
|
OS << PFX " SGPR VGPR\n";
|
|
int I = 0;
|
|
for (auto &MI : MBB) {
|
|
if (!MI.isDebugInstr()) {
|
|
auto &[RPBeforeInstr, RPAtInstr] =
|
|
RP[UseDownwardTracker ? I : (RP.size() - 1 - I)];
|
|
++I;
|
|
OS << printRP(RPBeforeInstr) << '\n' << printRP(RPAtInstr) << " ";
|
|
} else
|
|
OS << PFX " ";
|
|
MI.print(OS);
|
|
}
|
|
OS << printRP(RPAtMBBEnd) << '\n';
|
|
|
|
OS << PFX " Live-out:" << llvm::print(LiveOut, MRI);
|
|
if (UseDownwardTracker)
|
|
ReportLISMismatchIfAny(LiveOut, getLiveRegs(MBBEndSlot, LIS, MRI));
|
|
|
|
GCNRPTracker::LiveRegSet LiveThrough;
|
|
for (auto [Reg, Mask] : LiveIn) {
|
|
LaneBitmask MaskIntersection = Mask & LiveOut.lookup(Reg);
|
|
if (MaskIntersection.any()) {
|
|
LaneBitmask LTMask = getRegLiveThroughMask(
|
|
MRI, LIS, Reg, MBBStartSlot, MBBEndSlot, MaskIntersection);
|
|
if (LTMask.any())
|
|
LiveThrough[Reg] = LTMask;
|
|
}
|
|
}
|
|
OS << PFX " Live-thr:" << llvm::print(LiveThrough, MRI);
|
|
OS << printRP(getRegPressure(MRI, LiveThrough)) << '\n';
|
|
}
|
|
OS << "...\n";
|
|
return false;
|
|
|
|
#undef PFX
|
|
}
|