3dc09fbf29
Implment base support of the TLS functionality using Xtensa THREADPTR Option. Implement basic functionality of the DFPAccel Option(registers support).
311 lines
9.5 KiB
C++
311 lines
9.5 KiB
C++
//===-- XtensaMCTargetDesc.cpp - Xtensa target descriptions ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "XtensaMCTargetDesc.h"
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#include "TargetInfo/XtensaTargetInfo.h"
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#include "XtensaInstPrinter.h"
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#include "XtensaMCAsmInfo.h"
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#include "XtensaTargetStreamer.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/ErrorHandling.h"
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#define GET_INSTRINFO_MC_DESC
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#include "XtensaGenInstrInfo.inc"
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#define GET_REGINFO_MC_DESC
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#include "XtensaGenRegisterInfo.inc"
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#define GET_SUBTARGETINFO_MC_DESC
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#include "XtensaGenSubtargetInfo.inc"
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using namespace llvm;
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bool Xtensa::isValidAddrOffset(int Scale, int64_t OffsetVal) {
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bool Valid = false;
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switch (Scale) {
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case 1:
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Valid = (OffsetVal >= 0 && OffsetVal <= 255);
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break;
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case 2:
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Valid = (OffsetVal >= 0 && OffsetVal <= 510) && ((OffsetVal & 0x1) == 0);
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break;
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case 4:
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Valid = (OffsetVal >= 0 && OffsetVal <= 1020) && ((OffsetVal & 0x3) == 0);
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break;
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default:
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break;
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}
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return Valid;
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}
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bool Xtensa::isValidAddrOffsetForOpcode(unsigned Opcode, int64_t Offset) {
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int Scale = 0;
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switch (Opcode) {
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case Xtensa::L8UI:
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case Xtensa::S8I:
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Scale = 1;
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break;
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case Xtensa::L16SI:
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case Xtensa::L16UI:
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case Xtensa::S16I:
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Scale = 2;
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break;
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case Xtensa::LEA_ADD:
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return (Offset >= -128 && Offset <= 127);
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default:
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// assume that MI is 32-bit load/store operation
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Scale = 4;
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break;
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}
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return isValidAddrOffset(Scale, Offset);
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}
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// Verify Special Register
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bool Xtensa::checkRegister(MCRegister RegNo, const FeatureBitset &FeatureBits,
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RegisterAccessType RAType) {
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switch (RegNo) {
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case Xtensa::BREG:
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return FeatureBits[Xtensa::FeatureBoolean];
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case Xtensa::CCOUNT:
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case Xtensa::CCOMPARE0:
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if (FeatureBits[Xtensa::FeatureTimers1])
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return true;
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LLVM_FALLTHROUGH;
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case Xtensa::CCOMPARE1:
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if (FeatureBits[Xtensa::FeatureTimers2])
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return true;
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LLVM_FALLTHROUGH;
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case Xtensa::CCOMPARE2:
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if (FeatureBits[Xtensa::FeatureTimers3])
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return true;
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return false;
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case Xtensa::CONFIGID0:
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return RAType != Xtensa::REGISTER_EXCHANGE;
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case Xtensa::CONFIGID1:
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return RAType == Xtensa::REGISTER_READ;
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case Xtensa::CPENABLE:
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return FeatureBits[Xtensa::FeatureCoprocessor];
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case Xtensa::DEBUGCAUSE:
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return RAType == Xtensa::REGISTER_READ && FeatureBits[Xtensa::FeatureDebug];
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case Xtensa::DEPC:
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case Xtensa::EPC1:
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case Xtensa::EXCCAUSE:
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case Xtensa::EXCSAVE1:
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case Xtensa::EXCVADDR:
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return FeatureBits[Xtensa::FeatureException];
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LLVM_FALLTHROUGH;
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case Xtensa::EPC2:
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case Xtensa::EPS2:
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case Xtensa::EXCSAVE2:
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if (FeatureBits[Xtensa::FeatureHighPriInterrupts])
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return true;
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LLVM_FALLTHROUGH;
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case Xtensa::EPC3:
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case Xtensa::EPS3:
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case Xtensa::EXCSAVE3:
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if (FeatureBits[Xtensa::FeatureHighPriInterruptsLevel3])
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return true;
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LLVM_FALLTHROUGH;
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case Xtensa::EPC4:
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case Xtensa::EPS4:
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case Xtensa::EXCSAVE4:
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if (FeatureBits[Xtensa::FeatureHighPriInterruptsLevel4])
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return true;
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LLVM_FALLTHROUGH;
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case Xtensa::EPC5:
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case Xtensa::EPS5:
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case Xtensa::EXCSAVE5:
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if (FeatureBits[Xtensa::FeatureHighPriInterruptsLevel5])
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return true;
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LLVM_FALLTHROUGH;
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case Xtensa::EPC6:
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case Xtensa::EPS6:
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case Xtensa::EXCSAVE6:
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if (FeatureBits[Xtensa::FeatureHighPriInterruptsLevel6])
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return true;
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LLVM_FALLTHROUGH;
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case Xtensa::EPC7:
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case Xtensa::EPS7:
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case Xtensa::EXCSAVE7:
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if (FeatureBits[Xtensa::FeatureHighPriInterruptsLevel7])
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return true;
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return false;
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case Xtensa::INTENABLE:
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return FeatureBits[Xtensa::FeatureInterrupt];
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case Xtensa::INTERRUPT:
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return RAType == Xtensa::REGISTER_READ &&
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FeatureBits[Xtensa::FeatureInterrupt];
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case Xtensa::INTSET:
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case Xtensa::INTCLEAR:
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return RAType == Xtensa::REGISTER_WRITE &&
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FeatureBits[Xtensa::FeatureInterrupt];
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case Xtensa::ICOUNT:
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case Xtensa::ICOUNTLEVEL:
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case Xtensa::IBREAKENABLE:
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case Xtensa::DDR:
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case Xtensa::IBREAKA0:
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case Xtensa::IBREAKA1:
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case Xtensa::DBREAKA0:
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case Xtensa::DBREAKA1:
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case Xtensa::DBREAKC0:
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case Xtensa::DBREAKC1:
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return FeatureBits[Xtensa::FeatureDebug];
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case Xtensa::LBEG:
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case Xtensa::LEND:
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case Xtensa::LCOUNT:
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return FeatureBits[Xtensa::FeatureLoop];
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case Xtensa::LITBASE:
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return FeatureBits[Xtensa::FeatureExtendedL32R];
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case Xtensa::MEMCTL:
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return FeatureBits[Xtensa::FeatureDataCache];
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case Xtensa::ACCLO:
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case Xtensa::ACCHI:
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case Xtensa::M0:
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case Xtensa::M1:
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case Xtensa::M2:
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case Xtensa::M3:
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return FeatureBits[Xtensa::FeatureMAC16];
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case Xtensa::MISC0:
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case Xtensa::MISC1:
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case Xtensa::MISC2:
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case Xtensa::MISC3:
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return FeatureBits[Xtensa::FeatureMiscSR];
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case Xtensa::PRID:
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return RAType == Xtensa::REGISTER_READ && FeatureBits[Xtensa::FeaturePRID];
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case Xtensa::THREADPTR:
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return FeatureBits[FeatureTHREADPTR];
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case Xtensa::VECBASE:
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return FeatureBits[Xtensa::FeatureRelocatableVector];
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case Xtensa::FCR:
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case Xtensa::FSR:
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return FeatureBits[FeatureSingleFloat];
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case Xtensa::F64R_LO:
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case Xtensa::F64R_HI:
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case Xtensa::F64S:
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return FeatureBits[FeatureDFPAccel];
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case Xtensa::WINDOWBASE:
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case Xtensa::WINDOWSTART:
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return FeatureBits[Xtensa::FeatureWindowed];
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case Xtensa::NoRegister:
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return false;
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}
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return true;
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}
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// Get Xtensa User Register by encoding value.
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MCRegister Xtensa::getUserRegister(unsigned Code, const MCRegisterInfo &MRI) {
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MCRegister UserReg = Xtensa::NoRegister;
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if (MRI.getEncodingValue(Xtensa::FCR) == Code) {
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UserReg = Xtensa::FCR;
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} else if (MRI.getEncodingValue(Xtensa::FSR) == Code) {
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UserReg = Xtensa::FSR;
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} else if (MRI.getEncodingValue(Xtensa::F64R_LO) == Code) {
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UserReg = Xtensa::F64R_LO;
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} else if (MRI.getEncodingValue(Xtensa::F64R_HI) == Code) {
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UserReg = Xtensa::F64R_HI;
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} else if (MRI.getEncodingValue(Xtensa::F64S) == Code) {
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UserReg = Xtensa::F64S;
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} else if (MRI.getEncodingValue(Xtensa::THREADPTR) == Code) {
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UserReg = Xtensa::THREADPTR;
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}
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return UserReg;
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}
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static MCAsmInfo *createXtensaMCAsmInfo(const MCRegisterInfo &MRI,
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const Triple &TT,
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const MCTargetOptions &Options) {
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MCAsmInfo *MAI = new XtensaMCAsmInfo(TT);
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return MAI;
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}
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static MCInstrInfo *createXtensaMCInstrInfo() {
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MCInstrInfo *X = new MCInstrInfo();
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InitXtensaMCInstrInfo(X);
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return X;
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}
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static MCInstPrinter *createXtensaMCInstPrinter(const Triple &TT,
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unsigned SyntaxVariant,
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const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI) {
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return new XtensaInstPrinter(MAI, MII, MRI);
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}
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static MCRegisterInfo *createXtensaMCRegisterInfo(const Triple &TT) {
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MCRegisterInfo *X = new MCRegisterInfo();
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InitXtensaMCRegisterInfo(X, Xtensa::SP);
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return X;
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}
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static MCSubtargetInfo *
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createXtensaMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
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return createXtensaMCSubtargetInfoImpl(TT, CPU, CPU, FS);
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}
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static MCTargetStreamer *
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createXtensaAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,
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MCInstPrinter *InstPrint) {
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return new XtensaTargetAsmStreamer(S, OS);
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}
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static MCTargetStreamer *
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createXtensaObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
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return new XtensaTargetELFStreamer(S);
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaTargetMC() {
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// Register the MCAsmInfo.
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TargetRegistry::RegisterMCAsmInfo(getTheXtensaTarget(),
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createXtensaMCAsmInfo);
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// Register the MCCodeEmitter.
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TargetRegistry::RegisterMCCodeEmitter(getTheXtensaTarget(),
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createXtensaMCCodeEmitter);
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// Register the MCInstrInfo.
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TargetRegistry::RegisterMCInstrInfo(getTheXtensaTarget(),
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createXtensaMCInstrInfo);
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// Register the MCInstPrinter.
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TargetRegistry::RegisterMCInstPrinter(getTheXtensaTarget(),
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createXtensaMCInstPrinter);
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// Register the MCRegisterInfo.
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TargetRegistry::RegisterMCRegInfo(getTheXtensaTarget(),
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createXtensaMCRegisterInfo);
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// Register the MCSubtargetInfo.
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TargetRegistry::RegisterMCSubtargetInfo(getTheXtensaTarget(),
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createXtensaMCSubtargetInfo);
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// Register the MCAsmBackend.
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TargetRegistry::RegisterMCAsmBackend(getTheXtensaTarget(),
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createXtensaAsmBackend);
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// Register the asm target streamer.
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TargetRegistry::RegisterAsmTargetStreamer(getTheXtensaTarget(),
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createXtensaAsmTargetStreamer);
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// Register the ELF target streamer.
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TargetRegistry::RegisterObjectTargetStreamer(
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getTheXtensaTarget(), createXtensaObjectTargetStreamer);
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}
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