bdb4353ae0
It turns out that there are relatively trivial, albeit rare, cases that
require a MaxDepth of more than 16 (see added test). However, we want to
avoid having to rely on a large fixed MaxDepth.
Since these cases are relatively rare, apply the following strategy:
1. Start with a low MaxDepth of 16 - if the entry node was not
reached, we can return (the common case).
2. If the entry node was reached, exponentially increase MaxDepth up
to some large limit that should cover all cases and guard against
stack exhaustion.
This retains the better performance with a low MaxDepth in the common
case, and in complex cases backs off and retries. On a whole, this is
preferable vs. starting with a large MaxDepth which would unnecessarily
penalize the common case where a low MaxDepth is sufficient.
Reviewed By: dvyukov
Differential Revision: https://reviews.llvm.org/D145386
245 lines
9.8 KiB
LLVM
245 lines
9.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 < %s | FileCheck %s --check-prefixes=O0
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; RUN: llc -O1 < %s | FileCheck %s --check-prefixes=OPT
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; RUN: llc -O2 < %s | FileCheck %s --check-prefixes=OPT
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; RUN: llc -O3 < %s | FileCheck %s --check-prefixes=OPT
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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@__llvm_gcov_ctr.89 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.109 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.112 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.113 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.154 = internal global [1 x i64] zeroinitializer
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@__llvm_gcov_ctr.155 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.156 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.157 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.160 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.161 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.189 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.1109 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.1112 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.1113 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.1154 = internal global [1 x i64] zeroinitializer
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@__llvm_gcov_ctr.1155 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.1156 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.1157 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.1160 = internal global [2 x i64] zeroinitializer
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@__llvm_gcov_ctr.1161 = internal global [2 x i64] zeroinitializer
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define dso_local void @independent_load_stores() {
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; O0-LABEL: independent_load_stores:
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; O0: # %bb.0:
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; O0-NEXT: .Lpcsection0:
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; O0-NEXT: movq __llvm_gcov_ctr.109, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection1:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.109
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; O0-NEXT: .Lpcsection2:
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; O0-NEXT: movq __llvm_gcov_ctr.112, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection3:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.112
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; O0-NEXT: .Lpcsection4:
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; O0-NEXT: movq __llvm_gcov_ctr.113, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection5:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.113
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; O0-NEXT: .Lpcsection6:
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; O0-NEXT: movq __llvm_gcov_ctr.154, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection7:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.154
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; O0-NEXT: .Lpcsection8:
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; O0-NEXT: movq __llvm_gcov_ctr.155, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection9:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.155
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; O0-NEXT: .Lpcsection10:
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; O0-NEXT: movq __llvm_gcov_ctr.89, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection11:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.89
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; O0-NEXT: .Lpcsection12:
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; O0-NEXT: movq __llvm_gcov_ctr.160, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection13:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.160
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; O0-NEXT: .Lpcsection14:
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; O0-NEXT: movq __llvm_gcov_ctr.156, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection15:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.156
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; O0-NEXT: .Lpcsection16:
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; O0-NEXT: movq __llvm_gcov_ctr.157, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection17:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.157
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; O0-NEXT: .Lpcsection18:
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; O0-NEXT: movq __llvm_gcov_ctr.161, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection19:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.161
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; O0-NEXT: .Lpcsection20:
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; O0-NEXT: movq __llvm_gcov_ctr.1109, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection21:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.1109
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; O0-NEXT: .Lpcsection22:
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; O0-NEXT: movq __llvm_gcov_ctr.1112, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection23:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.1112
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; O0-NEXT: .Lpcsection24:
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; O0-NEXT: movq __llvm_gcov_ctr.1113, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection25:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.1113
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; O0-NEXT: .Lpcsection26:
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; O0-NEXT: movq __llvm_gcov_ctr.1154, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection27:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.1154
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; O0-NEXT: .Lpcsection28:
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; O0-NEXT: movq __llvm_gcov_ctr.1155, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection29:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.1155
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; O0-NEXT: .Lpcsection30:
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; O0-NEXT: movq __llvm_gcov_ctr.189, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection31:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.189
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; O0-NEXT: .Lpcsection32:
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; O0-NEXT: movq __llvm_gcov_ctr.1160, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection33:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.1160
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; O0-NEXT: .Lpcsection34:
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; O0-NEXT: movq __llvm_gcov_ctr.1156, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection35:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.1156
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; O0-NEXT: .Lpcsection36:
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; O0-NEXT: movq __llvm_gcov_ctr.1157, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection37:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.1157
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; O0-NEXT: .Lpcsection38:
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; O0-NEXT: movq __llvm_gcov_ctr.1161, %rax
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; O0-NEXT: addq $1, %rax
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; O0-NEXT: .Lpcsection39:
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; O0-NEXT: movq %rax, __llvm_gcov_ctr.1161
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; O0-NEXT: retq
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;
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; OPT-LABEL: independent_load_stores:
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; OPT: # %bb.0:
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; OPT-NEXT: .Lpcsection0:
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; OPT-NEXT: incq __llvm_gcov_ctr.109(%rip)
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; OPT-NEXT: .Lpcsection1:
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; OPT-NEXT: incq __llvm_gcov_ctr.112(%rip)
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; OPT-NEXT: .Lpcsection2:
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; OPT-NEXT: incq __llvm_gcov_ctr.113(%rip)
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; OPT-NEXT: .Lpcsection3:
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; OPT-NEXT: incq __llvm_gcov_ctr.154(%rip)
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; OPT-NEXT: .Lpcsection4:
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; OPT-NEXT: incq __llvm_gcov_ctr.155(%rip)
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; OPT-NEXT: .Lpcsection5:
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; OPT-NEXT: incq __llvm_gcov_ctr.89(%rip)
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; OPT-NEXT: .Lpcsection6:
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; OPT-NEXT: incq __llvm_gcov_ctr.160(%rip)
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; OPT-NEXT: .Lpcsection7:
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; OPT-NEXT: incq __llvm_gcov_ctr.156(%rip)
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; OPT-NEXT: .Lpcsection8:
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; OPT-NEXT: incq __llvm_gcov_ctr.157(%rip)
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; OPT-NEXT: .Lpcsection9:
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; OPT-NEXT: incq __llvm_gcov_ctr.161(%rip)
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; OPT-NEXT: .Lpcsection10:
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; OPT-NEXT: incq __llvm_gcov_ctr.1109(%rip)
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; OPT-NEXT: .Lpcsection11:
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; OPT-NEXT: incq __llvm_gcov_ctr.1112(%rip)
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; OPT-NEXT: .Lpcsection12:
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; OPT-NEXT: incq __llvm_gcov_ctr.1113(%rip)
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; OPT-NEXT: .Lpcsection13:
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; OPT-NEXT: incq __llvm_gcov_ctr.1154(%rip)
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; OPT-NEXT: .Lpcsection14:
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; OPT-NEXT: incq __llvm_gcov_ctr.1155(%rip)
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; OPT-NEXT: .Lpcsection15:
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; OPT-NEXT: incq __llvm_gcov_ctr.189(%rip)
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; OPT-NEXT: .Lpcsection16:
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; OPT-NEXT: incq __llvm_gcov_ctr.1160(%rip)
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; OPT-NEXT: .Lpcsection17:
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; OPT-NEXT: incq __llvm_gcov_ctr.1156(%rip)
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; OPT-NEXT: .Lpcsection18:
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; OPT-NEXT: incq __llvm_gcov_ctr.1157(%rip)
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; OPT-NEXT: .Lpcsection19:
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; OPT-NEXT: incq __llvm_gcov_ctr.1161(%rip)
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; OPT-NEXT: retq
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%1 = load i64, ptr @__llvm_gcov_ctr.109, align 8, !pcsections !0
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%2 = add i64 %1, 1
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store i64 %2, ptr @__llvm_gcov_ctr.109, align 8, !pcsections !0
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%3 = load i64, ptr @__llvm_gcov_ctr.112, align 8, !pcsections !0
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%4 = add i64 %3, 1
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store i64 %4, ptr @__llvm_gcov_ctr.112, align 8, !pcsections !0
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%5 = load i64, ptr @__llvm_gcov_ctr.113, align 8, !pcsections !0
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%6 = add i64 %5, 1
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store i64 %6, ptr @__llvm_gcov_ctr.113, align 8, !pcsections !0
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%7 = load i64, ptr @__llvm_gcov_ctr.154, align 8, !pcsections !0
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%8 = add i64 %7, 1
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store i64 %8, ptr @__llvm_gcov_ctr.154, align 8, !pcsections !0
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%9 = load i64, ptr @__llvm_gcov_ctr.155, align 8, !pcsections !0
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%10 = add i64 %9, 1
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store i64 %10, ptr @__llvm_gcov_ctr.155, align 8, !pcsections !0
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%11 = load i64, ptr @__llvm_gcov_ctr.89, align 8, !pcsections !0
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%12 = add i64 %11, 1
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store i64 %12, ptr @__llvm_gcov_ctr.89, align 8, !pcsections !0
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%13 = load i64, ptr @__llvm_gcov_ctr.160, align 8, !pcsections !0
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%14 = add i64 %13, 1
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store i64 %14, ptr @__llvm_gcov_ctr.160, align 8, !pcsections !0
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%15 = load i64, ptr @__llvm_gcov_ctr.156, align 8, !pcsections !0
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%16 = add i64 %15, 1
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store i64 %16, ptr @__llvm_gcov_ctr.156, align 8, !pcsections !0
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%17 = load i64, ptr @__llvm_gcov_ctr.157, align 8, !pcsections !0
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%18 = add i64 %17, 1
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store i64 %18, ptr @__llvm_gcov_ctr.157, align 8, !pcsections !0
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%19 = load i64, ptr @__llvm_gcov_ctr.161, align 8, !pcsections !0
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%20 = add i64 %19, 1
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store i64 %20, ptr @__llvm_gcov_ctr.161, align 8, !pcsections !0
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%21 = load i64, ptr @__llvm_gcov_ctr.1109, align 8, !pcsections !0
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%22 = add i64 %21, 1
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store i64 %22, ptr @__llvm_gcov_ctr.1109, align 8, !pcsections !0
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%23 = load i64, ptr @__llvm_gcov_ctr.1112, align 8, !pcsections !0
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%24 = add i64 %23, 1
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store i64 %24, ptr @__llvm_gcov_ctr.1112, align 8, !pcsections !0
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%25 = load i64, ptr @__llvm_gcov_ctr.1113, align 8, !pcsections !0
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%26 = add i64 %25, 1
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store i64 %26, ptr @__llvm_gcov_ctr.1113, align 8, !pcsections !0
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%27 = load i64, ptr @__llvm_gcov_ctr.1154, align 8, !pcsections !0
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%28 = add i64 %27, 1
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store i64 %28, ptr @__llvm_gcov_ctr.1154, align 8, !pcsections !0
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%29 = load i64, ptr @__llvm_gcov_ctr.1155, align 8, !pcsections !0
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%30 = add i64 %29, 1
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store i64 %30, ptr @__llvm_gcov_ctr.1155, align 8, !pcsections !0
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%31 = load i64, ptr @__llvm_gcov_ctr.189, align 8, !pcsections !0
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%32 = add i64 %31, 1
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store i64 %32, ptr @__llvm_gcov_ctr.189, align 8, !pcsections !0
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%33 = load i64, ptr @__llvm_gcov_ctr.1160, align 8, !pcsections !0
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%34 = add i64 %33, 1
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store i64 %34, ptr @__llvm_gcov_ctr.1160, align 8, !pcsections !0
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%35 = load i64, ptr @__llvm_gcov_ctr.1156, align 8, !pcsections !0
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%36 = add i64 %35, 1
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store i64 %36, ptr @__llvm_gcov_ctr.1156, align 8, !pcsections !0
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%37 = load i64, ptr @__llvm_gcov_ctr.1157, align 8, !pcsections !0
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%38 = add i64 %37, 1
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store i64 %38, ptr @__llvm_gcov_ctr.1157, align 8, !pcsections !0
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%39 = load i64, ptr @__llvm_gcov_ctr.1161, align 8, !pcsections !0
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%40 = add i64 %39, 1
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store i64 %40, ptr @__llvm_gcov_ctr.1161, align 8, !pcsections !0
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ret void
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}
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!0 = !{!"foo"}
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