b7e4fba6e5
After #98505, the textual IR keyword `x86_mmx` was temporarily made to parse as `<1 x i64>`, so as not to require a lot of test update noise. This completes the removal of the type, by removing the`x86_mmx` keyword from the IR parser, and making the (now no-op) test updates via `sed -i 's/\bx86_mmx\b/<1 x i64>/g' $(git grep -l x86_mmx llvm/test/)`. Resulting bitcasts from <1 x i64> to itself were then manually deleted. Changes to llvm/test/Bitcode/compatibility-$VERSION.ll were reverted, as they're intended to be equivalent to the .bc file, if parsed by old LLVM, so shouldn't be updated. A few tests were removed, as they're no longer testing anything, in the following files: - llvm/test/Transforms/GlobalOpt/x86_mmx_load.ll - llvm/test/Transforms/InstCombine/cast.ll - llvm/test/Transforms/InstSimplify/ConstProp/gep-zeroinit-vector.ll Works towards issue #98272.
25 lines
918 B
LLVM
25 lines
918 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=+mmx,+sse4.2 | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=+mmx,+sse4.2 | FileCheck %s --check-prefix=X64
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; MMX insertelement is not available; these are promoted to xmm.
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; (Without SSE they are split to two ints, and the code is much better.)
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define <1 x i64> @mmx_movzl(<1 x i64> %x) nounwind {
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; X86-LABEL: mmx_movzl:
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; X86: ## %bb.0:
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; X86-NEXT: movl $32, %eax
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; X86-NEXT: xorl %edx, %edx
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; X86-NEXT: retl
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;
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; X64-LABEL: mmx_movzl:
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; X64: ## %bb.0:
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; X64-NEXT: movl $32, %eax
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; X64-NEXT: retq
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%tmp = bitcast <1 x i64> %x to <2 x i32>
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%tmp3 = insertelement <2 x i32> %tmp, i32 32, i32 0
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%tmp8 = insertelement <2 x i32> %tmp3, i32 0, i32 1
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%tmp9 = bitcast <2 x i32> %tmp8 to <1 x i64>
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ret <1 x i64> %tmp9
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}
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