d0f9553ef5
This patch basically enables fast-isel for AIX 64-bit subtarget (previously enabled only for ELF 64). The initial motivation is to introduce branch folding to AIX generated code for correct debug behavior. I also saw some compiling time improvement in a few LLVM test-suite benchmarks. (toast, dbms, cjpeg, burg, etc.) Reviewed By: jsji Differential Revision: https://reviews.llvm.org/D98844
139 lines
2.8 KiB
LLVM
139 lines
2.8 KiB
LLVM
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
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; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
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; Test add with non-legal types
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define void @add_i8(i8 %a, i8 %b) nounwind {
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entry:
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; PPC64: add_i8
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%a.addr = alloca i8, align 4
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%0 = add i8 %a, %b
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; PPC64: add
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @add_i8_imm(i8 %a) nounwind {
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entry:
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; PPC64: add_i8_imm
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%a.addr = alloca i8, align 4
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%0 = add i8 %a, 22;
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; PPC64: addi
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @add_i16(i16 %a, i16 %b) nounwind {
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entry:
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; PPC64: add_i16
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%a.addr = alloca i16, align 4
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%0 = add i16 %a, %b
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; PPC64: add
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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define void @add_i16_imm(i16 %a, i16 %b) nounwind {
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entry:
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; PPC64: add_i16_imm
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%a.addr = alloca i16, align 4
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%0 = add i16 %a, 243;
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; PPC64: addi
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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; Test or with non-legal types
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define void @or_i8(i8 %a, i8 %b) nounwind {
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entry:
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; PPC64: or_i8
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%a.addr = alloca i8, align 4
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%0 = or i8 %a, %b
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; PPC64: or
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @or_i8_imm(i8 %a) nounwind {
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entry:
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; PPC64: or_i8_imm
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%a.addr = alloca i8, align 4
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%0 = or i8 %a, -13;
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; PPC64: ori
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @or_i16(i16 %a, i16 %b) nounwind {
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entry:
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; PPC64: or_i16
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%a.addr = alloca i16, align 4
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%0 = or i16 %a, %b
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; PPC64: or
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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define void @or_i16_imm(i16 %a) nounwind {
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entry:
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; PPC64: or_i16_imm
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%a.addr = alloca i16, align 4
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%0 = or i16 %a, 273;
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; PPC64: ori
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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; Test sub with non-legal types
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define void @sub_i8(i8 %a, i8 %b) nounwind {
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entry:
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; PPC64: sub_i8
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%a.addr = alloca i8, align 4
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%0 = sub i8 %a, %b
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; PPC64: sub
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @sub_i8_imm(i8 %a) nounwind {
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entry:
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; PPC64: sub_i8_imm
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%a.addr = alloca i8, align 4
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%0 = sub i8 %a, 22;
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; PPC64: addi
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @sub_i16(i16 %a, i16 %b) nounwind {
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entry:
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; PPC64: sub_i16
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%a.addr = alloca i16, align 4
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%0 = sub i16 %a, %b
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; PPC64: sub
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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define void @sub_i16_imm(i16 %a) nounwind {
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entry:
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; PPC64: sub_i16_imm
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%a.addr = alloca i16, align 4
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%0 = sub i16 %a, 247;
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; PPC64: addi
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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define void @sub_i16_badimm(i16 %a) nounwind {
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entry:
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; PPC64: sub_i16_imm
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%a.addr = alloca i16, align 4
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%0 = sub i16 %a, -32768;
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; PPC64: sub
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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