9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
108 lines
4.4 KiB
LLVM
108 lines
4.4 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare double @llvm.fabs.f64(double) #0
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; SI-LABEL: {{^}}fsub_f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @fsub_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
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ptr addrspace(1) %in2) {
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%r0 = load double, ptr addrspace(1) %in1
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%r1 = load double, ptr addrspace(1) %in2
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%r2 = fsub double %r0, %r1
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store double %r2, ptr addrspace(1) %out
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ret void
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}
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; SI-LABEL: {{^}}fsub_fabs_f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -\|v\[[0-9]+:[0-9]+\]\|}}
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define amdgpu_kernel void @fsub_fabs_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
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ptr addrspace(1) %in2) {
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%r0 = load double, ptr addrspace(1) %in1
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%r1 = load double, ptr addrspace(1) %in2
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%r1.fabs = call double @llvm.fabs.f64(double %r1) #0
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%r2 = fsub double %r0, %r1.fabs
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store double %r2, ptr addrspace(1) %out
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ret void
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}
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; SI-LABEL: {{^}}fsub_fabs_inv_f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], |v\[[0-9]+:[0-9]+\]|, -v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @fsub_fabs_inv_f64(ptr addrspace(1) %out, ptr addrspace(1) %in1,
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ptr addrspace(1) %in2) {
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%r0 = load double, ptr addrspace(1) %in1
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%r1 = load double, ptr addrspace(1) %in2
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%r0.fabs = call double @llvm.fabs.f64(double %r0) #0
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%r2 = fsub double %r0.fabs, %r1
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store double %r2, ptr addrspace(1) %out
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ret void
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}
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; SI-LABEL: {{^}}s_fsub_f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @s_fsub_f64(ptr addrspace(1) %out, double %a, double %b) {
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%sub = fsub double %a, %b
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store double %sub, ptr addrspace(1) %out
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ret void
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}
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; SI-LABEL: {{^}}s_fsub_imm_f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], -s\[[0-9]+:[0-9]+\]}}, 4.0
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define amdgpu_kernel void @s_fsub_imm_f64(ptr addrspace(1) %out, double %a, double %b) {
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%sub = fsub double 4.0, %a
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store double %sub, ptr addrspace(1) %out
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ret void
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}
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; SI-LABEL: {{^}}s_fsub_imm_inv_f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\]}}, -4.0
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define amdgpu_kernel void @s_fsub_imm_inv_f64(ptr addrspace(1) %out, double %a, double %b) {
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%sub = fsub double %a, 4.0
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store double %sub, ptr addrspace(1) %out
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ret void
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}
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; SI-LABEL: {{^}}s_fsub_self_f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -s\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @s_fsub_self_f64(ptr addrspace(1) %out, double %a) {
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%sub = fsub double %a, %a
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store double %sub, ptr addrspace(1) %out
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ret void
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}
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; SI-LABEL: {{^}}fsub_v2f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @fsub_v2f64(ptr addrspace(1) %out, <2 x double> %a, <2 x double> %b) {
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%sub = fsub <2 x double> %a, %b
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store <2 x double> %sub, ptr addrspace(1) %out
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ret void
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}
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; SI-LABEL: {{^}}fsub_v4f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @fsub_v4f64(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%b_ptr = getelementptr <4 x double>, ptr addrspace(1) %in, i32 1
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%a = load <4 x double>, ptr addrspace(1) %in
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%b = load <4 x double>, ptr addrspace(1) %b_ptr
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%result = fsub <4 x double> %a, %b
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store <4 x double> %result, ptr addrspace(1) %out
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ret void
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}
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; SI-LABEL: {{^}}s_fsub_v4f64:
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], s\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @s_fsub_v4f64(ptr addrspace(1) %out, <4 x double> %a, <4 x double> %b) {
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%result = fsub <4 x double> %a, %b
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store <4 x double> %result, ptr addrspace(1) %out, align 16
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ret void
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}
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attributes #0 = { nounwind readnone }
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