373ce14760
To generate zero value, the PXOR instruction need 3 operands that is tied to the same vreg. If is not good in SSA form and with undef value two address instruction pass may convert `%0:vr128 = PXORrr undef %0, undef %0` to `%1:vr128 = PXORrr undef %1:vr128(tied-def 0), undef %0:vr128`. It is not expected. It can be simplified to SET0 instruction which only take 1 destination operand. It should be more friendly to two address instruction pass and register allocation pass. `%0:vr128 = V_SET0` Also add AVX1 code path so that it is consistant to other code. Differential Revision: https://reviews.llvm.org/D124903
54 lines
2.9 KiB
LLVM
54 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+amx-tile,+amx-int8,+amx-bf16,+avx512f -verify-machineinstrs | FileCheck %s
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define void @test_amx(i8* %pointer, i8* %base, i64 %stride) {
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; CHECK-LABEL: test_amx:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; CHECK-NEXT: vmovups %zmm0, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb $1, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb $8, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw $8, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb $8, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw $8, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movb $8, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw $8, -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: ldtilecfg -{{[0-9]+}}(%rsp)
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; CHECK-NEXT: movw $8, %ax
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; CHECK-NEXT: tilezero %tmm0
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; CHECK-NEXT: tileloadd (%rsi,%rdx), %tmm1
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; CHECK-NEXT: tileloadd (%rsi,%rdx), %tmm2
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; CHECK-NEXT: tdpbssd %tmm2, %tmm1, %tmm0
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; CHECK-NEXT: tdpbsud %tmm2, %tmm1, %tmm0
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; CHECK-NEXT: tdpbusd %tmm2, %tmm1, %tmm0
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; CHECK-NEXT: tdpbuud %tmm2, %tmm1, %tmm0
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; CHECK-NEXT: tdpbf16ps %tmm2, %tmm1, %tmm0
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; CHECK-NEXT: tileloaddt1 (%rsi,%rdx), %tmm1
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; CHECK-NEXT: tilestored %tmm0, (%rdi,%rdx)
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; CHECK-NEXT: tilerelease
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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%c = call x86_amx @llvm.x86.tilezero.internal(i16 8, i16 8)
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%a = call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 8, i8* %base, i64 %stride)
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%b = call x86_amx @llvm.x86.tileloadd64.internal(i16 8, i16 8, i8* %base, i64 %stride)
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%d0 = call x86_amx @llvm.x86.tdpbssd.internal(i16 8, i16 8, i16 8, x86_amx %c, x86_amx %a, x86_amx %b)
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%d1 = call x86_amx @llvm.x86.tdpbsud.internal(i16 8, i16 8, i16 8, x86_amx %d0, x86_amx %a, x86_amx %b)
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%d2 = call x86_amx @llvm.x86.tdpbusd.internal(i16 8, i16 8, i16 8, x86_amx %d1, x86_amx %a, x86_amx %b)
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%d3 = call x86_amx @llvm.x86.tdpbuud.internal(i16 8, i16 8, i16 8, x86_amx %d2, x86_amx %a, x86_amx %b)
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%d4 = call x86_amx @llvm.x86.tdpbf16ps.internal(i16 8, i16 8, i16 8, x86_amx %d3, x86_amx %a, x86_amx %b)
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%e = call x86_amx @llvm.x86.tileloaddt164.internal(i16 8, i16 8, i8* %base, i64 %stride)
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call void @llvm.x86.tilestored64.internal(i16 8, i16 8, i8* %pointer, i64 %stride, x86_amx %d4)
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ret void
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}
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declare x86_amx @llvm.x86.tilezero.internal(i16, i16)
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declare x86_amx @llvm.x86.tileloadd64.internal(i16, i16, i8*, i64)
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declare x86_amx @llvm.x86.tileloaddt164.internal(i16, i16, i8*, i64)
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declare x86_amx @llvm.x86.tdpbssd.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
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declare x86_amx @llvm.x86.tdpbsud.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
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declare x86_amx @llvm.x86.tdpbusd.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
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declare x86_amx @llvm.x86.tdpbuud.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
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declare x86_amx @llvm.x86.tdpbf16ps.internal(i16, i16, i16, x86_amx, x86_amx, x86_amx)
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declare void @llvm.x86.tilestored64.internal(i16, i16, i8*, i64, x86_amx)
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