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clang-p2996/llvm/lib/Target/RISCV
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Craig Topper ab2348a6fa [RISCV] Add sext.b/h and zext.b/h/w to RISCVInstrInfo::foldMemoryOperandImpl. 
We can always fold zext.b since it is just andi. The others require
Zba/Zbb.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D130302
2022-07-21 14:54:58 -07:00
..
AsmParser
[RISCV] Implement support for the Zicbop extension
2022-06-28 12:43:26 +01:00
Disassembler
Rename MCFixedLenDisassembler.h as MCDecoderOps.h
2022-05-15 08:44:58 +08:00
MCTargetDesc
[CodeGen] Move instruction predicate verification to emitInstruction
2022-07-14 09:33:28 +01:00
TargetInfo
…
CMakeLists.txt
[RISCV] Add a RISCV specific CodeGenPrepare pass.
2022-07-14 10:20:59 -07:00
RISCV.h
[RISCV] Add a RISCV specific CodeGenPrepare pass.
2022-07-14 10:20:59 -07:00
RISCV.td
[RISCV][Clang] Add support for Zmmul extension
2022-07-18 20:26:08 -04:00
RISCVAsmPrinter.cpp
[CodeGen] Move instruction predicate verification to emitInstruction
2022-07-14 09:33:28 +01:00
RISCVCallingConv.td
[RISCV] Rename FPRs and use Register arithmetic
2019-09-27 15:49:10 +00:00
RISCVCallLowering.cpp
[GlobalISel] Base implementation for sret demotion.
2021-01-06 10:30:50 +05:30
RISCVCallLowering.h
…
RISCVCodeGenPrepare.cpp
[RISCV] Teach RISCVCodeGenPrepare to optimize (i64 (and (zext/sext (i32 X), C1)))
2022-07-17 11:00:56 -07:00
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
[RISCV] Fixing undefined physical register issue when subreg liveness tracking enabled.
2022-06-15 16:23:39 +08:00
RISCVFrameLowering.cpp
[RISCV] Add early-exit to RVV stack computation. NFCI.
2022-07-13 08:50:08 +01:00
RISCVFrameLowering.h
[RISCV] Add early-exit to RVV stack computation. NFCI.
2022-07-13 08:50:08 +01:00
RISCVGatherScatterLowering.cpp
[RISCV] Don't require loop simplify form in RISCVGatherScatterLowering.
2022-06-10 13:00:20 -07:00
RISCVInsertVSETVLI.cpp
Revert "[RISCV] Avoid changing etype for splat of 0 or -1"
2022-06-29 10:27:02 -07:00
RISCVInstrFormats.td
[RISCV] Support mask policy for RVV IR intrinsics.
2022-03-22 01:19:16 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
…
RISCVInstrInfo.cpp
[RISCV] Add sext.b/h and zext.b/h/w to RISCVInstrInfo::foldMemoryOperandImpl.
2022-07-21 14:54:58 -07:00
RISCVInstrInfo.h
[RISCV] Add sext.b/h and zext.b/h/w to RISCVInstrInfo::foldMemoryOperandImpl.
2022-07-21 14:54:58 -07:00
RISCVInstrInfo.td
[RISCV] Add isel patterns for ineg+setge/le/uge/ule.
2022-07-18 09:55:01 -07:00
RISCVInstrInfoA.td
[RISCV] Reduce scalar load/store isel patterns to a single ComplexPattern. NFCI
2022-06-03 09:00:17 -07:00
RISCVInstrInfoC.td
…
RISCVInstrInfoD.td
[RISCV] Add more patterns for FNMADD
2022-06-04 12:31:45 +08:00
RISCVInstrInfoF.td
[RISCV] Add more patterns for FNMADD
2022-06-04 12:31:45 +08:00
RISCVInstrInfoM.td
[RISCV][Clang] Add support for Zmmul extension
2022-07-18 20:26:08 -04:00
RISCVInstrInfoV.td
[RISCV] Add scheduling resources for vector segment instructions.
2022-07-12 22:51:58 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Remove true_mask patterns for VRGATHERE16..
2022-06-21 11:59:37 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Increase complexity of RVV element extraction patterns
2022-07-11 10:53:15 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Mark fminnum_vl and fmaxnum_vl as commutable.
2022-07-08 10:19:09 -07:00
RISCVInstrInfoZb.td
[RISCV] Move some SHXADD matching cases into a ComplexPattern. NFC
2022-07-03 21:57:05 -07:00
RISCVInstrInfoZfh.td
[RISCV] Add more patterns for FNMADD
2022-06-04 12:31:45 +08:00
RISCVInstrInfoZicbo.td
[RISCV] Implement support for the Zicbop extension
2022-06-28 12:43:26 +01:00
RISCVInstrInfoZk.td
…
RISCVInstructionSelector.cpp
[Target] Remove redundant member initialization (NFC)
2022-01-06 22:01:44 -08:00
RISCVISelDAGToDAG.cpp
[RISCV] Recognize bexti from (srl (and X, 1<<C), C).
2022-07-20 15:03:52 -07:00
RISCVISelDAGToDAG.h
[RISCV] Remove doPeepholeLoadStoreADDI.
2022-07-11 10:44:33 -07:00
RISCVISelLowering.cpp
[RISCV] Combine (select_cc (srl (and X, 1<<C), C), 0, eq/ne, true, fale)
2022-07-20 22:32:11 -07:00
RISCVISelLowering.h
[RISCV] Exploit fact that vscale is always power of two to replace urem sequence
2022-07-13 10:54:47 -07:00
RISCVLegalizerInfo.cpp
[globalisel][legalizer] Separate the deprecated LegalizerInfo from the current one
2021-06-01 13:23:48 -07:00
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.cpp
llvm-reduce: Add cloning of target MachineFunctionInfo
2022-06-07 10:14:48 -04:00
RISCVMachineFunctionInfo.h
llvm-reduce: Add cloning of target MachineFunctionInfo
2022-06-07 10:14:48 -04:00
RISCVMacroFusion.cpp
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVMacroFusion.h
[RISCV] Add macrofusion infrastructure and one example usage.
2022-06-23 08:38:39 -07:00
RISCVMakeCompressible.cpp
[RISCV] Fix wrong register rename for store value during make-compressible optimization
2022-07-08 18:07:17 +08:00
RISCVMCInstLower.cpp
[RISCV] Move some methods out of RISCVInstrInfo and into RISCV namespace.
2022-06-12 10:47:21 -07:00
RISCVMergeBaseOffset.cpp
[RISCV] Teach RISCVMergeBaseOffset to handle read-modify-write of a global.
2022-06-28 11:46:24 -07:00
RISCVRedundantCopyElimination.cpp
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
RISCVRegisterBankInfo.cpp
[Target] Apply clang-tidy fixes for readability-redundant-member-init (NFC)
2022-03-27 22:22:37 -07:00
RISCVRegisterBankInfo.h
[nfc][codegen] Move RegisterBank[Info].h under CodeGen
2022-03-01 21:53:25 -08:00
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
[RISCV] Add a scavenge spill slot when use ADDI to compute scalable stack offset
2022-07-03 20:18:13 +08:00
RISCVRegisterInfo.h
…
RISCVRegisterInfo.td
[RISCV] Add llvm.read.register support for vlenb
2022-05-13 09:12:02 -07:00
RISCVSchedRocket.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVSchedSiFive7.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVSchedule.td
…
RISCVScheduleB.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVScheduleV.td
[RISCV] Add scheduling resources for vector segment instructions.
2022-07-12 22:51:58 -07:00
RISCVSExtWRemoval.cpp
[RISCV] Fold stack reload into sext.w by using lw instead of ld.
2022-07-18 09:09:17 -07:00
RISCVSubtarget.cpp
[RISCV] Disable subregister liveness by default
2022-07-14 17:04:10 +01:00
RISCVSubtarget.h
[RISCV][Clang] Add support for Zmmul extension
2022-07-18 20:26:08 -04:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp
[RISCV] Teach RISCVCodeGenPrepare to optimize (i64 (and (zext/sext (i32 X), C1)))
2022-07-17 11:00:56 -07:00
RISCVTargetMachine.h
[RISCV] Store/restore RISCVMachineFunctionInfo into MIR YAML file
2022-04-08 11:55:48 +08:00
RISCVTargetObjectFile.cpp
ELF: Create unique SHF_GNU_RETAIN sections for llvm.used global objects
2021-02-26 16:38:44 -08:00
RISCVTargetObjectFile.h
[Target] Use Align in TargetLoweringObjectFile::getSectionForConstant.
2020-05-21 15:23:29 -07:00
RISCVTargetTransformInfo.cpp
[RISCV] Add cost model for vector.reverse mask operation
2022-07-15 06:58:57 +00:00
RISCVTargetTransformInfo.h
[LoopVectorize] Add option to use active lane mask for loop control flow
2022-07-11 13:46:55 +01:00