5c45ae4108
Current implementation will rename both register in store instructions if we store base address into memory with same base register, it's OK if the offset is 0, however that is wrong transform if offset isn't 0, give a smalle example here: sd a0, 808(a0) We should not transform into: addi a2, a0, 768 sd a2, 40(a2) That should just rename base address like this: addi a2, a0, 768 sd a0, 40(a2) Reviewed By: asb Differential Revision: https://reviews.llvm.org/D128876
391 lines
14 KiB
C++
391 lines
14 KiB
C++
//===-- RISCVMakeCompressible.cpp - Make more instructions compressible ---===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass searches for instructions that are prevented from being compressed
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// by one of the following:
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//
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// 1. The use of a single uncompressed register.
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// 2. A base register + offset where the offset is too large to be compressed
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// and the base register may or may not be compressed.
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//
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//
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// For case 1, if a compressed register is available, then the uncompressed
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// register is copied to the compressed register and its uses are replaced.
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//
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// For example, storing zero uses the uncompressible zero register:
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// sw zero, 0(a0) # if zero
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// sw zero, 8(a0) # if zero
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// sw zero, 4(a0) # if zero
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// sw zero, 24(a0) # if zero
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//
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// If a compressed register (e.g. a1) is available, the above can be transformed
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// to the following to improve code size:
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// li a1, 0
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// c.sw a1, 0(a0)
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// c.sw a1, 8(a0)
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// c.sw a1, 4(a0)
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// c.sw a1, 24(a0)
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//
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//
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// For case 2, if a compressed register is available, then the original base
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// is copied and adjusted such that:
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//
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// new_base_register = base_register + adjustment
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// base_register + large_offset = new_base_register + small_offset
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//
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// For example, the following offsets are too large for c.sw:
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// lui a2, 983065
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// sw a1, -236(a2)
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// sw a1, -240(a2)
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// sw a1, -244(a2)
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// sw a1, -248(a2)
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// sw a1, -252(a2)
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// sw a0, -256(a2)
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//
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// If a compressed register is available (e.g. a3), a new base could be created
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// such that the addresses can accessed with a compressible offset, thus
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// improving code size:
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// lui a2, 983065
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// addi a3, a2, -256
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// c.sw a1, 20(a3)
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// c.sw a1, 16(a3)
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// c.sw a1, 12(a3)
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// c.sw a1, 8(a3)
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// c.sw a1, 4(a3)
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// c.sw a0, 0(a3)
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//
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//
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// This optimization is only applied if there are enough uses of the copied
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// register for code size to be reduced.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-make-compressible"
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#define RISCV_COMPRESS_INSTRS_NAME "RISCV Make Compressible"
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namespace {
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struct RISCVMakeCompressibleOpt : public MachineFunctionPass {
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static char ID;
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bool runOnMachineFunction(MachineFunction &Fn) override;
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RISCVMakeCompressibleOpt() : MachineFunctionPass(ID) {
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initializeRISCVMakeCompressibleOptPass(*PassRegistry::getPassRegistry());
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}
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StringRef getPassName() const override { return RISCV_COMPRESS_INSTRS_NAME; }
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};
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} // namespace
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char RISCVMakeCompressibleOpt::ID = 0;
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INITIALIZE_PASS(RISCVMakeCompressibleOpt, "riscv-make-compressible",
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RISCV_COMPRESS_INSTRS_NAME, false, false)
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// Return log2(widthInBytes) of load/store done by Opcode.
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static unsigned log2LdstWidth(unsigned Opcode) {
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switch (Opcode) {
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default:
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llvm_unreachable("Unexpected opcode");
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case RISCV::LW:
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case RISCV::SW:
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case RISCV::FLW:
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case RISCV::FSW:
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return 2;
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case RISCV::LD:
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case RISCV::SD:
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case RISCV::FLD:
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case RISCV::FSD:
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return 3;
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}
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}
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// Return a mask for the offset bits of a non-stack-pointer based compressed
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// load/store.
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static uint8_t compressedLDSTOffsetMask(unsigned Opcode) {
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return 0x1f << log2LdstWidth(Opcode);
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}
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// Return true if Offset fits within a compressed stack-pointer based
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// load/store.
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static bool compressibleSPOffset(int64_t Offset, unsigned Opcode) {
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return log2LdstWidth(Opcode) == 2 ? isShiftedUInt<6, 2>(Offset)
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: isShiftedUInt<6, 3>(Offset);
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}
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// Given an offset for a load/store, return the adjustment required to the base
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// register such that the address can be accessed with a compressible offset.
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// This will return 0 if the offset is already compressible.
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static int64_t getBaseAdjustForCompression(int64_t Offset, unsigned Opcode) {
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// Return the excess bits that do not fit in a compressible offset.
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return Offset & ~compressedLDSTOffsetMask(Opcode);
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}
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// Return true if Reg is in a compressed register class.
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static bool isCompressedReg(Register Reg) {
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return RISCV::GPRCRegClass.contains(Reg) ||
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RISCV::FPR32CRegClass.contains(Reg) ||
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RISCV::FPR64CRegClass.contains(Reg);
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}
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// Return true if MI is a load for which there exists a compressed version.
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static bool isCompressibleLoad(const MachineInstr &MI) {
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const RISCVSubtarget &STI = MI.getMF()->getSubtarget<RISCVSubtarget>();
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const unsigned Opcode = MI.getOpcode();
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return Opcode == RISCV::LW || (!STI.is64Bit() && Opcode == RISCV::FLW) ||
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Opcode == RISCV::LD || Opcode == RISCV::FLD;
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}
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// Return true if MI is a store for which there exists a compressed version.
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static bool isCompressibleStore(const MachineInstr &MI) {
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const RISCVSubtarget &STI = MI.getMF()->getSubtarget<RISCVSubtarget>();
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const unsigned Opcode = MI.getOpcode();
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return Opcode == RISCV::SW || (!STI.is64Bit() && Opcode == RISCV::FSW) ||
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Opcode == RISCV::SD || Opcode == RISCV::FSD;
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}
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// Find a single register and/or large offset which, if compressible, would
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// allow the given instruction to be compressed.
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//
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// Possible return values:
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//
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// {Reg, 0} - Uncompressed Reg needs replacing with a compressed
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// register.
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// {Reg, N} - Reg needs replacing with a compressed register and
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// N needs adding to the new register. (Reg may be
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// compressed or uncompressed).
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// {RISCV::NoRegister, 0} - No suitable optimization found for this
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// instruction.
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static RegImmPair getRegImmPairPreventingCompression(const MachineInstr &MI) {
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const unsigned Opcode = MI.getOpcode();
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if (isCompressibleLoad(MI) || isCompressibleStore(MI)) {
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const MachineOperand &MOImm = MI.getOperand(2);
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if (!MOImm.isImm())
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return RegImmPair(RISCV::NoRegister, 0);
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int64_t Offset = MOImm.getImm();
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int64_t NewBaseAdjust = getBaseAdjustForCompression(Offset, Opcode);
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Register Base = MI.getOperand(1).getReg();
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// Memory accesses via the stack pointer do not have a requirement for
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// either of the registers to be compressible and can take a larger offset.
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if (RISCV::SPRegClass.contains(Base)) {
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if (!compressibleSPOffset(Offset, Opcode) && NewBaseAdjust)
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return RegImmPair(Base, NewBaseAdjust);
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} else {
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Register SrcDest = MI.getOperand(0).getReg();
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bool SrcDestCompressed = isCompressedReg(SrcDest);
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bool BaseCompressed = isCompressedReg(Base);
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// If only Base and/or offset prevent compression, then return Base and
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// any adjustment required to make the offset compressible.
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if ((!BaseCompressed || NewBaseAdjust) && SrcDestCompressed)
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return RegImmPair(Base, NewBaseAdjust);
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// For loads, we can only change the base register since dest is defined
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// rather than used.
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//
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// For stores, we can change SrcDest (and Base if SrcDest == Base) but
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// cannot resolve an uncompressible offset in this case.
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if (isCompressibleStore(MI)) {
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if (!SrcDestCompressed && (BaseCompressed || SrcDest == Base) &&
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!NewBaseAdjust)
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return RegImmPair(SrcDest, NewBaseAdjust);
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}
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}
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}
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return RegImmPair(RISCV::NoRegister, 0);
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}
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// Check all uses after FirstMI of the given register, keeping a vector of
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// instructions that would be compressible if the given register (and offset if
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// applicable) were compressible.
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//
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// If there are enough uses for this optimization to improve code size and a
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// compressed register is available, return that compressed register.
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static Register analyzeCompressibleUses(MachineInstr &FirstMI,
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RegImmPair RegImm,
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SmallVectorImpl<MachineInstr *> &MIs) {
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MachineBasicBlock &MBB = *FirstMI.getParent();
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const TargetRegisterInfo *TRI =
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MBB.getParent()->getSubtarget().getRegisterInfo();
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RegScavenger RS;
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RS.enterBasicBlock(MBB);
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for (MachineBasicBlock::instr_iterator I = FirstMI.getIterator(),
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E = MBB.instr_end();
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I != E; ++I) {
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MachineInstr &MI = *I;
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// Determine if this is an instruction which would benefit from using the
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// new register.
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RegImmPair CandidateRegImm = getRegImmPairPreventingCompression(MI);
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if (CandidateRegImm.Reg == RegImm.Reg &&
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CandidateRegImm.Imm == RegImm.Imm) {
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// Advance tracking since the value in the new register must be live for
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// this instruction too.
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RS.forward(I);
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MIs.push_back(&MI);
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}
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// If RegImm.Reg is modified by this instruction, then we cannot optimize
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// past this instruction. If the register is already compressed, then it may
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// possible to optimize a large offset in the current instruction - this
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// will have been detected by the preceeding call to
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// getRegImmPairPreventingCompression.
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if (MI.modifiesRegister(RegImm.Reg, TRI))
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break;
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}
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// Adjusting the base costs one new uncompressed addi and therefore three uses
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// are required for a code size reduction. If no base adjustment is required,
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// then copying the register costs one new c.mv (or c.li Rd, 0 for "copying"
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// the zero register) and therefore two uses are required for a code size
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// reduction.
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if (MIs.size() < 2 || (RegImm.Imm != 0 && MIs.size() < 3))
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return RISCV::NoRegister;
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// Find a compressible register which will be available from the first
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// instruction we care about to the last.
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const TargetRegisterClass *RCToScavenge;
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// Work out the compressed register class from which to scavenge.
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if (RISCV::GPRRegClass.contains(RegImm.Reg))
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RCToScavenge = &RISCV::GPRCRegClass;
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else if (RISCV::FPR32RegClass.contains(RegImm.Reg))
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RCToScavenge = &RISCV::FPR32CRegClass;
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else if (RISCV::FPR64RegClass.contains(RegImm.Reg))
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RCToScavenge = &RISCV::FPR64CRegClass;
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else
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return RISCV::NoRegister;
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return RS.scavengeRegisterBackwards(*RCToScavenge, FirstMI.getIterator(),
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/*RestoreAfter=*/false, /*SPAdj=*/0,
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/*AllowSpill=*/false);
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}
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// Update uses of the old register in the given instruction to the new register.
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static void updateOperands(MachineInstr &MI, RegImmPair OldRegImm,
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Register NewReg) {
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unsigned Opcode = MI.getOpcode();
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// If this pass is extended to support more instructions, the check for
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// definedness may need to be strengthened.
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assert((isCompressibleLoad(MI) || isCompressibleStore(MI)) &&
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"Unsupported instruction for this optimization.");
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int SkipN = 0;
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// Skip the first (value) operand to a store instruction (except if the store
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// offset is zero) in order to avoid an incorrect transformation.
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// e.g. sd a0, 808(a0) to addi a2, a0, 768; sd a2, 40(a2)
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if (isCompressibleStore(MI) && OldRegImm.Imm != 0)
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SkipN = 1;
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// Update registers
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for (MachineOperand &MO : drop_begin(MI.operands(), SkipN))
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if (MO.isReg() && MO.getReg() == OldRegImm.Reg) {
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// Do not update operands that define the old register.
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//
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// The new register was scavenged for the range of instructions that are
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// being updated, therefore it should not be defined within this range
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// except possibly in the final instruction.
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if (MO.isDef()) {
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assert(isCompressibleLoad(MI));
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continue;
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}
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// Update reg
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MO.setReg(NewReg);
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}
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// Update offset
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MachineOperand &MOImm = MI.getOperand(2);
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int64_t NewOffset = MOImm.getImm() & compressedLDSTOffsetMask(Opcode);
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MOImm.setImm(NewOffset);
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}
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bool RISCVMakeCompressibleOpt::runOnMachineFunction(MachineFunction &Fn) {
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// This is a size optimization.
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if (skipFunction(Fn.getFunction()) || !Fn.getFunction().hasMinSize())
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return false;
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const RISCVSubtarget &STI = Fn.getSubtarget<RISCVSubtarget>();
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const RISCVInstrInfo &TII = *STI.getInstrInfo();
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// This optimization only makes sense if compressed instructions are emitted.
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if (!STI.hasStdExtC())
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return false;
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for (MachineBasicBlock &MBB : Fn) {
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LLVM_DEBUG(dbgs() << "MBB: " << MBB.getName() << "\n");
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for (MachineInstr &MI : MBB) {
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// Determine if this instruction would otherwise be compressed if not for
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// an uncompressible register or offset.
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RegImmPair RegImm = getRegImmPairPreventingCompression(MI);
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if (!RegImm.Reg && RegImm.Imm == 0)
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continue;
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// Determine if there is a set of instructions for which replacing this
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// register with a compressed register (and compressible offset if
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// applicable) is possible and will allow compression.
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SmallVector<MachineInstr *, 8> MIs;
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Register NewReg = analyzeCompressibleUses(MI, RegImm, MIs);
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if (!NewReg)
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continue;
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// Create the appropriate copy and/or offset.
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if (RISCV::GPRRegClass.contains(RegImm.Reg)) {
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assert(isInt<12>(RegImm.Imm));
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BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(RISCV::ADDI), NewReg)
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.addReg(RegImm.Reg)
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.addImm(RegImm.Imm);
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} else {
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// If we are looking at replacing an FPR register we don't expect to
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// have any offset. The only compressible FP instructions with an offset
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// are loads and stores, for which the offset applies to the GPR operand
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// not the FPR operand.
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assert(RegImm.Imm == 0);
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unsigned Opcode = RISCV::FPR32RegClass.contains(RegImm.Reg)
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? RISCV::FSGNJ_S
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: RISCV::FSGNJ_D;
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BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(Opcode), NewReg)
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.addReg(RegImm.Reg)
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.addReg(RegImm.Reg);
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}
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// Update the set of instructions to use the compressed register and
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// compressible offset instead. These instructions should now be
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// compressible.
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// TODO: Update all uses if RegImm.Imm == 0? Not just those that are
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// expected to become compressible.
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for (MachineInstr *UpdateMI : MIs)
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updateOperands(*UpdateMI, RegImm, NewReg);
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}
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}
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return true;
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}
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/// Returns an instance of the Make Compressible Optimization pass.
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FunctionPass *llvm::createRISCVMakeCompressibleOptPass() {
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return new RISCVMakeCompressibleOpt();
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}
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