8dbc6398e1
The CSR renaming further prepares the way for an upcoming patch adding support for more RISC-V ABIs. Modify RISCVRegisterInfo::getCalleeSavedRegs and RISCVRegisterInfo::getReservedRegs to do MF->getSubtarget<RISCVSubtarget>() once rather than multiple times. llvm-svn: 356123
58 lines
2.0 KiB
TableGen
58 lines
2.0 KiB
TableGen
//===-- RISCVCallingConv.td - Calling Conventions RISCV ----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the RISCV architecture.
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//
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//===----------------------------------------------------------------------===//
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// The RISC-V calling convention is handled with custom code in
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// RISCVISelLowering.cpp (CC_RISCV).
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def CSR_ILP32_LP64
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: CalleeSavedRegs<(add X1, X3, X4, X8, X9, (sequence "X%u", 18, 27))>;
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// Needed for implementation of RISCVRegisterInfo::getNoPreservedMask()
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def CSR_NoRegs : CalleeSavedRegs<(add)>;
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// Interrupt handler needs to save/restore all registers that are used,
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// both Caller and Callee saved registers.
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def CSR_Interrupt : CalleeSavedRegs<(add X1,
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(sequence "X%u", 3, 9),
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(sequence "X%u", 10, 11),
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(sequence "X%u", 12, 17),
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(sequence "X%u", 18, 27),
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(sequence "X%u", 28, 31))>;
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// Same as CSR_Interrupt, but including all 32-bit FP registers.
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def CSR_XLEN_F32_Interrupt: CalleeSavedRegs<(add X1,
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(sequence "X%u", 3, 9),
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(sequence "X%u", 10, 11),
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(sequence "X%u", 12, 17),
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(sequence "X%u", 18, 27),
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(sequence "X%u", 28, 31),
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(sequence "F%u_32", 0, 7),
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(sequence "F%u_32", 10, 11),
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(sequence "F%u_32", 12, 17),
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(sequence "F%u_32", 28, 31),
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(sequence "F%u_32", 8, 9),
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(sequence "F%u_32", 18, 27))>;
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// Same as CSR_Interrupt, but including all 64-bit FP registers.
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def CSR_XLEN_F64_Interrupt: CalleeSavedRegs<(add X1,
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(sequence "X%u", 3, 9),
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(sequence "X%u", 10, 11),
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(sequence "X%u", 12, 17),
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(sequence "X%u", 18, 27),
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(sequence "X%u", 28, 31),
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(sequence "F%u_64", 0, 7),
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(sequence "F%u_64", 10, 11),
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(sequence "F%u_64", 12, 17),
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(sequence "F%u_64", 28, 31),
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(sequence "F%u_64", 8, 9),
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(sequence "F%u_64", 18, 27))>;
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