4d33918034
Unlike SelectionDAG, treat this as a normally legalizable operation. In SelectionDAG this is supposed to only ever formed if it's legal, but I've found that to be restricting. For AMDGPU this is contextually legal depending on whether denormal flushing is allowed in the use function. Technically we currently treat the denormal mode as a subtarget feature, so custom lowering could be avoided. However I consider this to be a defect, and this should be contextually dependent on the controllable rounding mode of the parent function. llvm-svn: 371800
92 lines
3.9 KiB
C++
92 lines
3.9 KiB
C++
//===- AMDGPULegalizerInfo ---------------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the Machinelegalizer class for
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/// AMDGPU.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUMACHINELEGALIZER_H
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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#include "AMDGPUArgumentUsageInfo.h"
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namespace llvm {
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class GCNTargetMachine;
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class LLVMContext;
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class GCNSubtarget;
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/// This class provides the information for the target register banks.
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class AMDGPULegalizerInfo : public LegalizerInfo {
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const GCNSubtarget &ST;
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public:
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AMDGPULegalizerInfo(const GCNSubtarget &ST,
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const GCNTargetMachine &TM);
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bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B,
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GISelChangeObserver &Observer) const override;
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Register getSegmentAperture(unsigned AddrSpace,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, bool Signed) const;
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bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeLoad(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B,
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GISelChangeObserver &Observer) const;
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bool legalizeFMad(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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Register getLiveInRegister(MachineRegisterInfo &MRI,
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Register Reg, LLT Ty) const;
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bool loadInputValue(Register DstReg, MachineIRBuilder &B,
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const ArgDescriptor *Arg) const;
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bool legalizePreloadedArgIntrin(
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MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
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AMDGPUFunctionArgInfo::PreloadedValue ArgType) const;
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bool legalizeFDIVFast(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeImplicitArgPtr(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B, unsigned AddrSpace) const;
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bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const override;
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};
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} // End llvm namespace.
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#endif
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