Lewis Revill 7abf863f76 [RISCV] Lower inline asm constraint A for RISC-V ...

This allows arguments with the constraint A to be lowered to input nodes
for RISC-V, which implies a memory address stored in a register.

This patch adds the minimal amount of code required to get operands with
the right constraints to compile.

https://reviews.llvm.org/D54296

llvm-svn: 369095

2019-08-16 10:28:34 +00:00

9.3 KiB

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