4a4987be36
Generate more efficient code for zero or sign extensions where the source is a subvector generated via SHUFFLE_VECTOR. Specifically, recognize patterns corresponding to (series of) VECTOR UNPACK instructions, or the VECTOR SIGN EXTEND TO DOUBLEWORD instruction. As a special case, also handle zero or sign extensions of a vector element to i128. Fixes: https://github.com/llvm/llvm-project/issues/129576 Fixes: https://github.com/llvm/llvm-project/issues/129899
71 lines
2.0 KiB
LLVM
71 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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define <8 x i16> @f1(<16 x i8> %a) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: vuplhb %v24, %v24
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; CHECK-NEXT: br %r14
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start:
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%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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%1 = zext <8 x i8> %0 to <8 x i16>
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ret <8 x i16> %1
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}
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define <8 x i16> @f2(<16 x i8> %a) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: vupllb %v24, %v24
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; CHECK-NEXT: br %r14
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start:
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%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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%1 = zext <8 x i8> %0 to <8 x i16>
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ret <8 x i16> %1
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}
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define <4 x i32> @f3(<8 x i16> %a) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: vuplhh %v24, %v24
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; CHECK-NEXT: br %r14
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start:
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%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%1 = zext <4 x i16> %0 to <4 x i32>
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ret <4 x i32> %1
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}
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define <4 x i32> @f4(<8 x i16> %a) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: vupllh %v24, %v24
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; CHECK-NEXT: br %r14
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start:
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%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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%1 = zext <4 x i16> %0 to <4 x i32>
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ret <4 x i32> %1
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}
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define <2 x i64> @f5(<4 x i32> %a) {
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; CHECK-LABEL: f5:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: vuplhf %v24, %v24
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; CHECK-NEXT: br %r14
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start:
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%0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 1>
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%1 = zext <2 x i32> %0 to <2 x i64>
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ret <2 x i64> %1
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}
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define <2 x i64> @f6(<4 x i32> %a) {
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; CHECK-LABEL: f6:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: vupllf %v24, %v24
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; CHECK-NEXT: br %r14
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start:
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%0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
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%1 = zext <2 x i32> %0 to <2 x i64>
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ret <2 x i64> %1
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}
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