6599961c17
This patch contains following enhancements to SrcRegMap and DstRegMap:
1 In findOnlyInterestingUse not only check if the Reg is two address usage,
but also check after commutation can it be two address usage.
2 If a physical register is clobbered, remove SrcRegMap entries that are
mapped to it.
3 In processTiedPairs, when create a new COPY instruction, add a SrcRegMap
entry only when the COPY instruction is coalescable. (The COPY src is
killed)
With these enhancements isProfitableToCommute can do better commute decision,
and finally more register copies are removed.
Differential Revision: https://reviews.llvm.org/D108731
172 lines
5.4 KiB
LLVM
172 lines
5.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE2
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE,SSE42
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
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; PR28925
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define <4 x i32> @test1(<4 x i1> %cond, <4 x i32> %x) {
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; SSE-LABEL: test1:
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; SSE: # %bb.0:
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; SSE-NEXT: pslld $31, %xmm0
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; SSE-NEXT: psrad $31, %xmm0
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; SSE-NEXT: pandn %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test1:
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; AVX: # %bb.0:
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; AVX-NEXT: vpslld $31, %xmm0, %xmm0
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; AVX-NEXT: vpsrad $31, %xmm0, %xmm0
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; AVX-NEXT: vpandn %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %x
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ret <4 x i32> %r
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}
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define <4 x i32> @test2(<4 x float> %a, <4 x float> %b, <4 x i32> %x) {
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; SSE-LABEL: test2:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpneqps %xmm1, %xmm0
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; SSE-NEXT: andps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: test2:
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; AVX: # %bb.0:
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; AVX-NEXT: vcmpneqps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vandps %xmm2, %xmm0, %xmm0
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; AVX-NEXT: retq
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%cond = fcmp oeq <4 x float> %a, %b
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%r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %x
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ret <4 x i32> %r
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}
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define float @fsel_zero_false_val(float %a, float %b, float %x) {
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; SSE-LABEL: fsel_zero_false_val:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpeqss %xmm1, %xmm0
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; SSE-NEXT: andps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: fsel_zero_false_val:
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; AVX: # %bb.0:
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; AVX-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vandps %xmm2, %xmm0, %xmm0
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; AVX-NEXT: retq
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%cond = fcmp oeq float %a, %b
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%r = select i1 %cond, float %x, float 0.0
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ret float %r
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}
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define float @fsel_zero_true_val(float %a, float %b, float %x) {
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; SSE-LABEL: fsel_zero_true_val:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpeqss %xmm1, %xmm0
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; SSE-NEXT: andnps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: fsel_zero_true_val:
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; AVX: # %bb.0:
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; AVX-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vandnps %xmm2, %xmm0, %xmm0
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; AVX-NEXT: retq
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%cond = fcmp oeq float %a, %b
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%r = select i1 %cond, float 0.0, float %x
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ret float %r
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}
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define double @fsel_nonzero_false_val(double %x, double %y, double %z) {
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; SSE-LABEL: fsel_nonzero_false_val:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpeqsd %xmm1, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm2
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; SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
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; SSE-NEXT: andnpd %xmm1, %xmm0
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; SSE-NEXT: orpd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: fsel_nonzero_false_val:
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; AVX: # %bb.0:
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; AVX-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
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; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm1, %xmm0
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; AVX-NEXT: retq
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%cond = fcmp oeq double %x, %y
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%r = select i1 %cond, double %z, double 42.0
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ret double %r
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}
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define double @fsel_nonzero_true_val(double %x, double %y, double %z) {
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; SSE-LABEL: fsel_nonzero_true_val:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpeqsd %xmm1, %xmm0
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; SSE-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
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; SSE-NEXT: andpd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm2, %xmm0
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; SSE-NEXT: orpd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: fsel_nonzero_true_val:
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; AVX: # %bb.0:
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; AVX-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
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; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%cond = fcmp oeq double %x, %y
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%r = select i1 %cond, double 42.0, double %z
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ret double %r
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}
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define double @fsel_nonzero_constants(double %x, double %y) {
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; SSE-LABEL: fsel_nonzero_constants:
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; SSE: # %bb.0:
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; SSE-NEXT: cmpeqsd %xmm1, %xmm0
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; SSE-NEXT: movq %xmm0, %rax
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; SSE-NEXT: andl $1, %eax
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; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
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; SSE-NEXT: retq
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;
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; AVX-LABEL: fsel_nonzero_constants:
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; AVX: # %bb.0:
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; AVX-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
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; AVX-NEXT: vmovsd {{.*#+}} xmm2 = mem[0],zero
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; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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%cond = fcmp oeq double %x, %y
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%r = select i1 %cond, double 12.0, double 42.0
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ret double %r
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}
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define <2 x double> @vsel_nonzero_constants(<2 x double> %x, <2 x double> %y) {
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; SSE2-LABEL: vsel_nonzero_constants:
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; SSE2: # %bb.0:
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; SSE2-NEXT: cmplepd %xmm0, %xmm1
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; SSE2-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
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; SSE2-NEXT: movapd %xmm1, %xmm0
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; SSE2-NEXT: andnpd %xmm2, %xmm0
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; SSE2-NEXT: andpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
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; SSE2-NEXT: orpd %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE42-LABEL: vsel_nonzero_constants:
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; SSE42: # %bb.0:
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; SSE42-NEXT: cmplepd %xmm0, %xmm1
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; SSE42-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
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; SSE42-NEXT: movapd %xmm1, %xmm0
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; SSE42-NEXT: blendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
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; SSE42-NEXT: movapd %xmm2, %xmm0
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; SSE42-NEXT: retq
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;
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; AVX-LABEL: vsel_nonzero_constants:
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; AVX: # %bb.0:
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; AVX-NEXT: vcmplepd %xmm0, %xmm1, %xmm0
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; AVX-NEXT: vmovsd {{.*#+}} xmm1 = mem[0],zero
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; AVX-NEXT: vblendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
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; AVX-NEXT: retq
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%cond = fcmp oge <2 x double> %x, %y
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%r = select <2 x i1> %cond, <2 x double> <double 12.0, double -1.0>, <2 x double> <double 42.0, double 0.0>
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ret <2 x double> %r
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}
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