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clang-p2996/llvm/test/CodeGen/X86
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Sanjay Patel 40163f1df8 [x86] add special-case lowering for usubsat for AVX512 
This is a small extension of D112095 to avoid another regression
seen with D112085.
In this case, we allow the same conversion from usubsat to ALU
ops if the target supports vpternlog.

That pattern will get converted later in X86DAGToDAGISel::tryVPTERNLOG().
This seems better than putting a magic immediate constant directly in
this code to create the exact vpternlog that we need. It's possible that
there are other special-cases along these lines, so we should try to
keep all of the vpternlog magic in one place.

Differential Revision: https://reviews.llvm.org/D112138
2021-10-20 16:41:13 -04:00
..
AMX
[X86] [AMX] Replace bitcast with specific AMX intrinsics with X86 specific cast.
2021-08-17 17:04:26 +08:00
avx512-shuffles
Revert "[X86] combineX86ShuffleChain(): canonicalize mask elts picking from splats"
2021-08-05 18:58:08 +02:00
GC
…
GlobalISel
Delay outgoing register assignments to last.
2021-10-04 12:33:20 -07:00
Inputs
[SampleFDO] Flow Sensitive Sample FDO (FSAFDO) profile loader
2021-08-18 18:37:35 -07:00
3addr-16bit.ll
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3addr-or.ll
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3dnow-intrinsics.ll
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4char-promote.ll
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8bit_cmov_of_trunc_promotion.ll
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64-bit-shift-by-32-minus-y.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
2003-08-03-CallArgLiveRanges.ll
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2003-08-23-DeadBlockTest.ll
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2003-11-03-GlobalBool.ll
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2004-02-13-FrameReturnAddress.ll
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2004-02-14-InefficientStackPointer.ll
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2004-02-22-Casts.ll
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2004-03-30-Select-Max.ll
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2004-04-13-FPCMOV-Crash.ll
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2004-06-10-StackifierCrash.ll
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2004-10-08-SelectSetCCFold.ll
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2005-01-17-CycleInDAG.ll
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2005-02-14-IllegalAssembler.ll
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2005-05-08-FPStackifierPHI.ll
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2006-01-19-ISelFoldingBug.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2006-03-01-InstrSchedBug.ll
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2006-03-02-InstrSchedBug.ll
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2006-04-04-CrossBlockCrash.ll
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2006-04-27-ISelFoldingBug.ll
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2006-05-01-SchedCausingSpills.ll
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2006-05-02-InstrSched1.ll
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2006-05-02-InstrSched2.ll
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2006-05-08-CoalesceSubRegClass.ll
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2006-05-08-InstrSched.ll
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2006-05-11-InstrSched.ll
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2006-05-17-VectorArg.ll
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2006-05-22-FPSetEQ.ll
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2006-05-25-CycleInDAG.ll
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2006-07-10-InlineAsmAConstraint.ll
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2006-07-12-InlineAsmQConstraint.ll
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2006-07-20-InlineAsm.ll
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2006-07-28-AsmPrint-Long-As-Pointer.ll
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2006-07-31-SingleRegClass.ll
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2006-08-07-CycleInDAG.ll
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2006-08-16-CycleInDAG.ll
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2006-08-21-ExtraMovInst.ll
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2006-09-01-CycleInDAG.ll
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2006-10-02-BoolRetCrash.ll
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2006-10-09-CycleInDAG.ll
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2006-10-10-FindModifiedNodeSlotBug.ll
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2006-10-12-CycleInDAG.ll
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2006-10-13-CycleInDAG.ll
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2006-10-19-SwitchUnnecessaryBranching.ll
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2006-11-12-CSRetCC.ll
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2006-11-17-IllegalMove.ll
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2006-11-27-SelectLegalize.ll
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2006-12-16-InlineAsmCrash.ll
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2006-12-19-IntelSyntax.ll
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2007-01-08-InstrSched.ll
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2007-01-08-X86-64-Pointer.ll
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2007-01-13-StackPtrIndex.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2007-01-29-InlineAsm-ir.ll
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2007-02-04-OrAddrMode.ll
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2007-02-16-BranchFold.ll
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2007-02-19-LiveIntervalAssert.ll
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2007-02-23-DAGCombine-Miscompile.ll
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2007-02-25-FastCCStack.ll
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2007-03-01-SpillerCrash.ll
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2007-03-15-GEP-Idx-Sink.ll
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2007-03-16-InlineAsm.ll
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2007-03-18-LiveIntervalAssert.ll
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2007-03-24-InlineAsmMultiRegConstraint.ll
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2007-03-24-InlineAsmPModifier.ll
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2007-03-24-InlineAsmVectorOp.ll
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2007-03-24-InlineAsmXConstraint.ll
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2007-03-26-CoalescerBug.ll
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2007-04-08-InlineAsmCrash.ll
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2007-04-11-InlineAsmVectorResult.ll
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2007-04-17-LiveIntervalAssert.ll
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2007-04-24-Huge-Stack.ll
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2007-04-24-VectorCrash.ll
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2007-04-27-InlineAsm-IntMemInput.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2007-05-05-Personality.ll
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2007-05-05-VecCastExpand.ll
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2007-05-14-LiveIntervalAssert.ll
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2007-05-15-maskmovq.ll
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2007-05-17-ShuffleISelBug.ll
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2007-06-04-X86-64-CtorAsmBugs.ll
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2007-06-28-X86-64-isel.ll
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2007-06-29-DAGCombinerBug.ll
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2007-06-29-VecFPConstantCSEBug.ll
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2007-07-03-GR64ToVR64.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2007-07-10-StackerAssert.ll
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2007-07-18-Vector-Extract.ll
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2007-08-01-LiveVariablesBug.ll
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2007-08-09-IllegalX86-64Asm.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2007-08-10-SignExtSubreg.ll
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2007-09-05-InvalidAsm.ll
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2007-09-06-ExtWeakAliasee.ll
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2007-09-27-LDIntrinsics.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
2007-10-04-AvoidEFLAGSCopy.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2007-10-12-CoalesceExtSubReg.ll
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2007-10-12-SpillerUnfold1.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
2007-10-12-SpillerUnfold2.ll
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2007-10-14-CoalescerCrash.ll
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2007-10-15-CoalescerCrash.ll
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2007-10-16-CoalescerCrash.ll
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2007-10-19-SpillerUnfold.ll
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2007-10-28-inlineasm-q-modifier.ll
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2007-10-29-ExtendSetCC.ll
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2007-10-30-LSRCrash.ll
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2007-10-31-extractelement-i64.ll
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2007-11-01-ISelCrash.ll
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2007-11-03-x86-64-q-constraint.ll
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2007-11-04-LiveIntervalCrash.ll
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2007-11-04-LiveVariablesBug.ll
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2007-11-04-rip-immediate-constant.ll
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2007-11-06-InstrSched.ll
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2007-11-07-MulBy4.ll
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2007-11-30-LoadFolding-Bug.ll
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2007-12-16-BURRSchedCrash.ll
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2007-12-18-LoadCSEBug.ll
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2008-01-08-IllegalCMP.ll
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2008-01-08-SchedulerCrash.ll
…
2008-01-09-LongDoubleSin.ll
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2008-01-16-FPStackifierAssert.ll
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2008-01-16-InvalidDAGCombineXform.ll
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2008-02-05-ISelCrash.ll
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2008-02-06-LoadFoldingBug.ll
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2008-02-14-BitMiscompile.ll
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2008-02-18-TailMergingBug.ll
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2008-02-20-InlineAsmClobber.ll
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2008-02-22-LocalRegAllocBug.ll
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2008-02-25-InlineAsmBug.ll
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2008-02-25-X86-64-CoalescerBug.ll
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2008-02-26-AsmDirectMemOp.ll
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2008-02-27-DeadSlotElimBug.ll
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2008-02-27-PEICrash.ll
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2008-03-06-frem-fpstack.ll
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2008-03-07-APIntBug.ll
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2008-03-10-RegAllocInfLoop.ll
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2008-03-12-ThreadLocalAlias.ll
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2008-03-13-TwoAddrPassCrash.ll
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2008-03-14-SpillerCrash.ll
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2008-03-19-DAGCombinerBug.ll
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2008-03-23-DarwinAsmComments.ll
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2008-03-25-TwoAddrPassBug.ll
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2008-03-31-SpillerFoldingBug.ll
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2008-04-02-unnamedEH.ll
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2008-04-08-CoalescerCrash.ll
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2008-04-09-BranchFolding.ll
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2008-04-15-LiveVariableBug.ll
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2008-04-16-CoalescerBug.ll
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2008-04-16-ReMatBug.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
2008-04-17-CoalescerBug.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2008-04-24-MemCpyBug.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2008-04-24-pblendw-fold-crash.ll
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2008-04-26-Asm-Optimize-Imm.ll
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2008-04-28-CoalescerBug.ll
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2008-04-28-CyclicSchedUnit.ll
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2008-05-01-InvalidOrdCompare.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2008-05-09-PHIElimBug.ll
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2008-05-09-ShuffleLoweringBug.ll
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2008-05-12-tailmerge-5.ll
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2008-05-21-CoalescerBug.ll
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2008-05-22-FoldUnalignedLoad.ll
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2008-05-28-CoalescerBug.ll
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2008-05-28-LocalRegAllocBug.ll
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2008-06-13-NotVolatileLoadStore.ll
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2008-06-13-VolatileLoadStore.ll
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2008-06-16-SubregsBug.ll
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2008-06-25-VecISelBug.ll
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2008-07-07-DanglingDeadInsts.ll
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2008-07-09-ELFSectionAttributes.ll
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2008-07-11-SHLBy1.ll
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2008-07-16-CoalescerCrash.ll
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2008-07-19-movups-spills.ll
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2008-07-22-CombinerCrash.ll
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2008-07-23-VSetCC.ll
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2008-08-06-CmpStride.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2008-08-06-RewriterBug.ll
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2008-08-17-UComiCodeGenBug.ll
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2008-08-23-64Bit-maskmovq.ll
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2008-08-31-EH_RETURN32.ll
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2008-08-31-EH_RETURN64.ll
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2008-09-05-sinttofp-2xi32.ll
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2008-09-09-LinearScanBug.ll
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2008-09-11-CoalescerBug2.ll
[X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760)
2021-06-30 18:46:50 +01:00
2008-09-11-CoalescerBug.ll
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2008-09-17-inline-asm-1.ll
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2008-09-18-inline-asm-2.ll
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2008-09-19-RegAllocBug.ll
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2008-09-25-sseregparm-1.ll
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2008-09-26-FrameAddrBug.ll
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2008-09-29-ReMatBug.ll
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2008-09-29-VolatileBug.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2008-10-06-x87ld-nan-1.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2008-10-06-x87ld-nan-2.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2008-10-07-SSEISelBug.ll
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2008-10-11-CallCrash.ll
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2008-10-13-CoalescerBug.ll
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2008-10-16-VecUnaryOp.ll
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2008-10-17-Asm64bitRConstraint.ll
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2008-10-20-AsmDoubleInI32.ll
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2008-10-24-FlippedCompare.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2008-10-27-CoalescerBug.ll
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2008-10-29-ExpandVAARG.ll
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2008-11-03-F80VAARG.ll
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2008-11-06-testb.ll
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2008-11-13-inlineasm-3.ll
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2008-11-29-ULT-Sign.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2008-12-01-loop-iv-used-outside-loop.ll
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2008-12-01-SpillerAssert.ll
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2008-12-02-dagcombine-1.ll
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2008-12-02-dagcombine-2.ll
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2008-12-02-dagcombine-3.ll
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2008-12-02-IllegalResultType.ll
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2008-12-16-dagcombine-4.ll
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2008-12-19-EarlyClobberBug.ll
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2008-12-22-dagcombine-5.ll
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2008-12-23-crazy-address.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2008-12-23-dagcombine-6.ll
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2009-01-13-DoubleUpdate.ll
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2009-01-16-SchedulerBug.ll
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2009-01-16-UIntToFP.ll
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2009-01-18-ConstantExprCrash.ll
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2009-01-25-NoSSE.ll
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2009-01-26-WrongCheck.ll
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2009-01-27-NullStrings.ll
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2009-01-31-BigShift2.ll
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2009-01-31-BigShift3.ll
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2009-01-31-BigShift.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2009-02-01-LargeMask.ll
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2009-02-03-AnalyzedTwice.ll
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2009-02-04-sext-i64-gep.ll
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2009-02-08-CoalescerBug.ll
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2009-02-09-ivs-different-sizes.ll
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2009-02-11-codegenprepare-reuse.ll
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2009-02-12-DebugInfoVLA.ll
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2009-02-12-InlineAsm-nieZ-constraints.ll
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2009-02-12-SpillerBug.ll
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2009-02-21-ExtWeakInitializer.ll
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2009-02-25-CommuteBug.ll
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2009-02-26-MachineLICMBug.ll
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2009-03-03-BitcastLongDouble.ll
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2009-03-03-BTHang.ll
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2009-03-05-burr-list-crash.ll
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2009-03-09-APIntCrash.ll
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2009-03-09-SpillerBug.ll
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2009-03-10-CoalescerBug.ll
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2009-03-12-CPAlignBug.ll
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2009-03-13-PHIElimBug.ll
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2009-03-16-PHIElimInLPad.ll
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2009-03-23-LinearScanBug.ll
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2009-03-23-MultiUseSched.ll
[X86FixupLEAs] Try again to transform the sequence LEA/SUB to SUB/SUB
2021-07-16 10:16:03 -07:00
2009-03-25-TestBug.ll
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2009-03-26-NoImplicitFPBug.ll
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2009-04-12-FastIselOverflowCrash.ll
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2009-04-12-picrel.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2009-04-13-2AddrAssert-2.ll
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2009-04-13-2AddrAssert.ll
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2009-04-14-IllegalRegs.ll
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2009-04-16-SpillerUnfold.ll
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2009-04-24.ll
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2009-04-25-CoalescerBug.ll
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2009-04-27-CoalescerAssert.ll
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2009-04-27-LiveIntervalsAssert2.ll
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2009-04-27-LiveIntervalsAssert.ll
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2009-04-29-IndirectDestOperands.ll
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2009-04-29-LinearScanBug.ll
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2009-04-29-RegAllocAssert.ll
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2009-04-scale.ll
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2009-05-08-InlineAsmIOffset.ll
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2009-05-11-tailmerge-crash.ll
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2009-05-19-SingleElementExtractElement.ll
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2009-05-23-available_externally.ll
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2009-05-23-dagcombine-shifts.ll
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2009-05-28-DAGCombineCrash.ll
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2009-05-30-ISelBug.ll
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2009-06-02-RewriterBug.ll
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2009-06-03-Win64DisableRedZone.ll
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2009-06-03-Win64SpillXMM.ll
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2009-06-04-VirtualLiveIn.ll
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2009-06-05-sitofpCrash.ll
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2009-06-05-VariableIndexInsert.ll
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2009-06-05-VZextByteShort.ll
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2009-06-06-ConcatVectors.ll
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2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll
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2009-06-15-not-a-tail-call.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2009-06-18-movlp-shuffle-register.ll
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2009-07-06-TwoAddrAssert.ll
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2009-07-07-SplitICmp.ll
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2009-07-09-ExtractBoolFromVector.ll
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2009-07-15-CoalescerBug.ll
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2009-07-16-CoalescerBug.ll
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2009-07-19-AsmExtraOperands.ll
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2009-07-20-CoalescerBug.ll
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2009-07-20-DAGCombineBug.ll
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2009-08-06-branchfolder-crash.ll
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2009-08-06-inlineasm.ll
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2009-08-08-CastError.ll
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2009-08-12-badswitch.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2009-08-14-Win64MemoryIndirectArg.ll
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2009-08-19-LoadNarrowingMiscompile.ll
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2009-08-23-SubRegReuseUndo.ll
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2009-09-10-LoadFoldingBug.ll
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2009-09-10-SpillComments.ll
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2009-09-16-CoalescerBug.ll
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2009-09-19-earlyclobber.ll
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2009-09-21-NoSpillLoopCount.ll
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2009-09-22-CoalescerBug.ll
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2009-09-23-LiveVariablesBug.ll
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2009-10-14-LiveVariablesBug.ll
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2009-10-16-Scope.ll
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2009-10-19-atomic-cmp-eflags.ll
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2009-10-19-EmergencySpill.ll
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2009-10-25-RewriterBug.ll
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2009-11-04-SubregCoalescingBug.ll
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2009-11-13-VirtRegRewriterBug.ll
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2009-11-16-MachineLICM.ll
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2009-11-16-UnfoldMemOpBug.ll
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2009-11-17-UpdateTerminator.ll
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2009-11-18-TwoAddrKill.ll
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2009-11-25-ImpDefBug.ll
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2009-12-01-EarlyClobberBug.ll
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2009-12-11-TLSNoRedZone.ll
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2010-01-05-ZExt-Shl.ll
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2010-01-07-ISelBug.ll
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2010-01-08-Atomic64Bug.ll
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2010-01-11-ExtraPHIArg.ll
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2010-01-13-OptExtBug.ll
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2010-01-15-SelectionDAGCycle.ll
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2010-01-18-DbgValue.ll
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2010-01-19-OptExtBug.ll
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2010-02-01-DbgValueCrash.ll
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2010-02-01-TaillCallCrash.ll
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2010-02-03-DualUndef.ll
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2010-02-04-SchedulerBug.ll
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2010-02-11-NonTemporal.ll
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2010-02-12-CoalescerBug-Impdef.ll
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2010-02-15-ImplicitDefBug.ll
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2010-02-19-TailCallRetAddrBug.ll
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2010-02-23-DAGCombineBug.ll
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2010-02-23-DIV8rDefinesAX.ll
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2010-02-23-RematImplicitSubreg.ll
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2010-02-23-SingleDefPhiJoin.ll
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2010-03-04-Mul8Bug.ll
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2010-03-05-ConstantFoldCFG.ll
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2010-03-05-EFLAGS-Redef.ll
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2010-03-17-ISelBug.ll
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2010-04-06-SSEDomainFixCrash.ll
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2010-04-08-CoalescerBug.ll
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2010-04-13-AnalyzeBranchCrash.ll
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2010-04-21-CoalescerBug.ll
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2010-04-29-CoalescerCrash.ll
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2010-04-30-LocalAlloc-LandingPad.ll
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2010-05-03-CoalescerSubRegClobber.ll
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2010-05-05-LocalAllocEarlyClobber.ll
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2010-05-06-LocalInlineAsmClobber.ll
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2010-05-07-ldconvert.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
2010-05-10-DAGCombinerBug.ll
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2010-05-12-FastAllocKills.ll
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2010-05-16-nosseconversion.ll
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2010-05-25-DotDebugLoc.ll
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2010-05-26-DotDebugLoc.ll
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2010-05-26-FP_TO_INT-crash.ll
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2010-05-28-Crash.ll
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2010-06-01-DeadArg-DbgInfo.ll
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2010-06-09-FastAllocRegisters.ll
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2010-06-14-fast-isel-fs-load.ll
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2010-06-15-FastAllocEarlyCLobber.ll
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2010-06-24-g-constraint-crash.ll
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2010-06-25-asm-RA-crash.ll
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2010-06-25-CoalescerSubRegDefDead.ll
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2010-06-28-FastAllocTiedOperand.ll
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2010-06-28-matched-g-constraint.ll
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2010-07-02-asm-alignstack.ll
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2010-07-02-UnfoldBug.ll
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2010-07-06-asm-RIP.ll
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2010-07-06-DbgCrash.ll
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2010-07-11-FPStackLoneUse.ll
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2010-07-13-indirectXconstraint.ll
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2010-07-15-Crash.ll
…
2010-07-29-SetccSimplify.ll
…
2010-08-04-MaskedSignedCompare.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2010-08-04-MingWCrash.ll
…
2010-08-04-StackVariable.ll
…
2010-09-01-RemoveCopyByCommutingDef.ll
…
2010-09-16-asmcrash.ll
…
2010-09-16-EmptyFilename.ll
…
2010-09-17-SideEffectsInChain.ll
…
2010-09-30-CMOV-JumpTable-PHI.ll
…
2010-10-08-cmpxchg8b.ll
…
2010-11-02-DbgParameter.ll
…
2010-11-09-MOVLPS.ll
…
2010-11-18-SelectOfExtload.ll
…
2011-01-07-LegalizeTypesCrash.ll
…
2011-01-10-DagCombineHang.ll
…
2011-01-24-DbgValue-Before-Use.ll
…
2011-02-04-FastRegallocNoFP.ll
…
2011-02-12-shuffle.ll
…
2011-02-21-VirtRegRewriter-KillSubReg.ll
…
2011-02-23-UnfoldBug.ll
…
2011-02-27-Fpextend.ll
…
2011-03-02-DAGCombiner.ll
…
2011-03-08-Sched-crash.ll
…
2011-03-09-Physreg-Coalescing.ll
…
2011-03-30-CreateFixedObjCrash.ll
…
2011-04-13-SchedCmpJmp.ll
…
2011-04-19-sclr-bb.ll
…
2011-05-09-loaduse.ll
…
2011-05-26-UnreachableBlockElim.ll
…
2011-05-27-CrossClassCoalescing.ll
…
2011-06-01-fildll.ll
…
2011-06-03-x87chain.ll
…
2011-06-06-fgetsign80bit.ll
…
2011-06-12-FastAllocSpill.ll
…
2011-06-14-mmx-inlineasm.ll
…
2011-06-14-PreschedRegalias.ll
…
2011-06-19-QuicksortCoalescerBug.ll
…
2011-07-13-BadFrameIndexDisplacement.ll
…
2011-08-23-PerformSubCombine128.ll
…
2011-08-23-Trampoline.ll
…
2011-08-29-BlockConstant.ll
…
2011-08-29-InitOrder.ll
[static initializers] Emit global_ctors and global_dtors in reverse order when .ctors/.dtors are used.
2021-06-10 16:44:47 -07:00
2011-09-14-valcoalesce.ll
…
2011-09-18-sse2cmp.ll
…
2011-09-21-setcc-bug.ll
…
2011-10-11-SpillDead.ll
…
2011-10-11-srl.ll
…
2011-10-12-MachineCSE.ll
…
2011-10-18-FastISel-VectorParams.ll
…
2011-10-19-LegelizeLoad.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
2011-10-19-widen_vselect.ll
…
2011-10-21-widen-cmp.ll
…
2011-10-27-tstore.ll
…
2011-10-30-padd.ll
…
2011-11-07-LegalizeBuildVector.ll
…
2011-11-22-AVX2-Domains.ll
…
2011-11-30-or.ll
…
2011-12-8-bitcastintprom.ll
…
2011-12-06-AVXVectorExtractCombine.ll
…
2011-12-06-BitcastVectorGlobal.ll
…
2011-12-08-AVXISelBugs.ll
…
2011-12-15-vec_shift.ll
…
2011-12-26-extractelement-duplicate-load.ll
…
2011-12-28-vselecti8.ll
…
2011-20-21-zext-ui2fp.ll
…
2012-1-10-buildvector.ll
…
2012-01-10-UndefExceptionEdge.ll
…
2012-01-11-split-cv.ll
…
2012-01-12-extract-sv.ll
…
2012-01-16-mfence-nosse-flags.ll
…
2012-01-18-vbitcast.ll
…
2012-02-12-dagco.ll
…
2012-02-14-scalar.ll
…
2012-02-23-mmx-inlineasm.ll
…
2012-02-29-CoalescerBug.ll
…
2012-03-15-build_vector_wl.ll
…
2012-03-20-LargeConstantExpr.ll
…
2012-03-26-PostRALICMBug.ll
…
2012-04-09-TwoAddrPassBug.ll
…
2012-04-26-sdglue.ll
[DAG] DAGCombiner::visitVECTOR_SHUFFLE - recognise INSERT_SUBVECTOR patterns
2021-08-05 15:40:48 +01:00
2012-05-17-TwoAddressBug.ll
…
2012-05-19-CoalescerCrash.ll
…
2012-07-10-extload64.ll
…
2012-07-10-shufnorm.ll
…
2012-07-15-broadcastfold.ll
…
2012-07-15-BuildVectorPromote.ll
…
2012-07-15-tconst_shl.ll
…
2012-07-15-vshl.ll
…
2012-07-16-fp2ui-i1.ll
…
2012-07-16-LeaUndef.ll
…
2012-07-17-vtrunc.ll
…
2012-07-23-select_cc.ll
…
2012-08-07-CmpISelBug.ll
…
2012-08-16-setcc.ll
…
2012-08-17-legalizer-crash.ll
…
2012-08-28-UnsafeMathCrash.ll
…
2012-09-13-dagco-fneg.ll
…
2012-09-28-CGPBug.ll
…
2012-10-02-DAGCycle.ll
…
2012-10-03-DAGCycle.ll
…
2012-10-18-crash-dagco.ll
…
2012-11-28-merge-store-alias.ll
…
2012-12-1-merge-multiple.ll
…
2012-12-12-DAGCombineCrash.ll
…
2012-12-14-v8fp80-crash.ll
…
2012-12-19-NoImplicitFloat.ll
…
2013-01-09-DAGCombineBug.ll
…
2013-03-13-VEX-DestReg.ll
…
2013-05-06-ConactVectorCrash.ll
…
2013-10-14-FastISel-incorrect-vreg.ll
…
2014-05-29-factorial.ll
…
2014-08-29-CompactUnwind.ll
…
2020_12_02_decrementing_loop.ll
…
9601.ll
…
20090313-signext.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
20210831-inlineasm.ll
[SelectionDAGBuilder] Bugfix in visitInlineAsm()
2021-09-06 17:46:31 +02:00
abi-isel.ll
…
abs.ll
[X86] Use CMOVNS for abs instead of CMOVGE.
2021-10-14 12:28:28 -07:00
absolute-bit-mask-fastisel.ll
…
absolute-bit-mask.ll
…
absolute-bt.ll
…
absolute-cmp.ll
[TargetMachine] Don't imply dso_local on function declarations in Reloc::Static model for ELF/wasm
2020-12-05 14:54:37 -08:00
absolute-constant.ll
…
absolute-rotate.ll
…
add32ri8.ll
…
add_shl_constant.ll
…
add-cmov.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
add-ext.ll
…
add-i64.ll
…
add-of-carry.ll
…
add-sub-nsw-nuw.ll
…
add.ll
…
addcarry2.ll
…
addcarry.ll
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
addr-label-difference.ll
…
addr-mode-matcher-2.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
addr-mode-matcher.ll
…
addr-of-ret-addr.ll
…
address-type-promotion-constantexpr.ll
…
addrsig.ll
…
addsub-constant-folding.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
adx-commute.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
adx-intrinsics-upgrade.ll
…
adx-intrinsics.ll
…
aes_intrinsics.ll
…
alias-gep.ll
…
alias-static-alloca.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
aliases.ll
…
align-branch-boundary-default.ll
…
align-branch-boundary-noautopadding.ll
…
align-branch-boundary-suppressions-tls.ll
…
align-branch-boundary-suppressions.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
align-down-const.ll
…
align-down.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
aligned-comm.ll
…
aligned-variadic.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
alignment-2.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
alignment.ll
…
all-ones-vector.ll
…
alldiv-divdi3.ll
…
alloca-align-rounding-32.ll
…
alloca-align-rounding.ll
…
alloca-overaligned.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
allrem-moddi3.ll
…
and-encoding.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
and-load-fold.ll
…
and-or-fold.ll
…
and-sink.ll
…
and-su.ll
…
and-with-overflow.ll
…
andimm8.ll
…
anyext.ll
…
anyregcc-crash.ll
…
anyregcc.ll
…
apm.ll
…
AppendingLinkage.ll
…
arg_returned_bitcast.ll
…
arg-cast.ll
…
arg-copy-elide-win64.ll
…
arg-copy-elide.ll
…
arithmetic_fence2.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
arithmetic_fence.ll
[ISel] Legalized arithmetic.fence.f128 for 32-bits target
2021-09-28 10:27:25 +08:00
asan-check-memaccess-add.ll
[asan] Fixed a bug causing a crash when redzone optimization kicked in on X86 with -asan-optimize-callbacks flag on.
2021-09-21 22:26:03 +00:00
asan-check-memaccess-or.ll
[asan] Fixed a bug causing a crash when redzone optimization kicked in on X86 with -asan-optimize-callbacks flag on.
2021-09-21 22:26:03 +00:00
asm-block-labels.ll
…
asm-global-imm.ll
…
asm-indirect-mem.ll
…
asm-invalid-register-class-crasher.ll
…
asm-label2.ll
…
asm-label.ll
…
asm-mismatched-types.ll
…
asm-modifier2.ll
…
asm-modifier-P.ll
…
asm-modifier.ll
…
asm-reg-type-mismatch-avx512.ll
…
asm-reg-type-mismatch.ll
…
asm-reject-reg-type-mismatch.ll
…
asm-reject-rex.ll
…
asm-reject-vk32-vk64.ll
…
asm-reject-x87-int.ll
…
asm-reject-xmm16.ll
…
atom-call-reg-indirect-foldedreload32.ll
…
atom-call-reg-indirect-foldedreload64.ll
…
atom-call-reg-indirect.ll
…
atom-cmpb.ll
…
atom-fixup-lea1.ll
…
atom-fixup-lea2.ll
…
atom-fixup-lea3.ll
…
atom-fixup-lea4.ll
…
atom-lea-addw-bug.ll
…
atom-lea-sp.ll
…
atom-pad-short-functions.ll
…
atom-sched.ll
…
atom-shuf.ll
…
atomic8.ll
…
atomic16.ll
…
atomic32.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
atomic64.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
atomic128.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
atomic6432.ll
…
atomic-add.ll
…
atomic-dagsched.ll
…
atomic-eflags-reuse.ll
[X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760)
2021-06-30 18:46:50 +01:00
atomic-flags.ll
…
atomic-fp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
atomic-idempotent.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
atomic-load-store-wide.ll
…
atomic-load-store.ll
…
atomic-mi.ll
…
atomic-minmax-i6432.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
atomic-monotonic.ll
…
atomic-non-integer-fp128.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
atomic-non-integer.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
atomic-op.ll
…
atomic-ops-ancient-64.ll
…
atomic-or.ll
…
atomic-pointer.ll
IR: Support parsing numeric block ids, and emit them in textual output.
2019-03-22 18:27:13 +00:00
atomic-unordered.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
atomicf128.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
Atomics-64.ll
…
attr-dontcall.ll
Reland [clang] Rework dontcall attributes
2021-09-28 15:31:30 -07:00
attribute-sections.ll
…
avg-mask.ll
…
avg.ll
[X86][SSE] Add X86ISD::AVG to isCommutativeBinOp to support folding shuffles through the binop
2021-10-13 10:54:37 +01:00
avoid_complex_am.ll
…
avoid-lea-scale2.ll
test/CodeGen/X86: FileCheck-ize and add actions for x86_64-linux and x86_64-win32.
2011-03-16 13:53:07 +00:00
avoid-loop-align-2.ll
[test] Add explicit dso_local to constant/global variable declarations
2020-12-04 13:51:01 -08:00
avoid-loop-align.ll
[MC] Use .p2align instead of .align
2016-01-26 00:03:25 +00:00
avoid-sfb-g-no-change2.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
avoid-sfb-g-no-change3.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
avoid-sfb-g-no-change.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
avoid-sfb-kill-flags.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
avoid-sfb-offset.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
avoid-sfb-overlaps.ll
…
avoid-sfb.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx1-logical-load-folding.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx2-arith.ll
…
avx2-cmp.ll
…
avx2-conversions.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
avx2-fma-fneg-combine.ll
…
avx2-gather.ll
…
avx2-intrinsics-canonical.ll
…
avx2-intrinsics-fast-isel.ll
…
avx2-intrinsics-x86-upgrade.ll
…
avx2-intrinsics-x86.ll
[X86] Remove Commutable flag from mpsadbw intrinsics.
2021-09-19 13:22:22 -07:00
avx2-logic.ll
…
avx2-masked-gather.ll
[X86] Lower insertions into upper half of an 256-bit vector as broadcast+blend (PR50971)
2021-08-17 18:45:10 +03:00
avx2-nontemporal.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx2-phaddsub.ll
…
avx2-pmovxrm.ll
…
avx2-shift.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx2-vbroadcast.ll
[X86] Exclude invalid element types for bitcast/broadcast folding.
2021-06-24 12:39:01 +01:00
avx2-vbroadcasti128.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx2-vector-shifts.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
avx2-vperm.ll
…
avx512-adc-sbb.ll
…
avx512-any_extend_load.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-arith.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-broadcast-unfold.ll
…
avx512-bugfix-23634.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-bugfix-25270.ll
[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
2021-06-11 16:49:12 +01:00
avx512-bugfix-26264.ll
…
avx512-build-vector.ll
…
avx512-calling-conv.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
avx512-cmp-kor-sequence.ll
…
avx512-cmp-mask.ll
…
avx512-cmp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-cvt.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-cvttp2i.ll
…
avx512-ext.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-extract-subvector-load-store.ll
Fix the default alignment of i1 vectors.
2021-07-31 14:09:59 -07:00
avx512-extract-subvector.ll
…
avx512-fma-commute.ll
…
avx512-fma-intrinsics-upgrade.ll
…
avx512-fma-intrinsics.ll
…
avx512-fma.ll
…
avx512-fsel.ll
…
avx512-gather-scatter-intrin-deprecated.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-gather-scatter-intrin.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-gfni-intrinsics.ll
…
avx512-hadd-hsub.ll
…
avx512-i1test.ll
…
avx512-inc-dec.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
avx512-insert-extract_i1.ll
…
avx512-insert-extract.ll
[X86] Lower insertions into upper half of an 256-bit vector as broadcast+blend (PR50971)
2021-08-17 18:45:10 +03:00
avx512-intel-ocl.ll
…
avx512-intrinsics-canonical.ll
…
avx512-intrinsics-fast-isel.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-intrinsics-upgrade.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-intrinsics-x86_64.ll
…
avx512-intrinsics.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-load-store.ll
…
avx512-load-trunc-store-i1.ll
…
avx512-logic.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-mask-op.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
avx512-mask-spills.ll
…
avx512-mask-zext-bugfix.ll
…
avx512-masked_memop-16-8.ll
…
avx512-masked-memop-64-32.ll
[X86] Lower insertions into upper half of an 256-bit vector as broadcast+blend (PR50971)
2021-08-17 18:45:10 +03:00
avx512-memfold.ll
…
avx512-mov.ll
…
avx512-movmsk.ll
…
avx512-nontemporal.ll
…
avx512-pmovxrm.ll
…
avx512-regcall-Mask.ll
…
avx512-regcall-NoMask.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
avx512-rndscale.ll
…
avx512-rotate.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-scalar_mask.ll
…
avx512-scalar.ll
…
avx512-scalarIntrinsics.ll
…
avx512-select.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
avx512-shift.ll
…
avx512-skx-insert-subvec.ll
…
avx512-trunc.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-unsafe-fp-math.ll
…
avx512-vbroadcast.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-vbroadcasti128.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-vbroadcasti256.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-vec3-crash.ll
…
avx512-vec-cmp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512-vpclmulqdq.ll
…
avx512-vpermv3-commute.ll
…
avx512-vpternlog-commute.ll
…
avx512-vselect-crash.ll
…
avx512-vselect.ll
…
avx512bf16-intrinsics.ll
…
avx512bf16-vl-intrinsics.ll
…
avx512bw-arith.ll
…
avx512bw-intrinsics-canonical.ll
…
avx512bw-intrinsics-fast-isel.ll
…
avx512bw-intrinsics-upgrade.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
avx512bw-intrinsics.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512bw-mask-op.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
avx512bw-mov.ll
…
avx512bw-vec-cmp.ll
…
avx512bw-vec-test-testn.ll
…
avx512bwvl-arith.ll
…
avx512bwvl-intrinsics-canonical.ll
…
avx512bwvl-intrinsics-fast-isel.ll
…
avx512bwvl-intrinsics-upgrade.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
avx512bwvl-intrinsics.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512bwvl-mov.ll
…
avx512bwvl-vec-cmp.ll
…
avx512bwvl-vec-test-testn.ll
…
avx512cd-intrinsics-fast-isel.ll
…
avx512cd-intrinsics-upgrade.ll
…
avx512cd-intrinsics.ll
…
avx512cdvl-intrinsics-upgrade.ll
…
avx512cdvl-intrinsics.ll
…
avx512cfma-intrinsics.ll
[X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands.
2021-09-23 11:02:48 +08:00
avx512cfmul-intrinsics.ll
[X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands.
2021-09-23 11:02:48 +08:00
avx512cfmulsh-instrinsics.ll
[X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands.
2021-09-23 11:02:48 +08:00
avx512dq-intrinsics-fast-isel.ll
…
avx512dq-intrinsics-upgrade.ll
…
avx512dq-intrinsics.ll
…
avx512dq-mask-op.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
avx512dqvl-intrinsics-fast-isel.ll
…
avx512dqvl-intrinsics-upgrade.ll
…
avx512dqvl-intrinsics.ll
…
avx512er-intrinsics.ll
…
avx512f-256-set0.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
avx512f-vec-test-testn.ll
…
avx512fp16-arith-intrinsics.ll
[X86] AVX512FP16 instructions enabling 3/6
2021-08-18 09:03:41 +08:00
avx512fp16-arith-vl-intrinsics.ll
[X86] Optimize fdiv with reciprocal instructions for half type
2021-10-08 09:41:13 +08:00
avx512fp16-arith.ll
[X86] Optimize fdiv with reciprocal instructions for half type
2021-10-08 09:41:13 +08:00
avx512fp16-combine-vfmac-fadd.ll
[X86][FP16] Fix a bug when Combine the FADD(A, FMA(B, C, 0)) to FMA(B, C, A).
2021-09-28 11:38:53 +08:00
avx512fp16-combine-vfmulc-fadd.ll
[X86][FP16] Fix a bug when Combine the FADD(A, FMA(B, C, 0)) to FMA(B, C, A).
2021-09-28 11:38:53 +08:00
avx512fp16-combine-xor-vfmulc-fadd.ll
[X86][FP16] Fix a bug when Combine the FADD(A, FMA(B, C, 0)) to FMA(B, C, A).
2021-09-28 11:38:53 +08:00
avx512fp16-combine-xor-vfmulc.ll
[X86] AVX512FP16 instructions enabling 6/6
2021-08-30 13:08:45 +08:00
avx512fp16-cvt-ph-w-intrinsics.ll
[X86] AVX512FP16 instructions enabling 3/6
2021-08-18 09:03:41 +08:00
avx512fp16-cvt-ph-w-vl-intrinsics.ll
[X86] AVX512FP16 instructions enabling 3/6
2021-08-18 09:03:41 +08:00
avx512fp16-cvt.ll
[X86] AVX512FP16 instructions enabling 3/6
2021-08-18 09:03:41 +08:00
avx512fp16-fma-commute.ll
[X86] AVX512FP16 instructions enabling 5/6
2021-08-24 09:07:19 +08:00
avx512fp16-fma-intrinsics.ll
[X86] AVX512FP16 instructions enabling 5/6
2021-08-24 09:07:19 +08:00
avx512fp16-fmaxnum.ll
[X86] AVX512FP16 instructions enabling 2/6
2021-08-15 08:56:33 +08:00
avx512fp16-fminnum.ll
[X86] AVX512FP16 instructions enabling 2/6
2021-08-15 08:56:33 +08:00
avx512fp16-fold-load-binops.ll
[X86] AVX512FP16 instructions enabling 2/6
2021-08-15 08:56:33 +08:00
avx512fp16-fold-xmm-zero.ll
[X86] AVX512FP16 instructions enabling 2/6
2021-08-15 08:56:33 +08:00
avx512fp16-fp-logic.ll
[X86] AVX512FP16 instructions enabling 2/6
2021-08-15 08:56:33 +08:00
avx512fp16-insert-extract.ll
[X86] AVX512FP16 instructions enabling 1/6
2021-08-10 12:46:01 +08:00
avx512fp16-intrinsics.ll
[X86] Optimize fdiv with reciprocal instructions for half type
2021-10-08 09:41:13 +08:00
avx512fp16-machine-combiner.ll
[X86] AVX512FP16 instructions enabling 2/6
2021-08-15 08:56:33 +08:00
avx512fp16-mov.ll
[X86] AVX512FP16 instructions enabling 2/6
2021-08-15 08:56:33 +08:00
avx512fp16-mscatter.ll
[X86] AVX512FP16 instructions enabling 1/6
2021-08-10 12:46:01 +08:00
avx512fp16-rndscale.ll
[X86] AVX512FP16 instructions enabling 4/6
2021-08-22 08:59:35 +08:00
avx512fp16-scalar.ll
[X86] AVX512FP16 instructions enabling 4/6
2021-08-22 08:59:35 +08:00
avx512fp16-subv-broadcast-fp16.ll
[X86] AVX512FP16 instructions enabling 1/6
2021-08-10 12:46:01 +08:00
avx512fp16-unsafe-fp-math.ll
[X86] AVX512FP16 instructions enabling 2/6
2021-08-15 08:56:33 +08:00
avx512fp16vl-fma-intrinsics.ll
[X86] AVX512FP16 instructions enabling 5/6
2021-08-24 09:07:19 +08:00
avx512fp16vl-intrinsics.ll
[X86] Optimize fdiv with reciprocal instructions for half type
2021-10-08 09:41:13 +08:00
avx512ifma-intrinsics-fast-isel.ll
…
avx512ifma-intrinsics-upgrade.ll
…
avx512ifma-intrinsics.ll
…
avx512ifmavl-intrinsics-fast-isel.ll
…
avx512ifmavl-intrinsics-upgrade.ll
…
avx512ifmavl-intrinsics.ll
…
avx512vbmi2-funnel-shifts.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512vbmi2-intrinsics-fast-isel.ll
…
avx512vbmi2-intrinsics-upgrade.ll
[DAG] CombineConsecutiveLoads - replace getABITypeAlign with allowsMemoryAccess (PR45116)
2021-08-24 12:31:22 +01:00
avx512vbmi2-intrinsics.ll
[DAG] CombineConsecutiveLoads - replace getABITypeAlign with allowsMemoryAccess (PR45116)
2021-08-24 12:31:22 +01:00
avx512vbmi2vl-funnel-shifts.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512vbmi2vl-intrinsics-fast-isel.ll
…
avx512vbmi2vl-intrinsics-upgrade.ll
…
avx512vbmi2vl-intrinsics.ll
…
avx512vbmi-intrinsics-fast-isel.ll
…
avx512vbmi-intrinsics-upgrade.ll
…
avx512vbmi-intrinsics.ll
…
avx512vbmivl-intrinsics-fast-isel.ll
…
avx512vbmivl-intrinsics-upgrade.ll
…
avx512vbmivl-intrinsics.ll
…
avx512vl_vnni-intrinsics-upgrade.ll
…
avx512vl_vnni-intrinsics.ll
…
avx512vl-arith.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512vl-intrinsics-canonical.ll
…
avx512vl-intrinsics-fast-isel.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512vl-intrinsics-upgrade.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512vl-intrinsics.ll
…
avx512vl-logic.ll
[X86] Handle inverted inputs when matching VPTERNLOG from 2 binary ops.
2021-09-06 17:44:52 -07:00
avx512vl-mov.ll
…
avx512vl-nontemporal.ll
…
avx512vl-vbroadcast.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx512vl-vec-cmp.ll
…
avx512vl-vec-masked-cmp.ll
…
avx512vl-vec-test-testn.ll
…
avx512vl-vpclmulqdq.ll
…
avx512vlcd-intrinsics-fast-isel.ll
…
avx512vlvp2intersect-intrinsics.ll
…
avx512vnni-intrinsics-upgrade.ll
…
avx512vnni-intrinsics.ll
…
avx512vnni.ll
…
avx512vp2intersect-intrinsics.ll
…
avx512vpopcntdq-intrinsics.ll
…
avx_vnni-intrinsics.ll
…
avx-arith.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx-basic.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx-bitcast.ll
…
avx-brcond.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx-cast.ll
…
avx-cmp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx-cvt-2.ll
…
avx-cvt-3.ll
…
avx-cvt.ll
…
avx-cvttp2si.ll
…
avx-fp2int.ll
…
avx-gfni-intrinsics.ll
…
avx-insertelt.ll
[X86] Lower insertions into upper half of an 256-bit vector as broadcast+blend (PR50971)
2021-08-17 18:45:10 +03:00
avx-intel-ocl.ll
…
avx-intrinsics-fast-isel.ll
…
avx-intrinsics-x86_64.ll
[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
2021-06-11 16:49:12 +01:00
avx-intrinsics-x86-upgrade.ll
[DAG] DAGCombiner::visitVECTOR_SHUFFLE - recognise INSERT_SUBVECTOR patterns
2021-08-05 15:40:48 +01:00
avx-intrinsics-x86.ll
…
avx-isa-check.ll
…
avx-load-store.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx-logic.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx-minmax.ll
…
avx-select.ll
…
avx-shift.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx-shuffle-x86_32.ll
…
avx-splat.ll
…
avx-trunc.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
avx-unpack.ll
…
avx-varargs-x86_64.ll
…
avx-vbroadcast.ll
[X86] Exclude invalid element types for bitcast/broadcast folding.
2021-06-24 12:39:01 +01:00
avx-vbroadcastf128.ll
…
avx-vextractf128.ll
…
avx-vinsertf128.ll
…
avx-vpclmulqdq.ll
…
avx-vperm2x128.ll
[DAG] DAGCombiner::visitVECTOR_SHUFFLE - recognise INSERT_SUBVECTOR patterns
2021-08-05 15:40:48 +01:00
avx-vzeroupper.ll
[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
2021-06-11 16:49:12 +01:00
avx-win64-args.ll
…
avx-win64.ll
…
avx.ll
[X86][AVX] matchShuffleAsBlend - use isElementEquivalent to help match broadcast/repeated elements
2021-08-22 15:26:17 +01:00
avxvnni.ll
…
backpropmask.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
bad-tls-fold.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
barrier-sse.ll
…
barrier.ll
…
base-pointer-and-cmpxchg.ll
reland [IR] make -stack-alignment= into a module attr
2021-06-08 10:59:46 -07:00
base-pointer-and-mwaitx.ll
reland [IR] make -stack-alignment= into a module attr
2021-06-08 10:59:46 -07:00
basic-block-sections_2.ll
Append ".__part." to every basic block section symbol.
2020-12-23 11:35:44 -08:00
basic-block-sections-blockaddress-taken.ll
…
basic-block-sections-clusters-branches.ll
Append ".__part." to every basic block section symbol.
2020-12-23 11:35:44 -08:00
basic-block-sections-clusters-eh.ll
Append ".__part." to every basic block section symbol.
2020-12-23 11:35:44 -08:00
basic-block-sections-clusters-error.ll
Rename basic block sections options to be consistent.
2020-07-31 11:50:55 -07:00
basic-block-sections-clusters.ll
Append ".__part." to every basic block section symbol.
2020-12-23 11:35:44 -08:00
basic-block-sections-cold.ll
[llvm] Set the default for -bbsections-cold-text-prefix to .text.split.
2020-10-14 12:16:36 -07:00
basic-block-sections-directjumps.ll
…
basic-block-sections-eh.ll
[CodeGen][SimplifyCFG] Teach DwarfEHPrepare to preserve DomTree
2021-01-02 01:01:19 +03:00
basic-block-sections-labels-empty-function.ll
[Propeller] Do not generate the BB address map for empty functions.
2021-03-29 20:15:01 -07:00
basic-block-sections-labels-functions-sections.ll
Introduce and use a new section type for the bb_addr_map section.
2020-10-08 11:13:19 -07:00
basic-block-sections-labels.ll
Add missing 'CHECK' prefix to basic block labels test.
2021-03-25 16:41:41 -07:00
basic-block-sections-list.ll
Basic block sections should enable function sections implicitly.
2021-02-16 16:27:16 -08:00
basic-block-sections-listbb.ll
Append ".__part." to every basic block section symbol.
2020-12-23 11:35:44 -08:00
basic-block-sections-mir-parse.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
basic-block-sections-mir-print.ll
…
basic-block-sections-named-section.ll
Basic block sections for functions with implicit-section-name attribute
2021-04-29 12:29:34 -07:00
basic-block-sections-pragma-sections.ll
Basic block sections for functions with implicit-section-name attribute
2021-04-29 12:29:34 -07:00
basic-block-sections-source-drift.ll
Detect Source Drift with Propeller.
2021-01-29 18:47:26 -08:00
basic-block-sections-unreachable.ll
…
basic-block-sections.ll
Basic block sections should enable function sections implicitly.
2021-02-16 16:27:16 -08:00
basic-promote-integers.ll
…
bb_rotate.ll
…
bc-extract.ll
…
bigstructret2.ll
…
bigstructret.ll
[X86] Handle COPYs of physregs better (regalloc hints)
2018-09-19 18:59:08 +00:00
bit-piece-comment.ll
…
bit-test-shift.ll
[X86] Automatically generate various tests. NFC
2019-08-26 13:53:29 +00:00
bitcast2.ll
…
bitcast-and-setcc-128.ll
…
bitcast-and-setcc-256.ll
…
bitcast-and-setcc-512.ll
…
bitcast-i256.ll
…
bitcast-int-to-vector-bool-sext.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
bitcast-int-to-vector-bool-zext.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
bitcast-int-to-vector-bool.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
bitcast-int-to-vector.ll
…
bitcast-mmx.ll
…
bitcast-setcc-128.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
bitcast-setcc-256.ll
…
bitcast-setcc-512.ll
…
bitcast-vector-bool.ll
Fix the default alignment of i1 vectors.
2021-07-31 14:09:59 -07:00
bitcast.ll
…
bitcnt-false-dep.ll
…
bitreverse.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
bittest-intrin.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
block_set.ll
…
block-placement.ll
…
block-placement.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
bmi2-x86_64.ll
…
bmi2.ll
…
bmi-intrinsics-fast-isel-x86_64.ll
…
bmi-intrinsics-fast-isel.ll
…
bmi-x86_64.ll
…
bmi.ll
…
bool-ext-inc.ll
…
bool-math.ll
[X86] Enable 8-bit OR with disjoint bits to convert to LEA
2019-03-05 18:37:33 +00:00
bool-simplify.ll
…
bool-vector.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
bool-zext.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
br-fold.ll
…
branchfolding-catchpads.ll
…
branchfolding-debug-invariant.mir
…
branchfolding-debugloc.ll
…
branchfolding-ehpad.mir
…
branchfolding-landingpads.ll
…
branchfolding-undef.mir
…
brcond.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
break-anti-dependencies.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
break-false-dep.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
broadcast-elm-cross-splat-vec.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
broadcastm-lowering.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
bss_pagealigned.ll
…
bswap_tree2.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
bswap_tree.ll
…
bswap-inline-asm.ll
…
bswap-rotate.ll
…
bswap-vector.ll
…
bswap-wide-int.ll
…
bswap.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
bt.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
btc_bts_btr.ll
…
btq.ll
…
bug26810.ll
…
bug37521.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
bug47278-eflags-error.mir
…
bug47278.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
bug80500.ll
…
build_fp16_constant_vector.ll
[X86] Building constant vector which element type is half will cause assertion fail.
2021-08-24 14:34:30 +08:00
build-vector-128.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
build-vector-256.ll
…
build-vector-512.ll
…
buildvec-extract.ll
…
buildvec-insertvec.ll
[X86][SSE] combineExtractWithShuffle - support zero-extending to allow extracting from narrow shuffle masks
2021-01-29 14:22:10 +00:00
bypass-slow-division-32.ll
…
bypass-slow-division-64.ll
…
bypass-slow-division-tune.ll
…
byref.ll
…
byval2.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
byval3.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
byval4.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
byval5.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
byval6.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
byval7.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
byval-align.ll
…
byval-callee-cleanup.ll
…
byval.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
cache-intrinsic.ll
…
call-imm.ll
…
call-push.ll
…
call-rv-marker.ll
[ObjC][ARC] Use the addresses of the ARC runtime functions instead of
2021-09-08 11:58:03 -07:00
call-site-info-output.ll
…
callbr-asm-bb-exports.ll
…
callbr-asm-blockplacement.ll
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
callbr-asm-branch-folding.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
callbr-asm-destinations.ll
…
callbr-asm-errors.ll
Implementation of asm-goto support in LLVM
2019-02-08 20:48:56 +00:00
callbr-asm-instr-scheduling.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
callbr-asm-kill.mir
[PHIElimination] Account for INLINEASM_BR when inserting kills
2021-10-07 20:04:39 +01:00
callbr-asm-label-addr.ll
…
callbr-asm-obj-file.ll
…
callbr-asm-outputs-pred-succ.ll
[MIRParser] Add support for IsInlineAsmBrIndirectTarget
2021-10-07 19:08:01 +01:00
callbr-asm-outputs.ll
…
callbr-asm-phi-placement.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
callbr-asm-sink.ll
…
callbr-asm.ll
…
callbr-codegenprepare.ll
…
cas.ll
…
cast-vsel.ll
…
catch.ll
…
catchpad-dynamic-alloca.ll
…
catchpad-lifetime.ll
…
catchpad-realign-savexmm.ll
…
catchpad-regmask.ll
…
catchpad-reuse.ll
…
catchpad-weight.ll
…
catchret-empty-fallthrough.ll
Fix SEH table addresses for Windows
2021-08-20 22:32:12 +03:00
catchret-fallthrough.ll
…
catchret-regmask.ll
…
cet_endbr_imm_enhance.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
cf-opt-memops.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
cfguard-checks.ll
…
cfguard-module-flag.ll
…
cfguard-x86-64-vectorcall.ll
…
cfguard-x86-vectorcall.ll
…
cfi-basic-block-sections-1.ll
Append ".__part." to every basic block section symbol.
2020-12-23 11:35:44 -08:00
cfi-epilogue-with-return.mir
…
cfi-epilogue-without-return.mir
…
cfi-inserter-basic-block-sections-callee-save-registers.ll
…
cfi-inserter-callee-save-register-2.mir
…
cfi-inserter-callee-save-register.mir
…
cfi-inserter-cfg-with-merge.mir
…
cfi-inserter-check-order.ll
…
cfi-inserter-noreturnblock.mir
…
cfi-inserter-verify-inconsistent-csr.mir
…
cfi-inserter-verify-inconsistent-loc.mir
…
cfi-inserter-verify-inconsistent-offset.mir
…
cfi-inserter-verify-inconsistent-register.mir
…
cfi-xmm.ll
…
cfi.ll
…
cfstring.ll
…
cgp-usubo.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
chain_order.ll
…
change-compare-stride-1.ll
…
change-compare-stride-trickiness-0.ll
…
change-compare-stride-trickiness-1.ll
…
change-compare-stride-trickiness-2.ll
…
change-unsafe-fp-math.ll
…
cldemote-intrinsic.ll
…
cleanuppad-inalloca.ll
…
cleanuppad-large-codemodel.ll
…
cleanuppad-realign.ll
…
clear_upper_vector_element_bits.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
clear-bitfield.ll
…
clear-highbits.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
clear-lowbits.ll
[X86] Move newly-added tests into the right file
2021-09-07 23:20:36 +03:00
clflushopt.ll
…
clwb.ll
…
clz.ll
[CGP] despeculateCountZeros - Don't create is-zero branch if cttz/ctlz source is known non-zero
2021-07-24 13:11:49 +01:00
clzero.ll
[X86] Regenerate clzero.ll tests
2020-12-08 15:36:47 +00:00
cmov-double.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
cmov-fp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
cmov-into-branch.ll
…
cmov-promotion.ll
…
cmov.ll
[X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760)
2021-06-30 18:46:50 +01:00
cmovcmov.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
cmp-bool.ll
[DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1)
2020-07-15 07:34:22 +00:00
cmp-concat.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
cmp-fast-isel.ll
…
cmp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
cmpxchg8b_alloca_regalloc_handling.ll
…
cmpxchg8b.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
cmpxchg-clobber-flags.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
cmpxchg-i1.ll
…
cmpxchg-i128-i1.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
coal-sections.ll
…
coalesce_commute_movsd.ll
…
coalesce_commute_subreg.ll
…
coalesce-dbg-value-subreg-rewrite.mir
…
coalesce-dead-lanes.mir
…
coalesce-esp.ll
…
coalesce-implicitdef.ll
…
coalescer-commute1.ll
…
coalescer-commute2.ll
…
coalescer-commute3.ll
…
coalescer-commute4.ll
…
coalescer-commute5.ll
…
coalescer-cross.ll
…
coalescer-dce2.ll
…
coalescer-dce.ll
…
coalescer-identity.ll
…
coalescer-remat.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
coalescer-subreg.ll
…
coalescer-win64.ll
…
code_placement_align_all.ll
…
code_placement_cold_loop_blocks.ll
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
2019-06-14 23:08:59 +00:00
code_placement_eh.ll
Move the personality function from LandingPadInst to Function
2015-06-17 20:52:32 +00:00
code_placement_ignore_succ_in_inner_loop.ll
…
code_placement_loop_rotation2.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
code_placement_loop_rotation3.ll
…
code_placement_loop_rotation.ll
[LLVM] Remove unwanted --check-prefix=CHECK from unit tests. NFC.
2016-04-19 23:51:52 +00:00
code_placement_no_header_change.ll
Revert [MBP] Disable aggressive loop rotate in plain mode
2019-08-29 19:03:58 +00:00
code_placement.ll
[test] Add explicit dso_local to constant/global variable declarations
2020-12-04 13:51:01 -08:00
code-model-elf-memset.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
code-model-elf.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
code-model-kernel.ll
[CodeGen][SimplifyCFG] Teach DwarfEHPrepare to preserve DomTree
2021-01-02 01:01:19 +03:00
codegen-prepare-addrmode-sext.ll
…
codegen-prepare-cast.ll
…
codegen-prepare-collapse.ll
[NFC] Fix typo in triples from unkown to unknown
2020-07-02 16:21:54 +08:00
codegen-prepare-crash.ll
…
codegen-prepare-extload.ll
[CodeGenPrep]Restructure promoting Ext to form ExtLoad
2017-03-17 19:05:21 +00:00
codegen-prepare-replacephi2.mir
…
codegen-prepare-replacephi.mir
…
codegen-prepare-uaddo.ll
…
codegen-prepare.ll
Turn on -addr-sink-using-gep by default.
2017-04-06 22:42:18 +00:00
codemodel.ll
[test] Add explicit dso_local to constant/global variable declarations
2020-12-04 13:51:01 -08:00
coff-comdat2.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
coff-comdat3.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
coff-comdat.ll
[IR] Rename comdat noduplicates to comdat nodeduplicate
2021-07-20 12:47:10 -07:00
coff-feat00.ll
…
coff-fp-section-name.ll
…
coff-linkonce.ll
…
coff-no-dead-strip.ll
…
coff-weak.ll
…
coldcc64.ll
…
combine-64bit-vec-binop.ll
…
combine-abs.ll
[X86] Use CMOVNS for abs instead of CMOVGE.
2021-10-14 12:28:28 -07:00
combine-adc.ll
…
combine-add-ssat.ll
[ISel] Expand saddsat and ssubsat via asr and xor
2021-08-19 16:08:07 +01:00
combine-add-usat.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
combine-add.ll
[DAGCombiner] don't try to partially reduce add-with-overflow ops
2021-07-29 08:51:54 -04:00
combine-addo.ll
…
combine-adx.ll
…
combine-and.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
combine-avx2-intrinsics.ll
…
combine-avx-intrinsics.ll
…
combine-bextr.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
combine-bitreverse.ll
[SelectionDAG] Optimize bitreverse expansion to minimize the number of mask constants.
2021-08-26 09:33:24 -07:00
combine-bitselect.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
combine-bswap.ll
…
combine-concatvectors.ll
[X86][AVX] Add missing X86ISD::VBROADCAST(v2f64 -> v4f64) isel pattern for AVX1 targets
2021-09-09 12:16:23 +01:00
combine-fabs.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
combine-fcopysign.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
combine-lds.ll
…
combine-movmsk-avx.ll
…
combine-movmsk.ll
…
combine-mul.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
combine-mulo.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
combine-multiplies.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
combine-or.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
combine-pmadd.ll
[X86] Fold PMADD(x,0) or PMADD(0,x) -> 0
2021-09-02 10:48:50 +01:00
combine-pmuldq.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
combine-ptest.ll
…
combine-rotates.ll
…
combine-sbb.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
combine-sdiv.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
combine-select.ll
…
combine-sext-in-reg.ll
…
combine-shl.ll
[DAG] DAGCombiner::foldSelectOfBinops - propagate the common flags to the merged binop
2021-07-18 18:38:59 +01:00
combine-smax.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
combine-smin.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
combine-sra.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
combine-srem.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
combine-srl.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
combine-sse41-intrinsics.ll
…
combine-sub-ssat.ll
…
combine-sub-usat.ll
…
combine-sub.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
combine-subo.ll
…
combine-testm-and.ll
…
combine-testpd.ll
…
combine-testps.ll
…
combine-udiv.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
combine-umax.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
combine-umin.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
combine-undef-index-mscatter.ll
…
combine-urem.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
combineIncDecVector-crash.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
commandline-metadata.ll
Implement -frecord-command-line (-frecord-gcc-switches)
2018-12-14 15:38:15 +00:00
commute-3dnow.ll
…
commute-blend-avx2.ll
…
commute-blend-sse41.ll
…
commute-clmul.ll
…
commute-fcmp.ll
…
commute-intrinsic.ll
…
commute-two-addr.ll
…
commute-vpclmulqdq-avx512.ll
…
commute-vpclmulqdq-avx.ll
…
commute-xop.ll
…
commuted-blend-mask.ll
…
compact-unwind.ll
…
compare_folding.ll
…
compare-add.ll
…
compare-global.ll
…
compare-inf.ll
…
compiler_used.ll
…
complex-asm.ll
…
complex-fastmath.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
complex-fca.ll
…
computeKnownBits_urem.ll
…
concat-cast.ll
[X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction.
2021-07-14 12:03:49 +01:00
conditional-indecrement.ll
…
conditional-tailcall-pgso.ll
…
conditional-tailcall-samedest.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
conditional-tailcall.ll
…
consecutive-load-shuffle.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
const-base-addr.ll
…
const-shift-of-constmasked.ll
…
constant-combines.ll
…
constant-hoisting-and.ll
…
constant-hoisting-bfi.ll
…
constant-hoisting-cmp.ll
…
constant-hoisting-optnone.ll
…
constant-hoisting-shift-immediate.ll
…
constant-pool-remat-0.ll
…
constant-pool-sharing.ll
…
constpool.ll
X86: Do not use llc -march in tests.
2017-08-02 00:28:10 +00:00
constrained-fp80-trunc-ext.ll
…
constructor.ll
[static initializers] Emit global_ctors and global_dtors in reverse order when .ctors/.dtors are used.
2021-06-10 16:44:47 -07:00
convert-2-addr-3-addr-inc64.ll
…
convertphitype.ll
…
copy-eflags-liveinlists.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
copy-eflags.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
copy-low-subvec-elt-to-high-subvec-elt.ll
[X86][TLI] SimplifyDemandedVectorEltsForTargetNode(): don't break apart broadcasts from which not just the 0'th elt is demanded
2021-09-19 17:38:32 +03:00
copy-propagation.ll
…
copysign-constant-magnitude.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
cpus-amd-no-x86_64.ll
…
cpus-amd.ll
…
cpus-intel-no-x86_64.ll
…
cpus-intel.ll
…
cpus-no-x86_64.ll
…
cpus-other.ll
…
crash-lre-eliminate-dead-def.ll
…
crash-nosse.ll
…
crash-O0.ll
…
crash.ll
…
crc32-intrinsics-fast-isel-x86_64.ll
[X86] Add CRC32 feature.
2021-09-06 17:24:30 +08:00
crc32-intrinsics-x86_64.ll
[X86] Add CRC32 feature.
2021-09-06 17:24:30 +08:00
crc32-intrinsics-x86.ll
[X86] Add CRC32 feature.
2021-09-06 17:24:30 +08:00
crc32-target-feature.ll
[X86] Add CRC32 feature.
2021-09-06 17:24:30 +08:00
critical-anti-dep-breaker.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
critical-edge-split-2.ll
…
cse-add-with-overflow.ll
…
csr-split.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
cstring.ll
[Codegen][X86] Modernize/regenerate old tests. NFCI.
2019-12-10 00:27:46 +01:00
ctor-priority-coff.ll
…
ctpop-combine.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
cvt16-2.ll
[X86] AVX512FP16 instructions enabling 3/6
2021-08-18 09:03:41 +08:00
cvt16.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
cvtv2f32.ll
…
cxx_tlscc64.ll
…
dag-fmf-cse.ll
…
dag-merge-fast-accesses.ll
…
dag-optnone.ll
…
dag-rauw-cse.ll
…
dag-update-nodetomatch.ll
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
dagcombine-and-setcc.ll
…
dagcombine-buildvector.ll
…
dagcombine-cse.ll
…
dagcombine-dead-store.ll
…
dagcombine-select.ll
…
dagcombine-shifts.ll
…
dagcombine-tokenfactor-limit-crash.ll
…
dagcombine-unsafe-math.ll
…
darwin-bzero.ll
…
darwin-no-dead-strip.ll
…
darwin-preemption.ll
…
darwin-quote.ll
…
darwin-tls.ll
…
dbg-baseptr.ll
…
dbg-changes-codegen-branch-folding2.mir
…
dbg-changes-codegen-branch-folding.ll
…
dbg-changes-codegen.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
dbg-combine.ll
…
dbg-distringtype-uint.ll
Moved the test to X86 as it's x86 specific.
2021-08-31 14:48:29 -04:00
dbg-line-0-no-discriminator.ll
…
dbg-list-dependencies.ll
…
dbg-value-func-arg.ll
…
dbg-value-superreg-copy.mir
…
DbgValueOtherTargets.test
…
debug-loclists-lto.ll
…
debug-loclists.ll
[DebugInfo] Fix emitting DWARF64 .debug_loclists sections (14/19).
2020-09-15 12:23:31 +07:00
debug-nodebug-crash.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
debuginfo-locations-dce.ll
…
debugloc-argsize.ll
…
debugloc-no-line-0.ll
…
delete-dead-instrs-with-live-uses.mir
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
deopt-bundles.ll
…
deopt-intrinsic-cconv.ll
…
deopt-intrinsic.ll
…
disable-shrink-store.ll
…
disable-tail-calls.ll
…
discontiguous-loops.ll
…
discriminate-mem-ops-missing-info.ll
…
discriminate-mem-ops-skip-pfetch.ll
…
discriminate-mem-ops.ll
…
div8.ll
…
div-rem-pair-recomposition-signed.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
div-rem-pair-recomposition-unsigned.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
div-rem-simplify.ll
…
divide-by-constant.ll
…
divide-windows-itanium.ll
…
divmod128.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
divrem8_ext.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
divrem.ll
…
dllexport-x86_64.ll
…
dllexport.ll
[COFF] Force Symbols containing '.' to be quoted
2021-08-30 17:26:57 -04:00
dllimport-x86_64.ll
…
dllimport.ll
…
dollar-name.ll
…
domain-reassignment-implicit-def.ll
…
domain-reassignment-test.ll
…
domain-reassignment.mir
[MachineVerifier] Diagnose invalid INSERT_SUBREGs
2021-07-20 17:32:29 -07:00
dont-remove-empty-preheader.ll
[CodeGenPrepare] Make TargetPassConfig required
2020-02-02 09:28:45 -08:00
dont-trunc-store-double-to-float.ll
…
dropped_constructor.ll
…
dso_local_equivalent.ll
…
dtor-priority-coff.ll
…
dup-cost.ll
…
dwarf_eh_resume.ll
…
dwarf-comp-dir.ll
…
dwarf-eh-prepare.ll
Re-apply the fix on DwarfEHPrepare and add a test
2021-10-02 21:50:35 -04:00
dwarf-headers.ll
…
dwarf-split-line-1.ll
…
dwarf-split-line-2.ll
…
dyn_alloca_aligned.ll
…
dyn-stackalloc.ll
…
dynamic-alloca-in-entry.ll
…
dynamic-alloca-lifetime.ll
…
dynamic-allocas-VLAs-stack-align.ll
reland [IR] make -stack-alignment= into a module attr
2021-06-08 10:59:46 -07:00
dynamic-allocas-VLAs.ll
reland [IR] make -stack-alignment= into a module attr
2021-06-08 10:59:46 -07:00
dynamic-regmask.ll
…
DynamicCalleeSavedRegisters.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
early-cfi-sections.ll
…
early-ifcvt-crash.ll
…
early-ifcvt-remarks.ll
…
early-ifcvt.ll
…
eh_frame.ll
…
eh-frame-unreachable.ll
…
eh-label.ll
…
eh-nolandingpads.ll
…
eh-null-personality.ll
…
eh-unknown.ll
…
ehcontguard.ll
…
eip-addressing-i386.ll
…
element-wise-atomic-memory-intrinsics.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
elf-associated-discarded.ll
Fix typo of colon to semicolon in lit tests
2021-10-09 10:03:50 +08:00
elf-associated.ll
…
elf-comdat2.ll
…
elf-comdat.ll
…
elf-group.ll
[IR] Rename comdat noduplicates to comdat nodeduplicate
2021-07-20 12:47:10 -07:00
elf-retain.ll
…
elf-unique-sections-by-flags.ll
…
embed-bitcode.ll
Set alignment of .llvmbc and .llvmcmd to 1
2020-08-29 18:27:34 -07:00
emit-big-cst.ll
…
empty-function.ll
[Windows] Replace TrapUnreachable with an int3 insertion pass
2019-09-09 23:04:25 +00:00
empty-functions.ll
Replace "no-frame-pointer-*" function attributes with "frame-pointer"
2019-01-14 10:55:55 +00:00
empty-struct-return-type.ll
…
emutls_generic.ll
…
emutls-pic.ll
…
emutls-pie.ll
…
emutls.ll
…
enqcmd-intrinsics.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
epilogue-cfi-fp.ll
…
epilogue-cfi-no-fp.ll
…
epilogue.ll
…
equiv_with_fndef.ll
…
equiv_with_vardef.ll
…
evex-to-vex-compress.mir
…
exception-label.ll
…
exedeps-movq.ll
…
exedepsfix-broadcast.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
expand-call-rvmarker.mir
[ObjC][ARC] Use the addresses of the ARC runtime functions instead of
2021-09-08 11:58:03 -07:00
expand-integer-x86_64-intrinsic-error.ll
…
expand-opaque-const.ll
…
expand-post-ra-pseudo.mir
…
expand-vr64-gr64-copy.mir
…
explicit-section-mergeable.ll
…
extend-set-cc-uses-dbg.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
extend.ll
…
extended-fma-contraction.ll
…
extern_weak.ll
…
extmul64.ll
…
extmul128.ll
…
extract-bits.ll
[X86] Regenerate bit extraction tests, cleaning up check-prefixes.
2020-12-16 14:48:21 +00:00
extract-combine.ll
…
extract-concat.ll
…
extract-extract.ll
…
extract-fp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
extract-insert.ll
Recommit r367901 "[X86] Enable -x86-experimental-vector-widening-legalization by default."
2019-08-07 16:24:26 +00:00
extract-lowbits.ll
[NFC][X86] Adjust multi-use tests in extract-lowbits.ll
2021-09-07 23:20:36 +03:00
extract-store.ll
…
extractelement-fp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
extractelement-from-arg.ll
…
extractelement-index.ll
…
extractelement-legalization-cycle.ll
…
extractelement-legalization-store-ordering.ll
…
extractelement-load.ll
[CodeGen][X86] Remove unused trivial check-prefixes from all CodeGen/X86 directory.
2020-11-16 09:45:55 +08:00
extractelement-shuffle.ll
…
extractps.ll
…
f16c-intrinsics-fast-isel.ll
…
f16c-intrinsics-upgrade.ll
…
f16c-intrinsics.ll
…
fabs.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fadd-combines.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fast-cc-callee-pops.ll
…
fast-cc-merge-stack-adj.ll
…
fast-cc-pass-in-regs.ll
…
fast-isel-abort-warm.ll
…
fast-isel-agg-constant.ll
…
fast-isel-args-fail2.ll
…
fast-isel-args-fail.ll
…
fast-isel-args.ll
…
fast-isel-atomic.ll
X86: Do not use llc -march in tests.
2017-08-02 00:28:10 +00:00
fast-isel-avoid-unnecessary-pic-base.ll
…
fast-isel-bail.ll
…
fast-isel-bc.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fast-isel-bitcast-crash.ll
…
fast-isel-bitcasts-avx512.ll
…
fast-isel-bitcasts-avx.ll
…
fast-isel-bitcasts.ll
…
fast-isel-branch_weights.ll
…
fast-isel-call-bool.ll
…
fast-isel-call-cleanup.ll
…
fast-isel-call.ll
…
fast-isel-cmp-branch2.ll
…
fast-isel-cmp-branch3.ll
…
fast-isel-cmp-branch.ll
…
fast-isel-cmp.ll
[CodeGen][X86] Remove unused trivial check-prefixes from all CodeGen/X86 directory.
2020-11-16 09:45:55 +08:00
fast-isel-constpool.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fast-isel-constrain-store-indexreg.ll
…
fast-isel-deadcode.ll
Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1)
2018-01-19 17:13:12 +00:00
fast-isel-divrem-x86-64.ll
…
fast-isel-divrem.ll
…
fast-isel-double-half-convertion.ll
…
fast-isel-emutls.ll
…
fast-isel-expect.ll
…
fast-isel-extract.ll
…
fast-isel-float-half-convertion.ll
…
fast-isel-fneg.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fast-isel-fold-mem.ll
…
fast-isel-fptrunc-fpext.ll
…
fast-isel-freeze.ll
…
fast-isel-gc-intrinsics.ll
…
fast-isel-gep.ll
…
fast-isel-gv.ll
…
fast-isel-i1.ll
…
fast-isel-int-float-conversion-x86-64.ll
…
fast-isel-int-float-conversion.ll
…
fast-isel-load-i1.ll
…
fast-isel-mem.ll
…
fast-isel-movsbl-indexreg.ll
…
fast-isel-nontemporal.ll
…
fast-isel-noplt-pic.ll
…
fast-isel-prolog-dbgloc.ll
…
fast-isel-ret-ext.ll
…
fast-isel-select-cmov2.ll
…
fast-isel-select-cmov.ll
…
fast-isel-select-cmp.ll
AsmPrinter: mark the beginning and the end of a function in verbose mode
2017-05-23 21:22:16 +00:00
fast-isel-select-pseudo-cmov.ll
…
fast-isel-select-sse.ll
…
fast-isel-select.ll
[FastISel] Flush local value map on every instruction
2021-01-11 08:32:36 -08:00
fast-isel-sext-zext.ll
…
fast-isel-sext.ll
…
fast-isel-shift.ll
[X86] Enable 8-bit SHL to convert to LEA
2019-03-05 18:37:41 +00:00
fast-isel-sse12-fptoint.ll
…
fast-isel-stackcheck.ll
…
fast-isel-store.ll
…
fast-isel-tailcall.ll
…
fast-isel-tls.ll
…
fast-isel-trunc-kill-subreg.ll
…
fast-isel-uint-float-conversion-x86-64.ll
…
fast-isel-uint-float-conversion.ll
[X86] Remove the suffix on vcvt[u]si2ss/sd register variants in assembly printing.
2019-05-06 21:39:51 +00:00
fast-isel-undef-fp.ll
[X86] Selecting fld0 for undefined value in fast ISEL.
2021-06-26 08:43:09 +08:00
fast-isel-vecload.ll
[CodeGen][X86] Remove unused trivial check-prefixes from all CodeGen/X86 directory.
2020-11-16 09:45:55 +08:00
fast-isel-x32.ll
…
fast-isel-x86-64.ll
…
fast-isel-x86.ll
…
fast-isel.ll
[SelDag] Add FREEZE
2020-03-24 23:04:58 +09:00
fast-regalloc-live-out-debug-values.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fastcall-correct-mangling.ll
…
fastcc3struct.ll
X86: Do not use llc -march in tests.
2017-08-02 00:28:10 +00:00
fastcc-2.ll
…
fastcc-byval.ll
…
fastcc-sret.ll
…
fastcc.ll
…
fastisel-gep-promote-before-add.ll
…
fastisel-memset-flush.ll
…
fastisel-softfloat.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fastmath-float-half-conversion.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fcmove.ll
…
fcmp-constant.ll
…
fcmp-logic.ll
[x86] add test for 3 fcmps and logic; NFC
2021-09-30 11:02:59 -04:00
fdiv-combine-vec.ll
…
fdiv-combine.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fdiv.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fentry-insertion.ll
…
field-extract-use-trunc.ll
…
fildll.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
file-directive.ll
…
file-source-filename.ll
…
finite-libcalls.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fixed-stack-di-mir.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
fixup-bw-copy.ll
…
fixup-bw-copy.mir
…
fixup-bw-inst.ll
…
fixup-bw-inst.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fixup-lea.ll
…
flags-copy-lowering.mir
Recommit "[X86] Clear kill flags when rewriting SETCC uses in flag copy lowering."
2021-09-21 14:59:25 -07:00
float-asmprint.ll
…
float-conv-elim.ll
…
floor-soft-float.ll
…
flt-rounds.ll
…
fltused_function_pointer.ll
Fix emission of _fltused for MSVC.
2019-01-24 18:34:00 +00:00
fltused_math.ll
…
fltused.ll
…
fma4-commute-x86.ll
…
fma4-fneg-combine.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fma4-intrinsics-x86_64-folded-load.ll
…
fma4-intrinsics-x86-upgrade.ll
…
fma4-intrinsics-x86.ll
…
fma4-scalar-memfold.ll
…
fma_patterns_wide.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fma_patterns.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fma-commute-loop.ll
…
fma-commute-x86.ll
…
fma-do-not-commute.ll
…
fma-fneg-combine-2.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fma-fneg-combine.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fma-intrinsics-canonical.ll
…
fma-intrinsics-fast-isel.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fma-intrinsics-phi-213-to-231.ll
…
fma-intrinsics-x86-upgrade.ll
…
fma-intrinsics-x86.ll
…
fma-phi-213-to-231.ll
…
fma-scalar-combine.ll
[DAGCombine] Add node level checks for fp-contract and fp-ninf in visitFMULForFMADistributiveCombine().
2021-09-02 11:33:14 +05:30
fma-scalar-memfold.ll
…
fma-signed-zero.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fma.ll
[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
2021-06-11 16:49:12 +01:00
fmaddsub-combine.ll
…
fmaxnum.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fmf-flags.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fmf-propagation.ll
…
fmf-reduction.ll
…
fminnum.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fmsubadd-combine.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fmul-combines.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fnabs.ll
…
fold-add.ll
…
fold-and-shift-x86_64.ll
…
fold-and-shift.ll
…
fold-call-2.ll
…
fold-call-3.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fold-call-oper.ll
…
fold-call.ll
…
fold-imm.ll
…
fold-load-binops.ll
…
fold-load-unops.ll
…
fold-load-vec.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fold-load.ll
…
fold-mul-lohi.ll
…
fold-pcmpeqd-1.ll
…
fold-pcmpeqd-2.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fold-push.ll
…
fold-rmw-ops.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fold-sext-trunc.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fold-tied-op.ll
…
fold-vector-bv-crash.ll
…
fold-vector-sext-crash2.ll
…
fold-vector-sext-crash.ll
…
fold-vector-sext-zext.ll
…
fold-vector-shl-crash.ll
…
fold-vector-shuffle-crash.ll
…
fold-vector-trunc-sitofp.ll
…
fold-vex.ll
…
fold-xmm-zero.ll
…
fold-zext-trunc.ll
…
fops-windows-itanium.ll
…
force-align-stack-alloca.ll
reland [IR] make -stack-alignment= into a module attr
2021-06-08 10:59:46 -07:00
force-align-stack.ll
…
fp2sint.ll
…
fp80-strict-libcalls.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp80-strict-scalar-cmp.ll
…
fp80-strict-scalar.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp128-calling-conv.ll
…
fp128-cast-strict.ll
[X86] AVX512FP16 instructions enabling 1/6
2021-08-10 12:46:01 +08:00
fp128-cast.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
fp128-compare.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp128-extract.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp128-g.ll
…
fp128-i128.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp128-libcalls-strict.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp128-libcalls.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp128-load.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp128-select.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp128-store.ll
…
fp_constant_op.ll
…
fp_load_cast_fold.ll
…
fp_load_fold.ll
…
fp-arith.ll
…
fp-cvt.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp-double-rounding.ll
…
fp-elim-and-no-fp-elim.ll
…
fp-elim.ll
…
fp-fast.ll
…
fp-fold.ll
…
fp-immediate-shorten.ll
…
fp-in-intregs.ll
…
fp-intrinsics-flags-x86_64.ll
…
fp-intrinsics-flags.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
fp-intrinsics-fma.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp-intrinsics.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp-load-trunc.ll
…
fp-logic-replace.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
fp-logic.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp-round.ll
[X86][ISel] Lowering FROUND(f16) and FROUNDEVEN(f16)
2021-09-27 13:35:03 +08:00
fp-roundeven.ll
[X86][ISel] Lowering FROUND(f16) and FROUNDEVEN(f16)
2021-09-27 13:35:03 +08:00
fp-select-cmp-and.ll
…
fp-stack-2results.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp-stack-compare-cmov.ll
…
fp-stack-compare.ll
Revert "[NFC][CodeGen] Add unary fneg tests to fp-fast.ll fp-fold.ll fp-in-intregs.ll fp-stack-compare-cmov.ll fp-stack-compare.ll fsxor-alignment.ll"
2019-06-13 19:25:16 +00:00
fp-stack-direct-ret.ll
…
fp-stack-O0-crash.ll
…
fp-stack-O0.ll
…
fp-stack-ret-conv.ll
[Codegen][X86] Modernize/regenerate old tests. NFCI.
2019-12-10 00:27:46 +01:00
fp-stack-ret-store.ll
…
fp-stack-ret.ll
…
fp-stack-retcopy.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
fp-stack-set-st1.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp-stack.ll
…
fp-strict-libcalls-msvc32.ll
…
fp-strict-scalar-cmp-fp16.ll
[X86] AVX512FP16 instructions enabling 2/6
2021-08-15 08:56:33 +08:00
fp-strict-scalar-cmp.ll
…
fp-strict-scalar-fp16.ll
[X86] AVX512FP16 instructions enabling 5/6
2021-08-24 09:07:19 +08:00
fp-strict-scalar-fptoint-fp16.ll
[X86] AVX512FP16 instructions enabling 3/6
2021-08-18 09:03:41 +08:00
fp-strict-scalar-fptoint.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp-strict-scalar-inttofp-fp16.ll
[X86] AVX512FP16 instructions enabling 3/6
2021-08-18 09:03:41 +08:00
fp-strict-scalar-inttofp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp-strict-scalar-round-fp16.ll
[X86][ISel] Lowering FROUND(f16) and FROUNDEVEN(f16)
2021-09-27 13:35:03 +08:00
fp-strict-scalar-round.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp-strict-scalar.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fp-trunc.ll
…
fp-undef.ll
…
fp-une-cmp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fpcmp-soft-fp.ll
…
fpenv.ll
…
fpstack-debuginstr-kill.ll
Remove irrelevant references to legacy git repositories from
2019-01-15 16:18:52 +00:00
fptosi-constant.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
fptosi-sat-scalar.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
fptoui-may-overflow.ll
[X86] Remove incorrect use of known bits in shuffle simplification.
2021-07-18 18:13:11 -07:00
fptoui-sat-scalar.ll
[X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction.
2021-07-14 12:03:49 +01:00
frame-base.ll
…
frame-lowering-debug-intrinsic-2.ll
…
frame-lowering-debug-intrinsic.ll
…
frame-order.ll
…
frameaddr.ll
…
frameregister.ll
…
freeze-combine.ll
…
freeze-constant-fold.ll
[DAG] isGuaranteedNotToBeUndefOrPoison - handle ISD::BUILD_VECTOR nodes
2021-07-31 15:08:25 +01:00
freeze-legalize.ll
[DAG] isGuaranteedNotToBeUndefOrPoison - handle ISD::BUILD_VECTOR nodes
2021-07-31 15:08:25 +01:00
freeze.ll
[X86] Add ISD::FREEZE and ISD::AssertAlign to the list of opcodes that don't guarantee upper 32 bits are zero.
2021-06-12 09:52:29 -07:00
frem-msvc32.ll
…
fsafdo_test1.ll
[SampleFDO] Add two passes of MIRAddFSDiscriminatorsPass
2021-08-11 11:11:04 -07:00
fsafdo_test2.ll
Fix CodeGen/X86/fsafdo_test2.ll fail in release
2021-08-19 16:54:04 +01:00
fsgsbase.ll
…
fshl.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
fshr.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
fsxor-alignment.ll
…
ftrunc.ll
[X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction.
2021-07-14 12:03:49 +01:00
full-lsr.ll
…
funclet-layout.ll
[Windows] Replace TrapUnreachable with an int3 insertion pass
2019-09-09 23:04:25 +00:00
function-alias.ll
…
function-subtarget-features-2.ll
X86: Do not use llc -march in tests.
2017-08-02 00:28:10 +00:00
function-subtarget-features.ll
[X86] Add CRC32 feature.
2021-09-06 17:24:30 +08:00
funnel-shift-rot.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
funnel-shift.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
ga-offset2.ll
…
ga-offset.ll
…
gather-addresses.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
gcc_except_table_bb_sections_ehpad_groups_with_cold.ll
…
gcc_except_table_bb_sections.ll
…
gcc_except_table_functions.ll
…
gcc_except_table-multi.ll
[IR] Rename comdat noduplicates to comdat nodeduplicate
2021-07-20 12:47:10 -07:00
gcc_except_table.ll
…
gep-expanded-vector.ll
…
getelementptr.ll
[CGP] Fix GEP issue with out of range APInt constant values not fitting in int64_t
2018-08-13 12:10:09 +00:00
gfni-intrinsics.ll
…
ghc-cc64.ll
…
ghc-cc.ll
…
global-access-pie.ll
…
global-fill.ll
…
global-sections-comdat.ll
…
global-sections-tls.ll
…
global-sections.ll
…
gnu-eh-alternative.ll
…
gnu-seh-nolpads.ll
…
gpr-to-mask.ll
…
greedy_regalloc_bad_eviction_sequence.ll
…
gs-fold.ll
…
h-register-addressing-32.ll
…
h-register-addressing-64.ll
…
h-register-store.ll
…
h-registers-0.ll
…
h-registers-1.ll
…
h-registers-2.ll
…
h-registers-3.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
haddsub-2.ll
…
haddsub-3.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
haddsub-4.ll
…
haddsub-broadcast.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
haddsub-shuf-undef-operand.ll
…
haddsub-shuf.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
haddsub-undef.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
haddsub.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
half-constrained.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
half.ll
[LegalizeTypes][X86] Improve ExpandIntRes_FP_TO_SINT/ExpandIntRes_FP_TO_UINT when input is SoftPromoteHalf.
2021-08-30 13:12:59 -07:00
handle-move.ll
…
heap-alloc-markers.mir
…
hhvm-cc.ll
…
hidden-vis-2.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
hidden-vis-3.ll
…
hidden-vis-4.ll
…
hidden-vis-pic.ll
…
hidden-vis.ll
…
hipe-cc64.ll
reland [IR] make -stack-alignment= into a module attr
2021-06-08 10:59:46 -07:00
hipe-cc.ll
reland [IR] make -stack-alignment= into a module attr
2021-06-08 10:59:46 -07:00
hipe-prologue.ll
…
hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
hoist-and-by-const-from-shl-in-eqcmp-zero.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
hoist-common.ll
…
hoist-invariant-load.ll
[tests] Stablize tests for possible change in deref semantics
2021-07-14 13:05:43 -07:00
hoist-spill-lpad.ll
…
hoist-spill.ll
…
horizontal-reduce-add.ll
…
horizontal-reduce-fadd.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
horizontal-reduce-smax.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
horizontal-reduce-smin.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
horizontal-reduce-umax.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
horizontal-reduce-umin.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
horizontal-shuffle-2.ll
[X86][SSE] Fix typo + infinite-loop in HOP(HOP'(X,X),HOP'(Y,Y)) fold (PR52040)
2021-10-02 15:31:12 +01:00
horizontal-shuffle-3.ll
…
horizontal-shuffle-4.ll
…
horizontal-shuffle-demanded.ll
…
horizontal-shuffle.ll
…
horizontal-sum.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
hot-unlikely-section-prefix.ll
…
huge-stack-offset2.ll
[X86] Emit fewer instructions to allocate >16GB stack frames
2017-03-17 20:25:49 +00:00
huge-stack-offset.ll
…
i1narrowfail.ll
[DAG] ReduceLoadOpStoreWidth - replace getABITypeAlign with allowsMemoryAccess (PR45116)
2021-09-25 18:35:57 +01:00
i2k.ll
…
i16lshr8pat.ll
…
i64-mem-copy.ll
…
i64-to-float.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
i128-add.ll
…
i128-and-beyond.ll
…
i128-fpconv-win64-strict.ll
[X86] Fix handling of i128<->fp on Windows
2021-09-29 13:05:59 +03:00
i128-fpconv-win64.ll
[X86] Fix handling of i128<->fp on Windows
2021-09-29 13:05:59 +03:00
i128-immediate.ll
…
i128-mul.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
i128-ret.ll
…
i128-sdiv.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
i128-udiv.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
i256-add.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
i386-setjmp-pic.ll
…
i386-shrink-wrapping.ll
…
i386-tlscall-fastregalloc.ll
…
i486-fence-loop.ll
…
i686-win-shrink-wrapping.ll
…
iabs.ll
[X86] Use CMOVNS for abs instead of CMOVGE.
2021-10-14 12:28:28 -07:00
icall-branch-funnel.ll
…
icmp-opt.ll
…
ident-metadata.ll
…
ifunc-asm.ll
…
illegal-bitfield-loadstore.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
illegal-insert.ll
X86: Do not use llc -march in tests.
2017-08-02 00:28:10 +00:00
illegal-vector-args-return.ll
…
immediate_merging64.ll
…
immediate_merging.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
implicit-faultmap.ll
…
implicit-null-check-negative.ll
[ImplicitNullChecks] Support complex addressing mode
2020-10-07 20:55:38 -04:00
implicit-null-check.ll
[ImplicitNullChecks] Support complex addressing mode
2020-10-07 20:55:38 -04:00
implicit-null-checks.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
implicit-null-chk-reg-rewrite.mir
…
implicit-use-spill.mir
…
imul-lea-2.ll
…
imul-lea.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
imul.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
inalloca-ctor.ll
…
inalloca-invoke.ll
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
inalloca-regparm.ll
…
inalloca-stdcall.ll
…
inalloca.ll
…
inc-of-add.ll
…
inconsistent_landingpad.ll
…
indirect-branch-tracking-cm-lager.ll
…
indirect-branch-tracking-eh2.ll
Revert "Revert "Temporarily do not drop volatile stores before unreachable""
2021-07-09 11:44:34 -04:00
indirect-branch-tracking-eh.ll
…
indirect-branch-tracking-r2.ll
…
indirect-branch-tracking.ll
…
indirect-hidden.ll
…
init-priority.ll
[X86] Reland D71360 Clean up UseInitArray initialization for X86ELFTargetObjectFile
2020-03-20 21:57:34 -07:00
inline-0bh.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
inline-asm-2addr.ll
…
inline-asm-A-constraint.ll
…
inline-asm-avx512f-v-constraint.ll
…
inline-asm-avx512f-x-constraint.ll
[X86] Enable half type support in inline assembly constraints
2021-09-01 09:29:31 +08:00
inline-asm-avx512vl-v-constraint-32bit.ll
…
inline-asm-avx512vl-v-constraint.ll
…
inline-asm-avx-v-constraint-32bit.ll
…
inline-asm-avx-v-constraint.ll
…
inline-asm-bad-constraint-n.ll
…
inline-asm-bad-modifier.ll
…
inline-asm-default-clobbers.ll
…
inline-asm-duplicated-constraint.ll
…
inline-asm-e-constraint.ll
…
inline-asm-error.ll
X86: Do not use llc -march in tests.
2017-08-02 00:28:10 +00:00
inline-asm-flag-clobber.ll
…
inline-asm-flag-output.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
inline-asm-fpstack.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
inline-asm-h.ll
…
inline-asm-i-constraint-i1.ll
…
inline-asm-imm-out-of-range.ll
…
inline-asm-modifier-c.ll
…
inline-asm-modifier-n.ll
…
inline-asm-modifier-q.ll
…
inline-asm-modifier-V.ll
…
inline-asm-mrv.ll
…
inline-asm-multilevel-gep.ll
…
inline-asm-n-constraint.ll
…
inline-asm-out-regs.ll
…
inline-asm-pic.ll
…
inline-asm-ptr-cast.ll
…
inline-asm-q-regs.ll
…
inline-asm-R-constraint.ll
X86: Do not use llc -march in tests.
2017-08-02 00:28:10 +00:00
inline-asm-sp-clobber-memcpy.ll
…
inline-asm-stack-realign2.ll
…
inline-asm-stack-realign3.ll
…
inline-asm-stack-realign.ll
[CodeGen] Print register names in lowercase in both MIR and debug output
2017-11-28 17:15:09 +00:00
inline-asm-tied.ll
…
inline-asm-x-i128.ll
…
inline-asm-x-scalar.ll
…
inline-asm.ll
X86: Do not use llc -march in tests.
2017-08-02 00:28:10 +00:00
inline-sse.ll
…
inlineasm-sched-bug.ll
Stricter check for the memory access.
2019-07-27 18:57:59 +00:00
innermost-loop-alignment.ll
[CodeGen] Add -align-loops
2021-08-04 12:45:18 -07:00
inreg.ll
…
ins_split_regalloc.ll
X86: Do not use llc -march in tests.
2017-08-02 00:28:10 +00:00
ins_subreg_coalesce-1.ll
…
ins_subreg_coalesce-2.ll
…
ins_subreg_coalesce-3.ll
…
insert-into-constant-vector.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
insert-loaded-scalar.ll
…
insert-positions.ll
…
insert-prefetch-inline.afdo
[AutoFDO] Properly merge context-sensitive profile of inlinee back to outlined function
2019-12-05 15:57:55 -08:00
insert-prefetch-inline.ll
[llvm] Opt-in flag for X86DiscriminateMemOps
2019-01-25 21:49:54 +00:00
insert-prefetch-invalid-instr.afdo
…
insert-prefetch-invalid-instr.ll
…
insert-prefetch-other.afdo
…
insert-prefetch.afdo
Revert "Revert r347596 "Support for inserting profile-directed cache prefetches""
2018-11-30 01:01:52 +00:00
insert-prefetch.ll
[llvm] Opt-in flag for X86DiscriminateMemOps
2019-01-25 21:49:54 +00:00
insertelement-copytoregs.ll
…
insertelement-duplicates.ll
…
insertelement-legalize.ll
…
insertelement-ones.ll
[X86] Improve i8 all-ones element insertion in pre-SSE4.1
2021-09-18 22:24:06 +03:00
insertelement-shuffle.ll
[X86] Lower insertions into upper half of an 256-bit vector as broadcast+blend (PR50971)
2021-08-17 18:45:10 +03:00
insertelement-var-index.ll
[X86] Fix lowering to illegal type in LowerINSERT_VECTOR_ELT
2021-07-28 08:16:59 +08:00
insertelement-zero.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
insertps-combine.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
insertps-from-constantpool.ll
…
insertps-O0-bug.ll
…
insertps-unfold-load-bug.ll
…
instr-symbols.mir
…
int-intrinsic.ll
…
intersect-fma-fmf.ll
…
interval-update-remat.ll
…
invalid-liveness.mir
…
invalid-shift-immediate.ll
…
invpcid-intrinsic.ll
…
ipra-inline-asm.ll
…
ipra-local-linkage.ll
…
ipra-reg-alias.ll
…
ipra-reg-usage.ll
[X86] Remove little support we had for MPX
2021-10-12 16:18:51 -07:00
ipra-transform.ll
…
isel-blendi-gettargetconstant.ll
…
isel-optnone.ll
X86: Do not use llc -march in tests.
2017-08-02 00:28:10 +00:00
isel-postprocessing-test-fold-memop.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
isel-sink2.ll
…
isel-sink3.ll
…
isel-sink.ll
…
isint.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
isnan2.ll
…
isnan.ll
…
ispositive.ll
…
jump_sign.ll
…
keylocker-intrinsics-fast-isel.ll
…
keylocker-intrinsics.ll
[X86] Adjust Keylocker handle mem size
2021-09-13 18:03:27 +08:00
known-bits-vector.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
known-bits.ll
…
known-signbits-vector.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
kshift.ll
…
label-annotation.ll
…
label-heapallocsite.ll
…
label-redefinition.ll
…
lack-of-signed-truncation-check.ll
[X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760)
2021-06-30 18:46:50 +01:00
lakemont.ll
…
large-code-model-isel.ll
X86: Do not use llc -march in tests.
2017-08-02 00:28:10 +00:00
large-constants.ll
…
large-gep-chain.ll
…
large-gep-scale.ll
…
large-global.ll
…
large-pic-string.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
late-address-taken.ll
…
late-remat-update-2.mir
…
late-remat-update.mir
…
ldzero.ll
…
lea-2.ll
…
lea-3.ll
…
lea-4.ll
…
lea-5.ll
…
lea-dagdag.ll
…
lea-opt2.ll
[X86FixupLEAs] Try again to transform the sequence LEA/SUB to SUB/SUB
2021-07-16 10:16:03 -07:00
lea-opt-cse1.ll
…
lea-opt-cse2.ll
…
lea-opt-cse3.ll
…
lea-opt-cse4.ll
…
lea-opt-memop-check-1.ll
…
lea-opt-memop-check-2.ll
…
lea-opt-with-debug.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
lea-opt.ll
…
lea-recursion.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
lea.ll
…
leaf-fp-elim.ll
…
leaFixup32.mir
…
leaFixup64.mir
[X86] Erase dead LEA instruction after converting it to MOV in FixupLEAPass::processInstrForSlow3OpLEA.
2019-12-11 07:51:23 -08:00
legalize-fmp-oeq-vector-select.ll
…
legalize-libcalls.ll
…
legalize-shift-64.ll
…
legalize-shift.ll
…
legalize-shl-vec.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
legalize-sub-zero-2.ll
…
legalize-sub-zero.ll
…
legalize-types-remapid.ll
…
legalize-vaarg.ll
…
legalizedag_vec.ll
…
libcall-sret.ll
…
licm-dominance.ll
[tests] Stablize tests for possible change in deref semantics
2021-07-14 13:05:43 -07:00
licm-nested.ll
…
licm-regpressure.ll
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
licm-symbol.ll
…
lifetime-alias.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
limit-split-cost.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
limited-prec.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
line-zero-prologue-end.ll
Do not emit prologue_end for line 0 locs if there is a non-zero loc present
2021-10-07 13:54:28 -07:00
linux-preemption.ll
[TargetMachine] Drop implied dso_local for definitions in ELF static relocation model/PIE
2020-12-30 16:57:50 -08:00
lit.local.cfg
…
live-out-reg-info.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
live-range-nosubreg.ll
…
liveness-local-regalloc.ll
…
llc-override-mcpu-mattr.ll
…
llc-start-stop-instance.ll
…
llrint-conv.ll
…
llround-conv.ll
…
load-chain.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
load-combine-dbg.ll
…
load-combine.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
load-local-v3i1.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
load-local-v3i129.ll
Fix the default alignment of i1 vectors.
2021-07-31 14:09:59 -07:00
load-local-v4i5.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
load-partial-dot-product.ll
[X86][SSE] Fix copy+paste typo in dot3_float4_as_float3 partial load test
2021-07-19 11:50:30 +01:00
load-partial.ll
[DAG] LoadedSlice::canMergeExpensiveCrossRegisterBankCopy - replace getABITypeAlign with allowsMemoryAccess (PR45116)
2021-08-24 15:28:30 +01:00
load-scalar-as-vector.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
load-slice.ll
…
loadStore_vectorizer.ll
Reapply "[LSV] Refactoring + supporting bitcasts to a type of different size"
2018-07-20 20:10:04 +00:00
loc-remat.ll
…
local_stack_symbol_ordering.ll
…
localescape.ll
…
log2_not_readnone.ll
…
logical-load-fold.ll
…
long-setcc.ll
…
longlong-deadload.ll
…
loop-blocks.ll
[PGO][PGSO] Enable size optimizations in code gen / target passes for cold code.
2019-12-13 11:01:19 -08:00
loop-hoist.ll
…
loop-rotate.ll
Revert [MBP] Disable aggressive loop rotate in plain mode
2019-08-29 19:03:58 +00:00
loop-search.ll
[Codegen] Merge tail blocks with no successors after block placement
2019-06-13 18:11:32 +00:00
loop-strength-reduce2.ll
…
loop-strength-reduce4.ll
…
loop-strength-reduce5.ll
…
loop-strength-reduce6.ll
…
loop-strength-reduce7.ll
…
loop-strength-reduce8.ll
…
loop-strength-reduce-2.ll
…
loop-strength-reduce-3.ll
…
loop-strength-reduce-crash.ll
…
loop-strength-reduce.ll
…
lower-bitcast.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
lower-ptrmask.ll
…
lower-vec-shift-2.ll
…
lower-vec-shift.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
lower-vec-shuffle-bug.ll
…
lrint-conv-i32.ll
…
lrint-conv-i64.ll
…
lround-conv-i32.ll
…
lround-conv-i64.ll
…
lrshrink.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
lsr-crash-empty-uses.ll
…
lsr-delayed-fold.ll
…
lsr-i386.ll
…
lsr-interesting-step.ll
…
lsr-loop-exit-cond.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
lsr-negative-stride.ll
…
lsr-nonaffine.ll
…
lsr-normalization.ll
…
lsr-overflow.ll
…
lsr-quadratic-expand.ll
…
lsr-redundant-addressing.ll
…
lsr-reuse-trunc.ll
…
lsr-reuse.ll
…
lsr-sort.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
lsr-static-addr.ll
…
lsr-wrap.ll
…
lvi-hardening-gadget-graph.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
lvi-hardening-indirectbr.ll
…
lvi-hardening-inline-asm.ll
…
lvi-hardening-loads.ll
…
lvi-hardening-ret.ll
…
lwp-intrinsics-x86_64.ll
…
lwp-intrinsics.ll
…
lzcnt-cmp.ll
…
lzcnt-tzcnt.ll
…
lzcnt-zext-cmp.ll
[x86] convert logic-of-FP-compares to FP logic-of-vector-compares
2021-09-24 11:38:19 -04:00
lzcnt.ll
…
macCatalyst.ll
[macCatalyst] Use macCatalyst pretty name in .build_version darwin
2019-07-12 22:06:08 +00:00
machine-combiner-int-vec.ll
…
machine-combiner-int.ll
…
machine-combiner.ll
[DAGCombine] reassoc flag shouldn't enable contract
2021-06-21 21:15:43 +00:00
machine-copy-dbgvalue.mir
[MachineCopyPropagation] Fix differences in code gen when compiling with -g
2021-07-02 19:27:06 +08:00
machine-copy-prop.mir
…
machine-cp-debug.mir
[MachineVerifier] Verify that a DBG_VALUE has a debug location
2020-05-28 13:53:40 -07:00
machine-cp-mask-reg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
machine-cp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
machine-cse.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
machine-function-splitter.ll
[CodeGen] Do not split functions with attr "implicit-section-name".
2021-04-21 21:51:33 -07:00
machine-outliner-cfi-tail-some.mir
…
machine-outliner-cfi-tail.mir
…
machine-outliner-debuginfo.ll
…
machine-outliner-disubprogram.ll
…
machine-outliner-noredzone.ll
…
machine-outliner-tailcalls.ll
…
machine-outliner.ll
…
machine-region-info.mir
…
machine-sink-and-implicit-null-checks.ll
…
machine-sink.ll
…
machine-trace-metrics-crash.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
MachineBranchProb.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
MachineSink-CritEdge.ll
…
MachineSink-DbgValue.ll
…
MachineSink-eflags.ll
…
machinesink-merge-debuginfo.ll
…
machinesink-null-debuginfo.ll
…
MachineSink-PHIUse.ll
…
MachineSink-SubReg.ll
Recommit 'Remove the restriction that MachineSinking is now stopped by
2016-08-12 03:33:22 +00:00
macho-comdat.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
macho-trap.ll
…
madd.ll
[X86] SimplifyDemandedVectorEltsForTargetNode - simplify PMADDWD for known zero elements
2021-10-04 14:36:45 +01:00
mangle-question-mark.ll
…
mask-negated-bool.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
masked_compressstore.ll
…
masked_expandload.ll
[X86] Lower insertions into upper half of an 256-bit vector as broadcast+blend (PR50971)
2021-08-17 18:45:10 +03:00
masked_gather_scatter_widen.ll
[SLP][COST][X86]Improve cost model for masked gather.
2021-07-08 11:53:30 -07:00
masked_gather_scatter.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
masked_gather.ll
[X86] Lower insertions into upper half of an 256-bit vector as broadcast+blend (PR50971)
2021-08-17 18:45:10 +03:00
masked_load.ll
[X86] Lower insertions into upper half of an 256-bit vector as broadcast+blend (PR50971)
2021-08-17 18:45:10 +03:00
masked_store_trunc_ssat.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
masked_store_trunc_usat.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
masked_store_trunc.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
masked_store.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
masked-iv-safe.ll
…
masked-iv-unsafe.ll
…
maskmovdqu.ll
[X86] Fix handling of maskmovdqu in X32
2021-07-15 22:56:08 +01:00
materialize.ll
[X86] make sure POP has implicit def/use of stack pointer when materializing 8-bit immediates for minsize
2020-03-30 09:25:31 -07:00
mature-mc-support.ll
…
mbp-false-cfg-break.ll
…
mcinst-avx-lowering.ll
…
mcinst-lowering.ll
…
mcu-abi.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
mem-intrin-base-reg.ll
…
mem-promote-integers.ll
…
membarrier.ll
…
memcmp-constant.ll
…
memcmp-mergeexpand.ll
[tests] Stablize tests for possible change in deref semantics
2021-07-14 13:05:43 -07:00
memcmp-minsize-x32.ll
[x86] split memcmp tests for 32/64-bit targets; NFC
2021-08-15 13:51:18 -04:00
memcmp-minsize.ll
[x86] split memcmp tests for 32/64-bit targets; NFC
2021-08-15 13:51:18 -04:00
memcmp-more-load-pairs-x32.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
memcmp-more-load-pairs.ll
[x86] split memcmp tests for 32/64-bit targets; NFC
2021-08-15 13:51:18 -04:00
memcmp-optsize-x32.ll
[x86] split memcmp tests for 32/64-bit targets; NFC
2021-08-15 13:51:18 -04:00
memcmp-optsize.ll
[x86] split memcmp tests for 32/64-bit targets; NFC
2021-08-15 13:51:18 -04:00
memcmp-pgso-x32.ll
[x86] split memcmp tests for 32/64-bit targets; NFC
2021-08-15 13:51:18 -04:00
memcmp-pgso.ll
[x86] split memcmp tests for 32/64-bit targets; NFC
2021-08-15 13:51:18 -04:00
memcmp-x32.ll
[x86] split memcmp tests for 32/64-bit targets; NFC
2021-08-15 13:51:18 -04:00
memcmp.ll
[x86] split memcmp tests for 32/64-bit targets; NFC
2021-08-15 13:51:18 -04:00
memcpy-2.ll
…
memcpy-from-string.ll
[CodeGen] Allow mempcy/memset to generate small overlapping stores.
2018-12-13 09:56:19 +00:00
memcpy-inline-fsrm.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
memcpy-inline.ll
[X86] Emit @PLT for x86-64 and keep unadorned symbols for x86-32
2020-12-05 13:17:47 -08:00
memcpy-scoped-aa.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
memcpy-struct-by-value.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
memcpy.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
mempcpy-32.ll
…
mempcpy.ll
…
memset64-on-x86-32.ll
…
memset-2.ll
…
memset-3.ll
…
memset-nonzero.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
memset-sse-stack-realignment.ll
[CodeGen][X86] Remove unused trivial check-prefixes from all CodeGen/X86 directory.
2020-11-16 09:45:55 +08:00
memset-zero.ll
…
memset.ll
…
merge_store_duplicated_loads.ll
…
merge_store.ll
[CGP] Support opaque pointers in address mode fold
2021-09-12 17:43:37 +02:00
merge-consecutive-loads-128.ll
…
merge-consecutive-loads-256.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
merge-consecutive-loads-512.ll
[DAG] Fold concat_vectors(concat_vectors(x,y),concat_vectors(a,b)) -> concat_vectors(x,y,a,b)
2021-08-16 16:06:54 +01:00
merge-consecutive-stores-i1.ll
…
merge-consecutive-stores-nt.ll
[DAG] scalarizeExtractedVectorLoad - replace getABITypeAlign with allowsMemoryAccess (PR45116)
2021-10-01 21:07:34 +01:00
merge-consecutive-stores.ll
…
merge-sp-update-lea.ll
…
merge-sp-updates-cfi.ll
…
merge-store-constants.ll
…
merge-store-partially-alias-loads.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
merge-vector-stores-scale-idx-crash.ll
…
MergeConsecutiveStores.ll
…
mfence.ll
…
midpoint-int-vec-128.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
midpoint-int-vec-256.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
midpoint-int-vec-512.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
midpoint-int.ll
…
min-legal-vector-width.ll
[X86][SSE] LowerRotate - perform modulo on the amount splat source directly.
2021-07-25 17:30:32 +01:00
mingw-alloca.ll
…
mingw-comdats-xdata.ll
…
mingw-comdats.ll
…
mingw-refptr.ll
…
misaligned-memset.ll
…
misched_phys_reg_assign_order.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
misched-aa-colored.ll
…
misched-aa-mmos.ll
…
misched-balance.ll
…
misched-code-difference-with-debug.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
misched-copy.ll
…
misched-crash.ll
…
misched-fusion.ll
…
misched-ilp.ll
…
misched-matmul.ll
…
misched-matrix.ll
…
misched-new.ll
…
mixed-ptr-sizes-i686.ll
…
mixed-ptr-sizes.ll
…
mmx-arg-passing-x86-64.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
mmx-arg-passing.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
mmx-arith.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
mmx-bitcast-fold.ll
…
mmx-bitcast.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
mmx-build-vector.ll
…
mmx-coalescing.ll
…
mmx-copy-gprs.ll
…
mmx-cvt.ll
…
mmx-fold-load.ll
…
mmx-fold-zero.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
mmx-intrinsics.ll
…
mmx-only.ll
…
mov-zero-to-xor.ll
…
movbe.ll
…
movddup-load-fold.ll
…
movdir-intrinsic-x86_64.ll
…
movdir-intrinsic-x86.ll
…
move_latch_to_loop_top.ll
…
movfs.ll
…
movgs.ll
…
movmsk-cmp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
movmsk.ll
…
movntdq-no-avx.ll
…
movpc32-check.ll
…
movtopush64.ll
…
movtopush-stack-align.ll
reland [IR] make -stack-alignment= into a module attr
2021-06-08 10:59:46 -07:00
movtopush.ll
reland [IR] make -stack-alignment= into a module attr
2021-06-08 10:59:46 -07:00
movtopush.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
ms-inline-asm-avx512.ll
…
ms-inline-asm-PR44272.ll
…
ms-inline-asm-redundant-clobber.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
ms-inline-asm.ll
…
mul64.ll
…
mul128_sext_loop.ll
…
mul128.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
mul-constant-i8.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
mul-constant-i16.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
mul-constant-i32.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
mul-constant-i64.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
mul-constant-result.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
mul-i256.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
mul-i512.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
mul-i1024.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
mul-legalize.ll
…
mul-remat.ll
…
mul-shift-reassoc.ll
[LiveIntervals] Fix repairOldRegInRange for simple def cases
2021-09-24 11:44:49 +01:00
mulfix_combine.ll
…
mulo-pow2.ll
…
muloti.ll
[X86] Disable muloti4 libcalls for x86-64.
2021-09-09 10:03:15 -07:00
mult-alt-generic-i686.ll
…
mult-alt-generic-x86_64.ll
…
mult-alt-x86.ll
…
multiple-loop-post-inc.ll
X86: Do not use llc -march in tests.
2017-08-02 00:28:10 +00:00
multiple-return-values-cross-block.ll
…
mulvi32.ll
…
mulx32.ll
…
mulx64.ll
…
musttail-fastcall.ll
…
musttail-inalloca.ll
…
musttail-indirect.ll
…
musttail-tailcc.ll
…
musttail-thiscall.ll
…
musttail-varargs.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
musttail.ll
…
mwaitx.ll
…
mxcsr-reg-usage.ll
…
named-reg-alloc.ll
…
named-reg-notareg.ll
…
named-vector-shuffle-reverse.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
narrow_op-1.ll
[DAG] ReduceLoadOpStoreWidth - replace getABITypeAlign with allowsMemoryAccess (PR45116)
2021-09-25 18:35:57 +01:00
narrow-shl-cst.ll
…
narrow-shl-load.ll
…
neg_cmp.ll
…
neg_fp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
neg-abs.ll
[X86] Add DAG combine for negation of CMOV absolute value pattern.
2021-10-16 13:31:43 -07:00
neg-of-3ops-lea.ll
…
neg-shl-add.ll
…
negate-add-zero.ll
…
negate-i1.ll
…
negate-shift.ll
…
negate.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
negative_zero.ll
X86: Do not use llc -march in tests.
2017-08-02 00:28:10 +00:00
negative-offset.ll
[test] Add explicit dso_local to constant/global variable declarations
2020-12-04 13:51:01 -08:00
negative-sin.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
negative-stride-fptosi-user.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
negative-subscript.ll
[test] Add explicit dso_local to constant/global variable declarations
2020-12-04 13:51:01 -08:00
new-remat.ll
…
newline-and-quote.ll
…
no-and8ri8.ll
…
no-cmov.ll
…
no-non-zero-debug-loc-prologue.ll
Do not emit prologue_end for line 0 locs if there is a non-zero loc present
2021-10-07 13:54:28 -07:00
no-plt-libcalls.ll
Revert "[BuildLibCalls/SimplifyLibCalls] Fix attributes on created CallInst instructions."
2021-06-24 19:24:34 -07:00
no-plt.ll
…
no-prolog-kill.ll
…
no-seh-unwind-inline-asm-codegen.ll
…
no-sse2-avg.ll
…
no-sse-win64.ll
…
no-sse-x86.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
no-stack-arg-probe.ll
…
no-unwind-inline-asm-codegen.ll
…
no-wide-load.ll
…
nobt.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
nocf_check.ll
…
nocx16.ll
…
nomerge.ll
…
nomovtopush.ll
…
non-lazy-bind.ll
…
non-unique-sections.ll
…
non-value-mem-operand.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
nonconst-static-ev.ll
…
nonconst-static-iv.ll
…
nontemporal-2.ll
…
nontemporal-3.ll
…
nontemporal-loads-2.ll
…
nontemporal-loads.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
nontemporal.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
noreturn-call-linux.ll
…
noreturn-call-win64.ll
…
noreturn-call.ll
…
norex-subreg.ll
…
nosse-error1.ll
…
nosse-varargs.ll
…
nosse-vector.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
not-and-simplify.ll
…
not-of-dec.ll
…
note-cet-property.ll
…
note-sections.ll
…
null-streamer.ll
…
O0-pipeline.ll
[CSSPGO] Set PseudoProbeInserter as a default pass.
2021-09-22 09:09:48 -07:00
objc-gc-module-flags.ll
…
oddshuffles.ll
[X86] SimplifyDemandedBits - only narrow a broadcast source if we only have one use.
2021-09-19 22:53:30 +01:00
oddsubvector.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
offset-operator.ll
[X86][AsmParser] re-introduce 'offset' operator
2019-12-30 14:35:26 -05:00
omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
opaque-constant-asm.ll
…
opt_phis2.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
opt_phis.mir
…
opt-ext-uses.ll
…
opt-pipeline.ll
[CSSPGO] Set PseudoProbeInserter as a default pass.
2021-09-22 09:09:48 -07:00
opt-shuff-tstore.ll
…
optimize-max-0.ll
…
optimize-max-1.ll
…
optimize-max-2.ll
…
optimize-max-3.ll
…
or-address.ll
…
or-branch.ll
[X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760)
2021-06-30 18:46:50 +01:00
or-lea.ll
…
or-with-overflow.ll
…
oss-fuzz-25184.ll
…
osx-private-labels.ll
MachO: don't emit L... private symbols in do_not_dead_strip sections.
2021-07-15 14:40:43 +01:00
overflow-intrinsic-optimizations.ll
[X86ISelLowering] avoid emitting libcalls to __mulodi4()
2021-09-07 10:44:54 -07:00
overflow-intrinsic-setcc-fold.ll
…
overflow.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
overflowing-iv-codegen.ll
…
overflowing-iv.ll
…
overlap-shift.ll
…
packed_struct.ll
[test] Add explicit dso_local to constant/global variable declarations
2020-12-04 13:51:01 -08:00
packss.ll
[X86] Twist shuffle mask when fold HOP(SHUFFLE(X,Y),SHUFFLE(X,Y)) -> SHUFFLE(HOP(X,Y))
2021-07-05 21:29:42 +08:00
paddus.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
palignr.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
parity-vec.ll
[X86] Enable promotion of i16 popcnt (PR52056)
2021-10-15 15:41:37 +02:00
parity.ll
[X86] Enable promotion of i16 popcnt (PR52056)
2021-10-15 15:41:37 +02:00
partial-fold32.ll
…
partial-fold64.ll
…
partial-tail-dup.ll
…
partition.ll
…
pass-three.ll
…
patchable-function-entry-ibt.ll
[AsmPrinter] Omit unique ID for __patchable_function_entries sections
2020-02-14 20:54:54 -08:00
patchable-function-entry.ll
[X86] For 32-bit targets, emit two-byte NOP when possible
2020-06-17 13:44:38 -04:00
patchable-prologue.ll
…
patchpoint-invoke.ll
Emit smaller exception tables for non-SJLJ mode.
2018-02-09 17:13:37 +00:00
patchpoint-verifiable.mir
…
patchpoint-webkit_jscc.ll
[MC] Suppress .Lcfi labels when emitting textual assembly
2017-10-10 00:57:36 +00:00
patchpoint.ll
Bias physical register immediate assignments
2018-11-14 21:11:53 +00:00
pause.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
peep-setb.ll
…
peep-test-0.ll
…
peep-test-1.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
peep-test-2.ll
…
peep-test-3.ll
…
peep-test-4.ll
…
peephole-cvt-sse.ll
…
peephole-fold-movsd.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
peephole-fold-testrr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
peephole-multiple-folds.ll
…
peephole-na-phys-copy-folding.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
peephole-recurrence.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
peephole.mir
…
personality_size.ll
…
personality.ll
…
phaddsub-extract.ll
…
phaddsub-undef.ll
…
phaddsub.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
phi-bit-propagation.ll
…
phi-immediate-factoring.ll
…
phielim-split.ll
…
phielim-undef.mir
[PHIElimination] Fix accounting for undef uses when updating LiveVariables
2021-10-11 20:22:47 +01:00
phys_subreg_coalesce-2.ll
…
phys_subreg_coalesce-3.ll
…
phys_subreg_coalesce.ll
…
phys-reg-local-regalloc.ll
…
physreg-pairs-error.ll
…
physreg-pairs.ll
…
pic_jumptable.ll
…
pic-load-remat.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pic.ll
…
pie.ll
…
pku.ll
…
pmaddubsw.ll
[X86] Fold PACK(*_EXTEND_VECTOR_INREG, UNDEF) -> *_EXTEND_VECTOR_INREG
2021-09-26 19:37:22 +01:00
pmovext.ll
…
pmovsx-inreg.ll
…
pmul.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
pmulh.ll
[X86] combineMulToPMADDWD - replace ASHR(X,16) -> LSHR(X,16)
2021-10-18 22:12:56 +01:00
pmulld.ll
…
pointer-vector.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
poison-ops.ll
…
pop-stack-cleanup-msvc.ll
…
pop-stack-cleanup.ll
…
popcnt.ll
[X86] Enable promotion of i16 popcnt (PR52056)
2021-10-15 15:41:37 +02:00
post-ra-sched-with-debug.mir
[DebugInfo][InstrRef] Correctly update DBG_PHIs during instr scheduling
2021-07-27 15:12:46 +01:00
post-ra-sched.ll
…
postalloc-coalescing.ll
…
postra-ignore-dbg-instrs.mir
…
postra-licm.ll
…
pow.75.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pow.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
powi-windows.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
powi.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
pr1462.ll
…
pr1489.ll
…
pr1505.ll
…
pr1505b.ll
…
pr2177.ll
…
pr2182.ll
…
pr2326.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr2585.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr2656.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr2659.ll
…
pr2849.ll
…
pr2924.ll
…
pr2982.ll
…
pr3154.ll
…
pr3216.ll
…
pr3241.ll
…
pr3243.ll
…
pr3244.ll
…
pr3250.ll
…
pr3317.ll
…
pr3366.ll
…
pr3457.ll
…
pr3522.ll
…
pr5145.ll
[X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760)
2021-06-30 18:46:50 +01:00
pr7882.ll
…
pr9127.ll
…
pr9517.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr9743.ll
…
pr10068.ll
…
pr10475.ll
…
pr10499.ll
…
pr10523.ll
…
pr10524.ll
…
pr10525.ll
…
pr10526.ll
…
pr11202.ll
…
pr11334.ll
…
pr11415.ll
…
pr11468.ll
reland [IR] make -stack-alignment= into a module attr
2021-06-08 10:59:46 -07:00
pr11985.ll
…
pr11998.ll
…
pr12360.ll
…
pr12889.ll
…
pr13209.ll
…
pr13220.ll
…
pr13458.ll
…
pr13577.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr13859.ll
…
pr13899.ll
…
pr14088.ll
…
pr14098.ll
…
pr14161.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr14204.ll
…
pr14314.ll
…
pr14333.ll
…
pr14562.ll
…
pr15267.ll
…
pr15296.ll
Revert "[X86] combineX86ShuffleChain(): canonicalize mask elts picking from splats"
2021-08-05 18:58:08 +02:00
pr15309.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr15705.ll
…
pr15981.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr16031.ll
[DAG] Fold select_cc setgt X, -1, C, ~C -> xor (ashr X, BW-1), C
2021-09-05 16:04:01 +01:00
pr16360.ll
…
pr16807.ll
…
pr17546.ll
…
pr17631.ll
…
pr17764.ll
…
pr18014.ll
…
pr18054.ll
…
pr18162.ll
…
pr18344.ll
…
pr18846.ll
…
pr19049.ll
…
pr20011.ll
…
pr20012.ll
…
pr20020.ll
…
pr20088.ll
…
pr21099.ll
…
pr21792.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr22019.ll
…
pr22103.ll
…
pr22338.ll
…
pr22473.ll
…
pr22774.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr22970.ll
…
pr23103.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr23246.ll
…
pr23273.ll
…
pr23603.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr23664.ll
…
pr24139.ll
…
pr24374.ll
…
pr24602.ll
…
pr25725.ll
[NFC] Added testcase for PR25725
2021-09-17 15:48:55 +02:00
pr25828.ll
…
pr26350.ll
…
pr26625.ll
…
pr26652.ll
…
pr26757.ll
…
pr26835.ll
…
pr26870.ll
…
pr27071.ll
…
pr27202.ll
…
pr27501.ll
…
pr27591.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr27681.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
pr28129.ll
…
pr28173.ll
…
pr28444.ll
…
pr28472.ll
…
pr28489.ll
…
pr28515.ll
…
pr28560.ll
…
pr28824.ll
…
pr29010.ll
…
pr29022.ll
…
pr29061.ll
…
pr29112.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr29170.ll
…
pr29222.ll
…
pr30284.ll
…
pr30290.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr30430.ll
…
pr30511.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr30562.ll
…
pr30813.ll
…
pr30821.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
pr31045.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr31088.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
pr31143.ll
…
pr31242.ll
…
pr31271.ll
…
pr31323.ll
…
pr31593.ll
…
pr31773.ll
…
pr31956.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr32108.ll
…
pr32241.ll
…
pr32256.ll
…
pr32278.ll
…
pr32282.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr32284.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
pr32329.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
pr32340.ll
…
pr32345.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr32368.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr32420.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr32451.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr32484.ll
…
pr32515.ll
…
pr32588.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr32610.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
pr32659.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr32907.ll
…
pr33010.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr33290.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr33349.ll
…
pr33396.ll
…
pr33715.ll
…
pr33747.ll
…
pr33828.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr33954.ll
…
pr33960.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr34080-2.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
pr34080.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr34088.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr34137.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr34139.ll
…
pr34149.ll
…
pr34177.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr34271-1.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr34271.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr34292.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr34381.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr34397.ll
…
pr34421.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr34592.ll
[DAG] DAGCombiner::visitVECTOR_SHUFFLE - recognise INSERT_SUBVECTOR patterns
2021-08-05 15:40:48 +01:00
pr34605.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr34629.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr34634.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr34653.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr34657.ll
…
pr34855.ll
…
pr35272.ll
…
pr35316.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr35399.ll
…
pr35443.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr35636.ll
…
pr35761.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr35763.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr35765.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr35918.ll
…
pr35972.ll
…
pr35982.ll
[DAG] CombineConsecutiveLoads - replace getABITypeAlign with allowsMemoryAccess (PR45116)
2021-08-24 12:31:22 +01:00
pr36199.ll
…
pr36274.ll
…
pr36312.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr36553.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr36602.ll
…
pr36865.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr37025.ll
[X86] Add PR37025 test coverage
2021-07-27 12:09:25 +01:00
pr37063.ll
…
pr37264.ll
…
pr37359.ll
…
pr37499.ll
…
pr37820.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr37826.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr37879.ll
…
pr37916.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr38038.ll
…
pr38185.ll
…
pr38217.ll
…
pr38533.ll
…
pr38539.ll
…
pr38639.ll
…
pr38738.ll
…
pr38743.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr38762.ll
…
pr38763.ll
…
pr38795.ll
…
pr38803.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr38819.ll
…
pr38865-2.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr38865-3.ll
…
pr38865.ll
…
pr38952.mir
…
pr39098.ll
…
pr39243.ll
…
pr39666.ll
…
pr39733.ll
…
pr39896.ll
…
pr39926.ll
…
pr40090.ll
…
pr40289-64bit.ll
…
pr40289.ll
…
pr40529.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr40539.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr40631_deadstore_elision.ll
…
pr40730.ll
…
pr40737.ll
…
pr40811.ll
…
pr40891.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr40994.ll
…
pr41619.ll
Fix the default alignment of i1 vectors.
2021-07-31 14:09:59 -07:00
pr41678.ll
…
pr41748.ll
…
pr42064.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr42452.ll
…
pr42565.ll
…
pr42616.ll
…
pr42727.ll
…
pr42870.ll
…
pr42905.ll
…
pr42909.ll
…
pr42992.ll
…
pr42998.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
pr43157.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr43507.ll
…
pr43509.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr43529.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr43575.ll
…
pr43820.ll
[SelectionDAG] Optimize bitreverse expansion to minimize the number of mask constants.
2021-08-26 09:33:24 -07:00
pr43866.ll
…
pr43952.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr44140.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr44396.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr44412.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr44749.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr44812.ll
…
pr44976.ll
…
pr45067.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr45378.ll
…
pr45443.ll
…
pr45563-2.ll
…
pr45563.ll
…
pr45833.ll
…
pr45995-2.ll
[X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760)
2021-06-30 18:46:50 +01:00
pr45995.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr46004.ll
…
pr46189.ll
…
pr46315.ll
[X86] Add PR46315 test case
2021-08-16 13:13:56 +01:00
pr46455.ll
…
pr46527.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
pr46532.ll
…
pr46585.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr46820.ll
…
pr46827.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
pr46877.ll
…
pr47000.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr47024.ll
…
pr47299.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr47482.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr47517.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr47874.ll
…
pr48064.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
pr48215.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr48458.ll
…
pr48727.ll
…
pr48888.ll
…
pr49028.ll
…
pr49076.ll
…
pr49087.ll
…
pr49162.ll
…
pr49393.ll
…
pr49451.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr49466.ll
…
pr49467.ll
…
pr49587.ll
…
pr50254.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pr50374.ll
[X86][SSE] combineScalarToVector - only reuse broadcasts for scalar_to_vector if the source operands scalar types match
2021-06-02 22:05:40 +01:00
pr50431.ll
…
pr50609.ll
[DAG] foldShuffleOfConcatUndefs - ensure shuffles of upper (undef) subvector elements is undef (PR50609)
2021-06-08 15:49:41 +01:00
pr50709.ll
[X86] Use EVT::getVectorVT instead of changeVectorElementType in reduceVMULWidth.
2021-06-14 22:07:04 -07:00
pr50782.ll
[X86] Teach X86FloatingPoint's handleCall to only erase the FP stack if there is a regmask operand that clobbers the FP stack.
2021-07-12 10:15:38 -07:00
pr50823.ll
[X86] Twist shuffle mask when fold HOP(SHUFFLE(X,Y),SHUFFLE(X,Y)) -> SHUFFLE(HOP(X,Y))
2021-07-05 21:29:42 +08:00
pr50907.ll
[X86] Tighten up some inline assembly constraint handling.
2021-06-26 22:57:22 -07:00
pr51175.ll
[X86] Fix a bug in TEST with immediate creation
2021-07-23 09:03:53 -07:00
pr51281.ll
[X86][AVX] Extract SUBV_BROADCAST constant bits from just the lower subvector range (PR51281)
2021-08-06 11:21:31 +01:00
pr51371.ll
[X86] Teach shouldSinkOperands to recognize pmuldq/pmuludq patterns.
2021-08-07 08:45:56 -07:00
pr51615.ll
[Codegen][X86] EltsFromConsecutiveLoads(): if only have AVX1, ensure that the "load" is actually foldable (PR51615)
2021-08-27 20:26:53 +03:00
pr51878_computeAliasing.ll
[SelectionDAG] Assume that a GlobalAlias may alias other global values
2021-10-05 12:15:55 +02:00
pr51903.mir
Recommit "[X86] Clear kill flags when rewriting SETCC uses in flag copy lowering."
2021-09-21 14:59:25 -07:00
PR34565.ll
…
PR37310.mir
…
PR40322.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pre-coalesce-2.ll
…
pre-coalesce.ll
…
pre-coalesce.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
pre-ra-sched.ll
…
preallocated-nocall.ll
…
preallocated-x64.ll
…
preallocated.ll
…
prefer-avx256-lzcnt.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
prefer-avx256-mask-extend.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
prefer-avx256-mask-shuffle.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
prefer-avx256-mulo.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
prefer-avx256-popcnt.ll
…
prefer-avx256-shift.ll
…
prefer-avx256-trunc.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
prefer-avx256-wide-mul.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
prefetch.ll
[X86] Don't imply -mprfchw when -m3dnow is specified. Enable prefetchw in the backend with 3dnow feature.
2020-06-25 12:46:52 -07:00
prefixdata.ll
Ensure that prefix data is preserved with subsections-via-symbols
2017-03-15 04:18:16 +00:00
preserve_allcc64.ll
…
preserve_mostcc64.ll
…
private-2.ll
…
private.ll
…
probe-stack-x32.ll
…
prolog-push-seq.ll
…
prologepilog_deref_size.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
prologue-epilogue-remarks.mir
…
prologuedata.ll
…
promote-assert-zext.ll
…
promote-cmp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
promote-i16.ll
…
promote-trunc.ll
…
promote-vec3.ll
…
promote.ll
…
ps4-noreturn.ll
…
ps4-ssp-nop.ll
…
psadbw.ll
[X86] SimplifyDemandedVectorEltsForTargetNode - add PSADBW handling
2021-09-16 11:28:31 +01:00
pseudo_cmov_lower1.ll
…
pseudo_cmov_lower2.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
pseudo_cmov_lower-fp16.ll
[X86] AVX512FP16 instructions enabling 2/6
2021-08-15 08:56:33 +08:00
pseudo_cmov_lower.ll
…
pshufb-mask-comments.ll
…
pshufd-combine-crash.ll
…
psubus.ll
[x86] add special-case lowering for usubsat for AVX512
2021-10-20 16:41:13 -04:00
ptest.ll
…
ptr-rotate.ll
…
ptrtoint-constexpr.ll
…
ptrtoint-narrow.ll
…
ptwrite32-intrinsic.ll
…
ptwrite64-intrinsic.ll
…
pull-binop-through-shift.ll
[CodeGen][X86] Remove unused trivial check-prefixes from all CodeGen/X86 directory.
2020-11-16 09:45:55 +08:00
pull-conditional-binop-through-shift.ll
[CodeGen][X86] Remove unused trivial check-prefixes from all CodeGen/X86 directory.
2020-11-16 09:45:55 +08:00
push-cfi-debug.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
push-cfi-obj.ll
…
push-cfi.ll
…
ragreedy-bug.ll
…
ragreedy-hoist-spill.ll
Revert "Allow rematerialization of virtual reg uses"
2021-09-24 10:26:11 -07:00
ragreedy-last-chance-recoloring.ll
…
rd-mod-wr-eflags.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
rdpid.ll
[CodeGen][X86] Remove unused trivial check-prefixes from all CodeGen/X86 directory.
2020-11-16 09:45:55 +08:00
rdpmc.ll
…
rdrand-x86_64.ll
…
rdrand.ll
…
rdseed-x86_64.ll
…
rdseed.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
rdtsc-upgrade.ll
…
rdtsc.ll
…
read-fp-no-frame-pointer.ll
…
recip-fastmath2.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
recip-fastmath.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
recip-pic.ll
…
red-zone2.ll
…
red-zone.ll
…
reduce-trunc-shl.ll
…
regalloc-advanced-split-cost.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
regalloc-copy-hints.mir
…
regalloc-fast-missing-live-out-spill.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regalloc-reconcile-broken-hints.ll
…
regalloc-spill-at-ehpad.ll
…
regalloc-tight-invoke.ll
…
regcall-no-plt.ll
…
reghinting.ll
…
regparm.ll
…
regpressure.ll
…
relocimm-small-model.ll
…
relptr-rodata.ll
[llvm][IR] Do not place constants with static relocations in a mergeable section
2021-02-18 15:39:00 -08:00
rem_crash.ll
…
rem.ll
…
remarks-section.ll
…
remat-constant.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
remat-fold-load.ll
…
remat-mov-0.ll
…
remat-phys-dead.ll
…
remat-scalar-zero.ll
…
replace_unsupported_masked_mem_intrin.ll
…
replace-load-and-with-bzhi.ll
…
ret-addr.ll
…
ret-i64-0.ll
…
ret-mmx.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
retpoline-external.ll
…
retpoline-regparm.ll
…
retpoline.ll
…
return_zeroext_i2.ll
…
return-ext.ll
…
returned-trunc-tail-calls.ll
…
rev16.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
reverse_branches.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
rip-rel-address.ll
…
rip-rel-lea.ll
…
rodata-relocs.ll
…
rot16.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
rot32.ll
…
rot64.ll
…
rotate2.ll
…
rotate4.ll
…
rotate_vec.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
rotate-extract-vector.ll
[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
2021-06-11 16:49:12 +01:00
rotate-extract.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
rotate-multi.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
rotate.ll
…
rounding-ops.ll
…
rrlist-livereg-corrutpion.ll
…
rtm.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sad_variations.ll
[X86] SimplifyDemandedVectorEltsForTargetNode - add PSADBW handling
2021-09-16 11:28:31 +01:00
sad.ll
[X86] SimplifyDemandedVectorEltsForTargetNode - add PSADBW handling
2021-09-16 11:28:31 +01:00
sadd_sat_plus.ll
[ISel] Expand saddsat and ssubsat via asr and xor
2021-08-19 16:08:07 +01:00
sadd_sat_vec.ll
[ISel] Expand saddsat and ssubsat via asr and xor
2021-08-19 16:08:07 +01:00
sadd_sat.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
saddo-redundant-add.ll
…
safestack_inline.ll
…
safestack_ssp.ll
…
safestack.ll
…
sandybridge-loads.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sar_fold64.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sar_fold.ll
…
sat-add.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
sbb.ll
…
scalar_sse_minmax.ll
…
scalar_widen_div.ll
…
scalar-extract.ll
…
scalar-fp-to-i32.ll
[X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction.
2021-07-14 12:03:49 +01:00
scalar-fp-to-i64.ll
[X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction.
2021-07-14 12:03:49 +01:00
scalar-int-to-fp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
scalar-min-max-fill-operand.ll
…
scalarize-bitcast.ll
…
scalarize-fp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
scatter-schedule.ll
…
scavenger.mir
…
scev-interchange.ll
…
scheduler-backtracking.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
sdiv_fix_sat.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
sdiv_fix.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
sdiv-exact.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sdiv-pow2.ll
…
section_mergeable_size.ll
…
segmented-stacks-dynamic.ll
…
segmented-stacks-standalone.ll
…
segmented-stacks.ll
…
seh-catch-all-win32.ll
…
seh-catch-all.ll
…
seh-catchpad.ll
Fix SEH table addresses for Windows
2021-08-20 22:32:12 +03:00
seh-except-finally.ll
Fix SEH table addresses for Windows
2021-08-20 22:32:12 +03:00
seh-except-restore.ll
…
seh-exception-code.ll
…
seh-filter-no-personality.ll
…
seh-finally.ll
Fix SEH table addresses for Windows
2021-08-20 22:32:12 +03:00
seh-localaddress.ll
…
seh-no-invokes.ll
…
seh-safe-div-win32.ll
…
seh-safe-div.ll
Fix SEH table addresses for Windows
2021-08-20 22:32:12 +03:00
seh-stack-realign.ll
[EH] Rename llvm.x86.seh.recoverfp intrinsic to llvm.eh.recoverfp
2019-01-16 00:37:13 +00:00
seh-unwind-inline-asm-codegen.ll
…
select_const.ll
[X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760)
2021-06-30 18:46:50 +01:00
select_meta.ll
Remove "Rewrite Symbols" from codegen pipeline
2021-05-31 08:32:36 -07:00
select-1-or-neg1.ll
…
select-constant-xor.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
select-ext.ll
[DAGCombiner] Transform (zext (select c, load1, load2)) -> (select c, zextload1, zextload2)
2021-02-18 13:15:20 -08:00
select-mmx.ll
…
select-of-fp-constants.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
select-of-half-constants.ll
[X86] Modify the commuted load isel pattern for VCMPSHZrm to match VCMPSSZrm/VCMPSDZrm.
2021-08-15 11:43:56 -07:00
select-prof-codegen.ll
[DAGCombiner] Fold BRCOND(FREEZE(COND)) to BRCOND(COND)
2021-01-13 09:36:52 +09:00
select-sra.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
select-testb-volatile-load.ll
…
select-with-and-or.ll
…
select.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
selectcc-to-shiftand.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
selectiondag-crash.ll
…
selectiondag-cse.ll
…
selectiondag-debug-loc.ll
…
selectiondag-dominator.ll
…
selectiondag-order.ll
…
semantic-interposition-asm.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
serialize-intrinsic.ll
…
setcc-combine.ll
…
setcc-freeze.ll
[DAGCombiner] Fold SETCC(FREEZE(x),const) to FREEZE(SETCC(x,const)) if SETCC is used by BRCOND
2021-07-28 09:22:15 +09:00
setcc-logic.ll
[X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760)
2021-06-30 18:46:50 +01:00
setcc-lowering.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
setcc-narrowing.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
setcc-wide-types.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
setcc.ll
[X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760)
2021-06-30 18:46:50 +01:00
setjmp-spills.ll
…
setoeq.ll
…
setuge.ll
…
sext-i1.ll
…
sext-load.ll
…
sext-ret-val.ll
…
sext-setcc-self.ll
…
sext-subreg.ll
…
sext-trunc.ll
…
sext-vsetcc.ll
[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
2021-06-11 16:49:12 +01:00
sha.ll
…
shadow-stack.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
shift_minsize.ll
[SelectionDAG] Fix shift libcall ABI mismatch in shift-amount argument
2021-10-08 09:57:57 +08:00
shift-amount-mod.ll
…
shift-and-x86_64.ll
…
shift-and.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
shift-avx2-crash.ll
…
shift-bmi2.ll
…
shift-by-signext.ll
…
shift-coalesce.ll
…
shift-codegen.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
shift-combine-crash.ll
…
shift-combine.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
shift-double-x86_64.ll
…
shift-double.ll
[DAGCombiner][X86] Don't peek through ANDs on the shift amount in matchRotateSub when called from MatchFunnelPosNeg.
2021-02-28 12:58:00 -08:00
shift-folding.ll
…
shift-i128.ll
…
shift-i256.ll
…
shift-logic.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
shift-mask.ll
…
shift-one.ll
…
shift-pair.ll
…
shift-parts.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
shift-pcmp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
shl_elim.ll
…
shl_undef.ll
…
shl-anyext.ll
…
shl-crash-on-legalize.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
shl-i64.ll
…
shrink_vmul_sse.ll
…
shrink_vmul.ll
[X86] SimplifyDemandedVectorEltsForTargetNode - simplify PMADDWD for known zero elements
2021-10-04 14:36:45 +01:00
shrink_wrap_dbg_value.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
shrink-compare-pgso.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
shrink-compare.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
shrink-const.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
shrink-fp-const1.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
shrink-fp-const2.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
shrink-wrap-chkstk-x86_64.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
shrink-wrap-chkstk.ll
…
shrink-wrapping-vla.ll
…
shrinkwrap-callbr.ll
…
shrinkwrap-hang.ll
…
shuffle-combine-crash-2.ll
…
shuffle-combine-crash-3.ll
…
shuffle-combine-crash.ll
…
shuffle-extract-subvector.ll
…
shuffle-of-insert.ll
…
shuffle-of-splat-multiuses.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
shuffle-strided-with-offset-128.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
shuffle-strided-with-offset-256.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
shuffle-strided-with-offset-512.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
shuffle-vs-trunc-128.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
shuffle-vs-trunc-256.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
shuffle-vs-trunc-512.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
sibcall-2.ll
…
sibcall-3.ll
…
sibcall-4.ll
…
sibcall-5.ll
…
sibcall-6.ll
…
sibcall-byval.ll
…
sibcall-win64.ll
…
sibcall.ll
[X86] pr51000 in-register struct return tailcalling
2021-08-25 10:15:50 -07:00
signbit-shift.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
signed-truncation-check.ll
…
simple-register-allocation-read-undef.mir
…
simple-zext.ll
…
sincos-opt.ll
…
sincos.ll
…
sink-addsub-of-const.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sink-blockfreq.ll
…
sink-gep-before-mem-inst.ll
…
sink-hoist.ll
…
sink-local-value.ll
…
sink-out-of-loop.ll
…
sitofp.ll
…
sjlj-baseptr.ll
…
sjlj-eh-musttail.ll
[SjLj] Insert UnregisterFn before musttail call
2021-06-23 15:33:55 -07:00
sjlj-eh.ll
…
sjlj-shadow-stack-liveness.mir
…
sjlj-unwind-inline-asm-codegen.ll
…
sjlj.ll
…
slow-incdec.ll
…
slow-pmulld.ll
[X86] Add tests for enabling slow-mulld on AVX2 targets
2021-10-04 11:24:05 +01:00
slow-unaligned-mem.ll
…
small-byval-memcpy.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
smax.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
smin.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
smul_fix_sat_constants.ll
[SelectionDAG] Fix miscompile bugs related to smul.fix.sat with scale zero
2021-08-30 22:08:26 +02:00
smul_fix_sat.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
smul_fix.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
smul-with-overflow.ll
…
smulo-128-legalisation-lowering.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
soft-fp-legal-in-HW-reg.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
soft-fp.ll
…
soft-sitofp.ll
…
speculative-execution-side-effect-suppression.ll
…
speculative-load-hardening-call-and-ret.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
speculative-load-hardening-gather.ll
…
speculative-load-hardening-indirect.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
speculative-load-hardening-no-spill.ll
…
speculative-load-hardening.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
splat-const.ll
…
splat-for-size.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
split-eh-lpad-edges.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
split-extend-vector-inreg.ll
…
split-store.ll
[DAGCombiner] Combine OR as ADD when no common bits are set
2019-04-23 10:01:08 +00:00
split-vector-bitcast.ll
[X86][SSE] getV4X86ShuffleImm8 - canonicalize broadcast masks
2020-07-29 11:32:44 +01:00
split-vector-rem.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sqrt-fastmath-mir.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
sqrt-fastmath-tune.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
sqrt-fastmath.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
sqrt-partial.ll
…
sqrt.ll
…
srem-lkk.ll
…
srem-seteq-illegal-types.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
srem-seteq-optsize.ll
…
srem-seteq-vec-nonsplat.ll
[TLI] prepareSREMEqFold(): use correct VT for the final VSELECT (PR51133)
2021-07-19 16:44:00 +03:00
srem-seteq-vec-splat.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
srem-seteq.ll
[X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760)
2021-06-30 18:46:50 +01:00
srem-vector-lkk.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sret-implicit.ll
…
sse1-fcopysign.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sse1.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sse2-intrinsics-canonical.ll
…
sse2-intrinsics-fast-isel-x86_64.ll
…
sse2-intrinsics-fast-isel.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
sse2-intrinsics-x86_64-upgrade.ll
…
sse2-intrinsics-x86_64.ll
…
sse2-intrinsics-x86-upgrade.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sse2-intrinsics-x86.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sse2-vector-shifts.ll
…
sse2.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sse3-avx-addsub-2.ll
…
sse3-avx-addsub.ll
…
sse3-intrinsics-fast-isel.ll
…
sse3-intrinsics-x86.ll
…
sse3.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sse4a-intrinsics-fast-isel.ll
…
sse4a-upgrade.ll
…
sse4a.ll
…
sse41-intrinsics-fast-isel.ll
…
sse41-intrinsics-x86-upgrade.ll
…
sse41-intrinsics-x86.ll
[X86] Remove Commutable flag from mpsadbw intrinsics.
2021-09-19 13:22:22 -07:00
sse41-pmovxrm.ll
…
sse41.ll
[X86][TLI] SimplifyDemandedVectorEltsForTargetNode(): don't break apart broadcasts from which not just the 0'th elt is demanded
2021-09-19 17:38:32 +03:00
sse42-intrinsics-fast-isel.ll
[X86] Add CRC32 feature.
2021-09-06 17:24:30 +08:00
sse42-intrinsics-x86.ll
[X86] Add CRC32 feature.
2021-09-06 17:24:30 +08:00
sse_partial_update.ll
…
sse_reload_fold.ll
…
sse-align-0.ll
…
sse-align-1.ll
…
sse-align-2.ll
…
sse-align-3.ll
…
sse-align-4.ll
…
sse-align-5.ll
…
sse-align-6.ll
…
sse-align-7.ll
…
sse-align-8.ll
…
sse-align-9.ll
…
sse-align-10.ll
…
sse-align-11.ll
…
sse-align-12.ll
…
sse-commute.ll
…
sse-cvttp2si.ll
…
sse-domains.ll
…
sse-fcopysign.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sse-fsignum.ll
…
sse-insertelt-from-mem.ll
[NFC][Codegen][X86] Improve test coverage for insertions into XMM vector
2021-07-25 21:08:03 +03:00
sse-insertelt.ll
[NFC][Codegen][X86] Improve test coverage for insertions into XMM vector
2021-07-25 21:08:03 +03:00
sse-intel-ocl.ll
…
sse-intrinsics-fast-isel-x86_64.ll
…
sse-intrinsics-fast-isel.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
sse-intrinsics-x86_64-upgrade.ll
…
sse-intrinsics-x86_64.ll
…
sse-intrinsics-x86-upgrade.ll
…
sse-intrinsics-x86.ll
…
sse-load-ret.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sse-minmax.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
sse-only.ll
…
sse-regcall.ll
…
sse-scalar-fp-arith-unary.ll
…
sse-scalar-fp-arith.ll
…
sse-unaligned-mem-feature.ll
…
sse-varargs.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sshl_sat_vec.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
sshl_sat.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
ssp-data-layout.ll
…
ssp-guard-spill.ll
…
ssse3-intrinsics-fast-isel.ll
…
ssse3-intrinsics-x86-upgrade.ll
…
ssse3-intrinsics-x86.ll
…
ssub_sat_plus.ll
[ISel] Expand saddsat and ssubsat via asr and xor
2021-08-19 16:08:07 +01:00
ssub_sat_vec.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
ssub_sat.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
stack_guard_remat.ll
…
stack-align2.ll
Default stack alignment of x86 NaCl to 16 bytes
2021-05-18 15:16:59 -07:00
stack-align-memcpy.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
stack-align.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
stack-clash-dynamic-alloca.ll
…
stack-clash-large-large-align.ll
…
stack-clash-large.ll
[X86] Don't clobber EBX in stackprobes
2021-09-07 15:00:44 -04:00
stack-clash-medium-natural-probes-mutliple-objects.ll
[X86] add dwarf annotation for inline stack probe
2021-04-01 00:32:50 +03:00
stack-clash-medium-natural-probes.ll
…
stack-clash-medium.ll
[X86] add dwarf annotation for inline stack probe
2021-04-01 00:32:50 +03:00
stack-clash-small-alloc-medium-align.ll
[X86, NFC] Update stack-clash tests using the automated tooling
2021-03-19 14:01:55 +02:00
stack-clash-small-large-align.ll
…
stack-clash-small.ll
[X86, NFC] Update stack-clash tests using the automated tooling
2021-03-19 14:01:55 +02:00
stack-clash-unknown-call.ll
[X86] add dwarf annotation for inline stack probe
2021-04-01 00:32:50 +03:00
stack-folding-3dnow.ll
…
stack-folding-adx-x86_64.ll
…
stack-folding-adx.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
stack-folding-avx512bf16.ll
…
stack-folding-avx512vp2intersect.ll
…
stack-folding-bmi2.ll
[X86] Automatically generate stack folding tests. NFC
2019-08-25 20:48:14 +00:00
stack-folding-bmi2.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
stack-folding-bmi.ll
[X86] Automatically generate stack folding tests. NFC
2019-08-25 20:48:14 +00:00
stack-folding-fp-avx1.ll
…
stack-folding-fp-avx512.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
stack-folding-fp-avx512fp16-fma.ll
[X86] AVX512FP16 instructions enabling 5/6
2021-08-24 09:07:19 +08:00
stack-folding-fp-avx512fp16.ll
[X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands.
2021-09-23 11:02:48 +08:00
stack-folding-fp-avx512fp16vl-fma.ll
[X86] AVX512FP16 instructions enabling 5/6
2021-08-24 09:07:19 +08:00
stack-folding-fp-avx512fp16vl.ll
[X86][FP16] Change the order of the operands in complex FMA intrinsics to allow swap between the mul operands.
2021-09-23 11:02:48 +08:00
stack-folding-fp-avx512vl.ll
…
stack-folding-fp-nofpexcept.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
stack-folding-fp-sse42.ll
…
stack-folding-int-avx1.ll
…
stack-folding-int-avx2.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
stack-folding-int-avx512.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
stack-folding-int-avx512vl.ll
…
stack-folding-int-avx512vnni.ll
…
stack-folding-int-avxvnni.ll
…
stack-folding-int-sse42.ll
[X86] Add CRC32 feature.
2021-09-06 17:24:30 +08:00
stack-folding-lwp.ll
[X86] Automatically generate stack folding tests. NFC
2019-08-25 20:48:14 +00:00
stack-folding-mmx.ll
…
stack-folding-sha.ll
[X86] Automatically generate stack folding tests. NFC
2019-08-25 20:48:14 +00:00
stack-folding-tbm.ll
…
stack-folding-x86_64.ll
…
stack-folding-xop.ll
…
stack-guard-memloc-vararg.ll
…
stack-guard-oob.ll
…
stack-probe-red-zone.ll
…
stack-probe-size.ll
…
stack-probes.ll
…
stack-protector-2.ll
[Inline] prevent inlining on stack protector mismatch
2020-12-02 11:00:16 -08:00
stack-protector-3.ll
fix up test from D102742
2021-05-24 12:09:02 -07:00
stack-protector-dbginfo.ll
[DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.
2018-05-09 02:40:45 +00:00
stack-protector-msvc.ll
Reapply "RegAllocFast: Rewrite and improve"
2020-09-30 10:35:25 -04:00
stack-protector-remarks.ll
…
stack-protector-strong-macho-win32-xor.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
stack-protector-target.ll
…
stack-protector-vreg-to-vreg-copy.ll
…
stack-protector-weight.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
stack-protector.ll
[SSP] [1/3] Revert "StackProtector: Use PointerMayBeCaptured"
2019-09-30 15:01:35 +00:00
stack-size-section-function-sections.ll
[MC] Set the unique id of .stack_sizes to the associated .text section's
2020-11-26 09:13:09 -08:00
stack-size-section.ll
[AsmPrinter] Omit unique ID for .stack_sizes
2020-02-14 21:25:06 -08:00
stack-update-frame-opcode.ll
…
StackColoring-dbg-invariance.mir
[StackColoring] Fix a debug invariance problem
2021-09-14 19:21:56 +02:00
StackColoring-dbg.ll
…
StackColoring-use-between-allocas.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
StackColoring.ll
…
stackguard-internal.ll
…
stackmap-fast-isel.ll
…
stackmap-frame-setup.ll
…
stackmap-large-constants.ll
…
stackmap-large-location-size.ll
Migrate last batch of tests to gc-live bundle format
2020-06-26 10:28:27 -07:00
stackmap-liveness.ll
…
stackmap-nops.ll
[X86] Adjust nop emission by compiler to consider target decode limitations
2020-01-11 08:45:17 -08:00
stackmap-shadow-optimization.ll
…
stackmap.ll
…
stackpointer.ll
…
statepoint-allocas.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
statepoint-call-lowering.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
statepoint-deopt-lowering.ll
…
statepoint-duplicates-export.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
statepoint-far-call.ll
…
statepoint-fastregalloc.mir
…
statepoint-fixup-call.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
statepoint-fixup-copy-prop-neg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
statepoint-fixup-invoke.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
statepoint-fixup-shared-ehpad.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
statepoint-fixup-undef-def.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
statepoint-fixup-undef.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
statepoint-forward.ll
…
statepoint-gc-live.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
statepoint-gctransition-call-lowering.ll
…
statepoint-invoke-ra-enter-at-end.mir
[X86] AVX512FP16 instructions enabling 1/6
2021-08-10 12:46:01 +08:00
statepoint-invoke-ra-hoist-copies.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
statepoint-invoke-ra-inline-spiller.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
statepoint-invoke-ra-remove-back-copies.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
statepoint-invoke-ra.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
statepoint-invoke.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
statepoint-live-in-remat.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
statepoint-live-in.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
statepoint-no-extra-const.ll
…
statepoint-no-realign-stack.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
statepoint-ra-no-ls.ll
…
statepoint-ra.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
statepoint-regs.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
statepoint-spill-lowering.ll
…
statepoint-spill-slot-size-promotion.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
statepoint-stack-usage.ll
[Statepoints] Change statepoint machine instr format to better suit VReg lowering.
2020-10-06 17:40:29 +07:00
statepoint-stackmap-format.ll
OpaquePtr: Bulk update tests to use typed byval
2020-11-20 14:00:46 -05:00
statepoint-stackmap-size.ll
Migrate last batch of tests to gc-live bundle format
2020-06-26 10:28:27 -07:00
statepoint-two-results.ll
…
statepoint-uniqueing.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
statepoint-vector-bad-spill.ll
…
statepoint-vector.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
statepoint-vreg-details.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
statepoint-vreg-folding.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
statepoint-vreg-invoke.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
statepoint-vreg-unlimited-tied-opnds.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
statepoint-vreg.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
statepoint-vreg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
stdarg.ll
…
stdcall-notailcall.ll
…
stdcall.ll
[Mangler] Calculate the argument list byte count suffix correctly when returning large values
2021-09-29 11:42:28 -07:00
store_op_load_fold2.ll
…
store_op_load_fold.ll
[X86] Regenerate store_op_load_fold.ll test checks
2021-08-19 12:42:09 +01:00
store-empty-member.ll
…
store-fp-constant.ll
…
store-global-address.ll
…
store-narrow.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
store-zero-and-minus-one.ll
…
stores-merging.ll
[SDAG] fix miscompile from merging stores of different sizes
2021-06-09 09:51:39 -04:00
storetrunc-fp.ll
…
strict-fadd-combines.ll
[X86] Add tests from D93707 for fsub_strict(x,fneg(y)) -> fadd_strict(x,y) folds.
2021-07-10 15:08:58 +01:00
strict-fsub-combines.ll
[X86] Add tests from D93707 for fsub_strict(x,fneg(y)) -> fadd_strict(x,y) folds.
2021-07-10 15:08:58 +01:00
stride-nine-with-base-reg.ll
…
stride-reuse.ll
…
sttni.ll
…
sub-of-bias.ll
…
sub-of-not.ll
…
sub-with-overflow.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
sub.ll
…
subcarry.ll
…
subreg-to-reg-0.ll
…
subreg-to-reg-1.ll
…
subreg-to-reg-2.ll
…
subreg-to-reg-3.ll
…
subreg-to-reg-4.ll
…
subreg-to-reg-6.ll
…
subvector-broadcast.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
sunkaddr-ext.ll
…
swap.ll
…
swift-async-reg-win64.ll
X86: pass swift_async context in R14 on Win64
2021-06-14 11:02:21 -07:00
swift-async-reg.ll
…
swift-async-win64.ll
X86: balance the frame prologue and epilogue on Win64
2021-06-15 20:13:52 -07:00
swift-async.ll
SwiftAsync: use runtime-provided flag for extended frame if back-deploying
2021-09-13 13:54:46 +01:00
swift-dynamic-async-frame.ll
Add a command-line flag to control the Swift extended async frame info.
2021-09-16 06:57:45 -07:00
swift-error.ll
…
swift-return.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
swiftcc.ll
…
swifterror.ll
…
swiftself-win64.ll
…
swiftself.ll
…
swifttail-async-i386.ll
…
swifttail-async-win64.ll
X86: balance the frame prologue and epilogue on Win64
2021-06-15 20:13:52 -07:00
swifttail-async.ll
…
swifttail-realign.ll
X86: add test for realignment fix committed earlier.
2021-08-04 12:10:20 +01:00
swifttail-return.ll
…
switch-bit-test-unreachable-default.ll
[ISEL][BitTestBlock] omit additional bit test when default destination is unreachable
2021-09-08 11:03:47 -07:00
switch-bt.ll
…
switch-crit-edge-constant.ll
…
switch-default-only.ll
…
switch-density.ll
[PGO][PGSO] Enable size optimizations in code gen / target passes for cold code.
2019-12-13 11:01:19 -08:00
switch-edge-weight.ll
…
switch-jump-table.ll
…
switch-lower-peel-top-case.ll
…
switch-or.ll
…
switch-order-weight.ll
…
switch-zextload.ll
…
switch.ll
[test] Make bt_order_by_weight in switch.ll more robust
2020-10-28 12:56:23 -07:00
SwitchLowering.ll
[ISEL][BitTestBlock] omit additional bit test when default destination is unreachable
2021-09-08 11:03:47 -07:00
swizzle-2.ll
…
swizzle-avx2.ll
…
SwizzleShuff.ll
…
symbol-redefinition.ll
…
system-intrinsics-64-xsave.ll
…
system-intrinsics-64-xsavec.ll
…
system-intrinsics-64-xsaveopt.ll
…
system-intrinsics-64-xsaves.ll
…
system-intrinsics-64.ll
…
system-intrinsics-xgetbv.ll
…
system-intrinsics-xsave.ll
…
system-intrinsics-xsavec.ll
…
system-intrinsics-xsaveopt.ll
…
system-intrinsics-xsaves.ll
…
system-intrinsics-xsetbv.ll
[X86] Remove isel predicates for xgetbv/xsetbv instructions so they can work on Windows.
2021-09-02 10:25:02 -07:00
system-intrinsics.ll
…
tagged-globals-pic.ll
[x86] Implement a tagged-globals backend feature.
2021-10-18 13:31:10 -07:00
tagged-globals-static.ll
[x86] Implement a tagged-globals backend feature.
2021-10-18 13:31:10 -07:00
tail-call-attrs.ll
…
tail-call-casts.ll
…
tail-call-conditional.mir
…
tail-call-got.ll
…
tail-call-legality.ll
…
tail-call-mutable-memarg.ll
…
tail-call-parameter-attrs-mismatch.ll
…
tail-call-win64.ll
…
tail-calls-compatible-attrs.ll
…
tail-dup-addr.ll
…
tail-dup-asm-goto.ll
[MIRParser] Add support for IsInlineAsmBrIndirectTarget
2021-10-07 19:08:01 +01:00
tail-dup-catchret.ll
…
tail-dup-debugloc.ll
…
tail-dup-debugvalue.mir
[DebugInfo] Correctly update debug users of SSA values in tail duplication
2021-07-26 17:27:57 +01:00
tail-dup-merge-loop-headers.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
tail-dup-no-other-successor.ll
…
tail-dup-partial.ll
…
tail-dup-repeat.ll
…
tail-merge-after-mbp.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
tail-merge-debugloc.ll
…
tail-merge-identical.ll
…
tail-merge-unreachable.ll
…
tail-merge-wineh.ll
…
tail-opts.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
tail-threshold.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
tailcall-64.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
tailcall-assume.ll
…
tailcall-calleesave.ll
…
tailcall-cgp-dup.ll
…
tailcall-disable.ll
…
tailcall-extract.ll
…
tailcall-fastisel.ll
…
tailcall-largecode.ll
…
tailcall-lifetime-end.ll
…
tailcall-mem-intrinsics.ll
…
tailcall-msvc-conventions.ll
…
tailcall-multiret.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
tailcall-pseudo-64.mir
…
tailcall-pseudo.mir
…
tailcall-readnone.ll
…
tailcall-returndup-void.ll
…
tailcall-ri64.ll
…
tailcall-stackalign.ll
…
tailcall-structret.ll
…
tailcall-swifttailcc.ll
…
tailcall-tailcc.ll
…
tailcall.ll
…
tailcallbyval64.ll
…
tailcallbyval.ll
…
tailcallfp2.ll
…
tailcallfp.ll
…
tailcallpic1.ll
…
tailcallpic2.ll
…
tailcallpic3.ll
…
tailcallstack64.ll
…
tailcc-calleesave.ll
…
tailcc-disable-tail-calls.ll
…
tailcc-fastcc.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
tailcc-fastisel.ll
[X86] Add new calling convention that guarantees tail call optimization
2019-10-07 22:28:58 +00:00
tailcc-largecode.ll
[X86] Add new calling convention that guarantees tail call optimization
2019-10-07 22:28:58 +00:00
tailcc-notail.ll
…
tailcc-ssp.ll
…
tailcc-stackalign.ll
[X86] Add new calling convention that guarantees tail call optimization
2019-10-07 22:28:58 +00:00
tailcc-structret.ll
[X86] Add new calling convention that guarantees tail call optimization
2019-10-07 22:28:58 +00:00
tailccbyval64.ll
…
tailccbyval.ll
…
tailccfp2.ll
…
tailccfp.ll
…
tailccpic1.ll
…
tailccpic2.ll
…
tailccstack64.ll
[X86] Add new calling convention that guarantees tail call optimization
2019-10-07 22:28:58 +00:00
taildup-callsiteinfo.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
taildup-crash.ll
…
taildup-heapallocsite.ll
…
tailjmp_gotpcrel_relax_relocation.ll
…
tailregccpic.ll
…
targetLoweringGeneric.ll
…
tbm_patterns.ll
…
tbm-intrinsics-fast-isel-x86_64.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
tbm-intrinsics-fast-isel.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
tbm-intrinsics-x86_64.ll
…
tbm-intrinsics.ll
…
test-nofold.ll
…
test-shrink-bug.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
test-shrink.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
test-vs-bittest.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
testb-je-fusion.ll
[X86] Regenerate testb-je-fusion.ll with common NOFUSION/FUSION prefixes
2021-10-18 21:52:10 +01:00
testl-commute.ll
…
text-section-prefix.ll
…
this-return-64.ll
…
thread_pointer-error.ll
[X86][ISel] Lowering llvm.thread.pointer
2021-10-12 11:01:18 +08:00
thread_pointer.ll
[X86][ISel] Lowering llvm.thread.pointer
2021-10-12 11:01:18 +08:00
throws-cfi-fp.ll
…
throws-cfi-no-fp.ll
…
tls-addr-non-leaf-function.ll
…
tls-android-negative.ll
…
tls-android.ll
…
tls-local-dynamic.ll
…
tls-models.ll
…
tls-no-plt.ll
…
tls-pic.ll
…
tls-pie.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
tls-shrink-wrapping.ll
…
tls-windows-itanium.ll
…
tls.ll
…
tlv-1.ll
…
tlv-2.ll
…
tlv-3.ll
…
token_landingpad.ll
…
topdepthreduce-postra.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
trap.ll
…
tree_way_unsigned_cmp.ll
…
trunc-and.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
trunc-ext-ld-st.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
trunc-store.ll
…
trunc-subvector.ll
…
trunc-to-bool.ll
…
trunc-vector-width.ll
[X86][AVX] getAVX512TruncNode - don't truncate from illegal vector widths.
2020-08-19 13:00:26 +01:00
TruncAssertSext.ll
…
TruncAssertZext.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
tsxldtrk-intrinsic.ll
…
twoaddr-coalesce-2.ll
…
twoaddr-coalesce-3.ll
…
twoaddr-coalesce.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
twoaddr-dbg-value.mir
…
twoaddr-lea.ll
[X86] Regenerate twoaddr-lea.ll test checks.
2021-07-16 17:43:36 +01:00
twoaddr-mul2.mir
[X86] Special-case ADD of two identical registers in convertToThreeAddress
2021-10-07 19:50:27 +01:00
twoaddr-sink-terminator.ll
…
typeid-alias.ll
…
uadd_inc_iv.ll
…
uadd_sat_plus.ll
…
uadd_sat_vec.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
uadd_sat.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
ubsantrap.ll
[UBSAN][PS4] For the PS4 target, emit the ud2 ocpode for ubsan traps.
2021-10-06 11:49:36 -07:00
udiv_fix_sat.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
udiv_fix.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
uint64-to-float.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
uint_to_fp-2.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
uint_to_fp-3.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
uint_to_fp.ll
…
uintr-intrinsics.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
umax.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
umin.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
umul_fix_sat.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
umul_fix.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
umul-with-carry.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
umul-with-overflow.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
umulo-64-legalisation-lowering.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
umulo-128-legalisation-lowering.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
unaligned-32-byte-memops.ll
…
unaligned-load.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
unaligned-spill-folding.ll
reland [IR] make -stack-alignment= into a module attr
2021-06-08 10:59:46 -07:00
undef-eflags.mir
…
undef-globals-bss.ll
…
undef-label.ll
…
undef-ops.ll
…
unfold-masked-merge-scalar-constmask-innerouter.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
unfold-masked-merge-scalar-constmask-interleavedbits.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
unfold-masked-merge-scalar-constmask-interleavedbytehalves.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
unfold-masked-merge-scalar-constmask-lowhigh.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
unfold-masked-merge-scalar-variablemask.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
unfold-masked-merge-vector-variablemask-const.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
unfold-masked-merge-vector-variablemask.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
unfoldMemoryOperand.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
unknown-location.ll
…
unreachable-loop-sinking.ll
…
unreachable-mbb-undef-phi.mir
…
unreachable-trap.ll
…
unreachableblockelim.ll
…
unused_stackslots.ll
…
unwind-init.ll
…
unwind-inline-asm-codegen.ll
Support unwinding from inline assembly
2021-05-13 19:13:03 +01:00
unwindraise.ll
…
update-terminator-debugloc.ll
Recommit [ScalarEvolution] Make getMinusSCEV() fail for unrelated pointers.
2021-07-06 12:16:05 -07:00
update-terminator.mir
…
urem-i8-constant.ll
…
urem-lkk.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
urem-power-of-two.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
urem-seteq-illegal-types.ll
[X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760)
2021-06-30 18:46:50 +01:00
urem-seteq-nonzero.ll
…
urem-seteq-optsize.ll
…
urem-seteq-vec-nonsplat.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
urem-seteq-vec-nonzero.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
urem-seteq-vec-splat.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
urem-seteq-vec-tautological.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
urem-seteq.ll
[X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760)
2021-06-30 18:46:50 +01:00
urem-vector-lkk.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
use-add-flags.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
use-cr-result-of-dom-icmp-st.ll
…
ushl_sat_vec.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
ushl_sat.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
usub_inc_iv.ll
…
usub_sat_plus.ll
…
usub_sat_vec.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
usub_sat.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
utf8.ll
…
utf16-cfstrings.ll
…
uwtables.ll
…
v2f32.ll
…
v4f32-immediate.ll
…
v4i32load-crash.ll
…
v8i1-masks.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vaargs-win32.ll
[X86][MS] Fix the aligement mismatch of vector variable arguments on Win32
2021-09-08 09:26:44 +08:00
vaargs.ll
…
vaes-intrinsics-avx512-x86.ll
…
vaes-intrinsics-avx512vl-x86.ll
…
vaes-intrinsics-avx-x86.ll
…
var-permute-128.ll
[X86][AVX] Prefer vinsertf128 to vperm2f128 on AVX1 targets
2021-07-26 11:11:56 +01:00
var-permute-256.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
var-permute-512.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vararg_no_start.ll
…
vararg_tailcall.ll
…
vararg-callee-cleanup.ll
…
varargs-softfloat.ll
[X86] avoid assert with varargs, soft float, and no-implicit-float
2021-06-15 11:27:35 -07:00
variable-sized-darwin-bzero.ll
[Codegen][X86] Modernize/regenerate old tests. NFCI.
2019-12-10 00:27:46 +01:00
variadic-node-pic.ll
Re-land r335297 "[X86] Implement more of x86-64 large and medium PIC code models"
2018-07-23 21:14:35 +00:00
vastart-defs-eflags.ll
…
vbinop-simplify-bug.ll
…
vec3-setcc-crash.ll
…
vec3.ll
[X86][SSE] getV4X86ShuffleImm8 - canonicalize broadcast masks
2020-07-29 11:32:44 +01:00
vec_align_i256.ll
…
vec_align.ll
[Codegen][X86] Modernize/regenerate old tests. NFCI.
2019-12-10 00:27:46 +01:00
vec_anyext.ll
…
vec_call.ll
…
vec_cast2.ll
…
vec_cast3.ll
[X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction.
2021-07-14 12:03:49 +01:00
vec_cast.ll
…
vec_cmp_sint-128.ll
…
vec_cmp_uint-128.ll
…
vec_compare-sse4.ll
…
vec_compare.ll
…
vec_ctbits.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vec_ext_inreg.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_extract-avx.ll
…
vec_extract-mmx.ll
…
vec_extract-sse4.ll
…
vec_extract.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_fabs.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_floor.ll
…
vec_fneg.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_fp_to_int.ll
[X86] Implement smarter instruction lowering for FP_TO_UINT from f32/f64 to i32/i64 and vXf32/vXf64 to vXi32 for SSE2 and AVX2 by using the exact semantic of the CVTTPS2SI instruction.
2021-07-14 12:03:49 +01:00
vec_fpext.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_fptrunc.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_i64.ll
…
vec_ins_extract-1.ll
…
vec_ins_extract.ll
…
vec_insert-2.ll
[X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add general shuffle combining support
2020-09-02 09:24:46 +01:00
vec_insert-3.ll
[X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add general shuffle combining support
2020-09-02 09:24:46 +01:00
vec_insert-4.ll
[CodeGen] Ensure callers of CreateStackTemporary use sensible alignments
2020-06-09 08:10:17 +01:00
vec_insert-5.ll
[X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add general shuffle combining support
2020-09-02 09:24:46 +01:00
vec_insert-7.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_insert-8.ll
Followup on Proposal to move MIR physical register namespace to '$' sigil.
2018-01-31 22:04:26 +00:00
vec_insert-9.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_insert-mmx.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_int_to_fp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_loadsingles.ll
…
vec_logical.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_minmax_match.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_minmax_sint.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vec_minmax_uint.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vec_partial.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_reassociate.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_return.ll
…
vec_saddo.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vec_sdiv_to_shift.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vec_set-2.ll
…
vec_set-3.ll
…
vec_set-4.ll
…
vec_set-6.ll
…
vec_set-7.ll
…
vec_set-8.ll
…
vec_set-A.ll
…
vec_set-B.ll
…
vec_set-C.ll
…
vec_set-D.ll
…
vec_set-F.ll
…
vec_set-H.ll
…
vec_set.ll
[CodeGen] Unify MBB reference format in both MIR and debug output
2017-12-04 17:18:51 +00:00
vec_setcc-2.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_setcc.ll
[X86] Teach getUndefRegClearance that we use undef for inputs to PUNPCK in some cases.
2020-05-09 12:19:30 -07:00
vec_shift2.ll
[CodeGen][X86] Remove unused check-prefixes from vec tests. NFCI.
2020-11-11 15:32:42 +08:00
vec_shift3.ll
[X86] Regenerate vector shift tests. NFCI.
2020-10-27 13:14:54 +00:00
vec_shift4.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
vec_shift5.ll
[X86] Fold (shift undef, X)->0 for vector shifts by immediate.
2021-05-27 09:31:47 -07:00
vec_shift6.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vec_shift7.ll
[CodeGen][X86] Remove unused check-prefixes from vec tests. NFCI.
2020-11-11 15:32:42 +08:00
vec_shift.ll
[X86] Regenerate vector shift tests. NFCI.
2020-10-27 13:14:54 +00:00
vec_shuf-insert.ll
…
vec_smulo.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vec_split.ll
[X86] Autogenerate vec_* tests. NFC
2019-08-20 23:11:29 +00:00
vec_ss_load_fold.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_ssubo.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vec_trunc_sext.ll
…
vec_uaddo.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
vec_uint_to_fp-fastmath.ll
…
vec_uint_to_fp.ll
…
vec_umulo.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vec_unsafe-fp-math.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_usubo.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
vec_zero_cse.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec_zero-2.ll
[X86] Autogenerate vec_* tests. NFC
2019-08-20 23:11:29 +00:00
vec_zero.ll
[X86][SSE] Regenerate vector zero tests
2019-03-05 16:52:14 +00:00
vec-copysign-avx512.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec-copysign.ll
…
vec-libcalls.ll
[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
2021-06-11 16:49:12 +01:00
vec-loadsingles-alignment.ll
…
vec-strict-128-fp16.ll
[X86] AVX512FP16 instructions enabling 5/6
2021-08-24 09:07:19 +08:00
vec-strict-128.ll
[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
2021-06-11 16:49:12 +01:00
vec-strict-256-fp16.ll
[X86] AVX512FP16 instructions enabling 5/6
2021-08-24 09:07:19 +08:00
vec-strict-256.ll
…
vec-strict-512-fp16.ll
[X86] AVX512FP16 instructions enabling 5/6
2021-08-24 09:07:19 +08:00
vec-strict-512.ll
…
vec-strict-cmp-128-fp16.ll
[X86] AVX512FP16 instructions enabling 2/6
2021-08-15 08:56:33 +08:00
vec-strict-cmp-128.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
vec-strict-cmp-256-fp16.ll
[X86] AVX512FP16 instructions enabling 2/6
2021-08-15 08:56:33 +08:00
vec-strict-cmp-256.ll
…
vec-strict-cmp-512-fp16.ll
[X86] AVX512FP16 instructions enabling 2/6
2021-08-15 08:56:33 +08:00
vec-strict-cmp-512.ll
…
vec-strict-cmp-sub128.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
vec-strict-fptoint-128-fp16.ll
[X86] AVX512FP16 instructions enabling 3/6
2021-08-18 09:03:41 +08:00
vec-strict-fptoint-128.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vec-strict-fptoint-256-fp16.ll
[X86] AVX512FP16 instructions enabling 3/6
2021-08-18 09:03:41 +08:00
vec-strict-fptoint-256.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
vec-strict-fptoint-512-fp16.ll
[X86] AVX512FP16 instructions enabling 3/6
2021-08-18 09:03:41 +08:00
vec-strict-fptoint-512.ll
…
vec-strict-inttofp-128-fp16.ll
[X86] AVX512FP16 instructions enabling 3/6
2021-08-18 09:03:41 +08:00
vec-strict-inttofp-128.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec-strict-inttofp-256-fp16.ll
[X86] AVX512FP16 instructions enabling 3/6
2021-08-18 09:03:41 +08:00
vec-strict-inttofp-256.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vec-strict-inttofp-512-fp16.ll
[X86] AVX512FP16 instructions enabling 3/6
2021-08-18 09:03:41 +08:00
vec-strict-inttofp-512.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
vec-strict-round-128.ll
…
vec-trunc-store.ll
…
vecloadextract.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
vector_splat-const-shift-of-constmasked.ll
[X86] Remove incorrect use of known bits in shuffle simplification.
2021-07-18 18:13:11 -07:00
vector-bitreverse.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-blend.ll
…
vector-compare-all_of.ll
…
vector-compare-any_of.ll
…
vector-compare-combines.ll
…
vector-compare-results.ll
…
vector-compare-simplify.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-constrained-fp-intrinsics-flags.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
vector-constrained-fp-intrinsics-fma.ll
…
vector-constrained-fp-intrinsics.ll
[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
2021-06-11 16:49:12 +01:00
vector-ext-logic.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-extend-inreg.ll
…
vector-fshl-128.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-fshl-256.ll
[X86][SSE] LowerRotate - perform modulo on the amount splat source directly.
2021-07-25 17:30:32 +01:00
vector-fshl-512.ll
[TLI] SimplifyDemandedVectorElts(): handle SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT(?, 0))
2021-06-14 23:52:53 +03:00
vector-fshl-rot-128.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-fshl-rot-256.ll
[X86] Freeze vXi8 shl(x,1) -> add(x,x) vector fold (PR50468)
2021-08-24 16:08:24 +01:00
vector-fshl-rot-512.ll
[X86] Freeze vXi8 shl(x,1) -> add(x,x) vector fold (PR50468)
2021-08-24 16:08:24 +01:00
vector-fshl-rot-sub128.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-fshr-128.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-fshr-256.ll
[X86] Freeze vXi8 shl(x,1) -> add(x,x) vector fold (PR50468)
2021-08-24 16:08:24 +01:00
vector-fshr-512.ll
[TLI] SimplifyDemandedVectorElts(): handle SCALAR_TO_VECTOR(EXTRACT_VECTOR_ELT(?, 0))
2021-06-14 23:52:53 +03:00
vector-fshr-rot-128.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-fshr-rot-256.ll
[X86] Freeze vXi8 shl(x,1) -> add(x,x) vector fold (PR50468)
2021-08-24 16:08:24 +01:00
vector-fshr-rot-512.ll
[X86] Freeze vXi8 shl(x,1) -> add(x,x) vector fold (PR50468)
2021-08-24 16:08:24 +01:00
vector-fshr-rot-sub128.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-gep.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
vector-half-conversions.ll
[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
2021-06-11 16:49:12 +01:00
vector-idiv-sdiv-128.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-idiv-sdiv-256.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-idiv-sdiv-512.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-idiv-udiv-128.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-idiv-udiv-256.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-idiv-udiv-512.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-idiv-v2i32.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
vector-idiv.ll
…
vector-interleave.ll
[X86][AVX] Prefer vinsertf128 to vperm2f128 on AVX1 targets
2021-07-26 11:11:56 +01:00
vector-interleaved-load-i8-stride-2.ll
[X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests
2021-10-03 12:31:30 +01:00
vector-interleaved-load-i8-stride-3.ll
[X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests
2021-10-03 12:31:30 +01:00
vector-interleaved-load-i8-stride-4.ll
[X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests
2021-10-03 12:31:30 +01:00
vector-interleaved-load-i8-stride-6.ll
[NFC][X86][Codegen] Add test coverage for interleaved i8 load/store stride=6
2021-10-03 14:35:17 +03:00
vector-interleaved-load-i16-stride-2.ll
[X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests
2021-10-03 12:31:30 +01:00
vector-interleaved-load-i16-stride-3.ll
[X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests
2021-10-03 12:31:30 +01:00
vector-interleaved-load-i16-stride-4.ll
[X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests
2021-10-03 12:31:30 +01:00
vector-interleaved-load-i16-stride-5.ll
[NFC][X86][Codegen] Add missing interleaving tests after D111546
2021-10-16 18:20:16 +03:00
vector-interleaved-load-i16-stride-6.ll
[NFC][X86][Codegen] Add missing interleaving tests after D111546
2021-10-16 18:20:16 +03:00
vector-interleaved-load-i32-stride-2.ll
[X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests
2021-10-03 12:31:30 +01:00
vector-interleaved-load-i32-stride-3.ll
[NFC][X86][Codegen] Add missing interleaving tests after D111546
2021-10-16 18:20:16 +03:00
vector-interleaved-load-i32-stride-4.ll
[NFC][X86][Codegen] Add missing interleaving tests after D111546
2021-10-16 18:20:16 +03:00
vector-interleaved-load-i32-stride-6.ll
[NFC][X86][Codegen] Add test coverage for interleaved i32 load/store stride=6
2021-10-04 20:57:35 +03:00
vector-interleaved-load-i64-stride-2.ll
[NFC][X86][Codegen] Add missing interleaving tests after D111546
2021-10-16 18:20:16 +03:00
vector-interleaved-load-i64-stride-3.ll
[NFC][X86][Codegen] Add test coverage for interleaved i64 load/store stride=3
2021-10-03 17:52:12 +03:00
vector-interleaved-load-i64-stride-4.ll
[NFC][X86][Codegen] Add missing interleaving tests after D111546
2021-10-16 18:20:16 +03:00
vector-interleaved-load-i64-stride-6.ll
[NFC][X86][Codegen] Add test coverage for interleaved i64 load/store stride=6
2021-10-04 20:57:36 +03:00
vector-interleaved-store-i8-stride-2.ll
[X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests
2021-10-03 12:31:30 +01:00
vector-interleaved-store-i8-stride-3.ll
[X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests
2021-10-03 12:31:30 +01:00
vector-interleaved-store-i8-stride-4.ll
[X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests
2021-10-03 12:31:30 +01:00
vector-interleaved-store-i8-stride-6.ll
[NFC][X86][Codegen] Add test coverage for interleaved i8 load/store stride=6
2021-10-03 14:35:17 +03:00
vector-interleaved-store-i16-stride-2.ll
[X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests
2021-10-03 12:31:30 +01:00
vector-interleaved-store-i16-stride-3.ll
[X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests
2021-10-03 12:31:30 +01:00
vector-interleaved-store-i16-stride-4.ll
[X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests
2021-10-03 12:31:30 +01:00
vector-interleaved-store-i16-stride-5.ll
[NFC][X86][Codegen] Add missing interleaving tests after D111546
2021-10-16 18:20:16 +03:00
vector-interleaved-store-i16-stride-6.ll
[NFC][X86][Codegen] Add missing interleaving tests after D111546
2021-10-16 18:20:16 +03:00
vector-interleaved-store-i32-stride-2.ll
[X86] Add SSE2/AVX1/AVX512BW test coverage to interleaved load/store tests
2021-10-03 12:31:30 +01:00
vector-interleaved-store-i32-stride-3.ll
[NFC][X86][Codegen] Add missing interleaving tests after D111546
2021-10-16 18:20:16 +03:00
vector-interleaved-store-i32-stride-4.ll
[NFC][X86][Codegen] Add missing interleaving tests after D111546
2021-10-16 18:20:16 +03:00
vector-interleaved-store-i32-stride-6.ll
[NFC][X86][Codegen] Add test coverage for interleaved i32 load/store stride=6
2021-10-04 20:57:35 +03:00
vector-interleaved-store-i64-stride-2.ll
[NFC][X86][Codegen] Add missing interleaving tests after D111546
2021-10-16 18:20:16 +03:00
vector-interleaved-store-i64-stride-3.ll
[NFC][X86][Codegen] Add test coverage for interleaved i64 load/store stride=3
2021-10-03 17:52:12 +03:00
vector-interleaved-store-i64-stride-4.ll
[NFC][X86][Codegen] Add missing interleaving tests after D111546
2021-10-16 18:20:16 +03:00
vector-interleaved-store-i64-stride-6.ll
[NFC][X86][Codegen] Add test coverage for interleaved i64 load/store stride=6
2021-10-04 20:57:36 +03:00
vector-intrinsics.ll
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00
vector-lzcnt-128.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-lzcnt-256.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-lzcnt-512.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-lzcnt-sub128.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-merge-store-fp-constants.ll
…
vector-mul.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-mulfix-legalize.ll
[X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760)
2021-06-30 18:46:50 +01:00
vector-narrow-binop.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-pack-128.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-pack-256.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-pack-512.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-partial-undef.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-pcmp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-popcnt-128-ult-ugt.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-popcnt-128.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-popcnt-256-ult-ugt.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-popcnt-256.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-popcnt-512-ult-ugt.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-popcnt-512.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-reduce-add.ll
…
vector-reduce-and-bool.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-reduce-and-cmp.ll
…
vector-reduce-and.ll
…
vector-reduce-fadd-fast.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-reduce-fadd.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-reduce-fmax-fmin-fast.ll
…
vector-reduce-fmax-nnan.ll
[X86] AVX512FP16 instructions enabling 2/6
2021-08-15 08:56:33 +08:00
vector-reduce-fmax.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-reduce-fmin-nnan.ll
[X86] AVX512FP16 instructions enabling 2/6
2021-08-15 08:56:33 +08:00
vector-reduce-fmin.ll
…
vector-reduce-fmul-fast.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-reduce-fmul.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-reduce-mul.ll
[X86] combineX86ShuffleChain - ensure we only peek through bitcasts to vectors (PR51858)
2021-09-15 10:21:05 +01:00
vector-reduce-or-bool.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-reduce-or-cmp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-reduce-or.ll
…
vector-reduce-smax.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-reduce-smin.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-reduce-umax.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-reduce-umin.ll
…
vector-reduce-xor-bool.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-reduce-xor.ll
…
vector-rem.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-rotate-128.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-rotate-256.ll
[X86] Freeze vXi8 shl(x,1) -> add(x,x) vector fold (PR50468)
2021-08-24 16:08:24 +01:00
vector-rotate-512.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-sext.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
vector-shift-ashr-128.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-shift-ashr-256.ll
…
vector-shift-ashr-512.ll
…
vector-shift-ashr-sub128.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-shift-by-select-loop.ll
[CodeGen][X86] Remove unused check-prefixes from vector shift tests. NFCI.
2020-11-11 14:19:14 +08:00
vector-shift-lshr-128.ll
…
vector-shift-lshr-256.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
vector-shift-lshr-512.ll
…
vector-shift-lshr-sub128.ll
…
vector-shift-shl-128.ll
…
vector-shift-shl-256.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
vector-shift-shl-512.ll
…
vector-shift-shl-sub128.ll
…
vector-shuffle-128-unpck.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
vector-shuffle-128-v2.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-shuffle-128-v4.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
vector-shuffle-128-v8.ll
[X86][AVX] Adjust AllowBWIVPERMV3 tolerance to account for VariableCrossLaneShuffleDepth
2021-07-25 14:05:11 +01:00
vector-shuffle-128-v16.ll
[X86][AVX] Adjust AllowBWIVPERMV3 tolerance to account for VariableCrossLaneShuffleDepth
2021-07-25 14:05:11 +01:00
vector-shuffle-256-v4.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
vector-shuffle-256-v8.ll
[X86][AVX] Prefer vinsertf128 to vperm2f128 on AVX1 targets
2021-07-26 11:11:56 +01:00
vector-shuffle-256-v16.ll
[X86][AVX] Adjust AllowBWIVPERMV3 tolerance to account for VariableCrossLaneShuffleDepth
2021-07-25 14:05:11 +01:00
vector-shuffle-256-v32.ll
Revert "[X86] combineX86ShuffleChain(): canonicalize mask elts picking from splats"
2021-08-05 18:58:08 +02:00
vector-shuffle-512-v8.ll
…
vector-shuffle-512-v16.ll
[DAG] Fold concat_vectors(concat_vectors(x,y),concat_vectors(a,b)) -> concat_vectors(x,y,a,b)
2021-08-16 16:06:54 +01:00
vector-shuffle-512-v32.ll
…
vector-shuffle-512-v64.ll
[X86][AVX] Adjust AllowBWIVPERMV3 tolerance to account for VariableCrossLaneShuffleDepth
2021-07-25 14:05:11 +01:00
vector-shuffle-avx512.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-shuffle-combining-avx2.ll
[X86][AVX] Ensure we retain zero elements in select(pshufb,pshufb) -> or(pshufb,pshufb) fold (PR52122)
2021-10-11 14:50:24 +01:00
vector-shuffle-combining-avx512bw.ll
[DAG] CombineConsecutiveLoads - replace getABITypeAlign with allowsMemoryAccess (PR45116)
2021-08-24 12:31:22 +01:00
vector-shuffle-combining-avx512bwvl.ll
…
vector-shuffle-combining-avx512f.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-shuffle-combining-avx512vbmi.ll
[DAG] CombineConsecutiveLoads - replace getABITypeAlign with allowsMemoryAccess (PR45116)
2021-08-24 12:31:22 +01:00
vector-shuffle-combining-avx.ll
…
vector-shuffle-combining-sse4a.ll
…
vector-shuffle-combining-sse41.ll
…
vector-shuffle-combining-ssse3.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-shuffle-combining-xop.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-shuffle-combining.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-shuffle-masked.ll
…
vector-shuffle-mmx.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-shuffle-sse1.ll
…
vector-shuffle-sse4a.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-shuffle-sse41.ll
…
vector-shuffle-v1.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
vector-shuffle-v48.ll
[X86][AVX] Adjust AllowBWIVPERMV3 tolerance to account for VariableCrossLaneShuffleDepth
2021-07-25 14:05:11 +01:00
vector-shuffle-variable-128.ll
…
vector-shuffle-variable-256.ll
…
vector-sqrt.ll
…
vector-trunc-math.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-trunc-packus.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
vector-trunc-ssat.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
vector-trunc-usat.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
vector-trunc.ll
[X86] Split FeatureFastVariableShuffle tuning into Lane-Crossing and Per-Lane variants
2021-06-01 10:39:36 +03:00
vector-truncate-combine.ll
…
vector-tzcnt-128.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-tzcnt-256.ll
…
vector-tzcnt-512.ll
…
vector-unsigned-cmp.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vector-variable-idx2.ll
…
vector-variable-idx.ll
[Codegen][X86] Modernize/regenerate old tests. NFCI.
2019-12-10 00:27:46 +01:00
vector-width-store-merge.ll
…
vector-zext.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vector-zmov.ll
…
vector.ll
…
vectorcall.ll
[Mangler] Calculate the argument list byte count suffix correctly when returning large values
2021-09-29 11:42:28 -07:00
version_directive.ll
…
vfcmp.ll
…
viabs.ll
…
virtreg-physreg-def-regallocfast.mir
…
virtual-registers-cleared-in-machine-functions-liveins.ll
…
visibility2.ll
…
visibility.ll
…
vmaskmov-offset.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
vmovq.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
volatile-memstores-nooverlapping-load-stores.ll
…
volatile.ll
…
vortex-bug.ll
…
vp2intersect_multiple_pairs.ll
[X86FixupLEAs] Try again to transform the sequence LEA/SUB to SUB/SUB
2021-07-16 10:16:03 -07:00
vpshufbitqbm-intrinsics-upgrade.ll
…
vpshufbitqbm-intrinsics.ll
…
vsel-cmp-load.ll
…
vselect-2.ll
…
vselect-avx.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vselect-constants.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vselect-minmax.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vselect-packss.ll
…
vselect-pcmp.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vselect-zero.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
vselect.ll
[X86] Fold SHUFPS(shuffle(x),shuffle(y),mask) -> SHUFPS(x,y,mask')
2021-09-19 20:39:19 +01:00
vshift_scalar.ll
…
vshift_split2.ll
[X86] Regenerate vector shift tests. NFCI.
2020-10-27 13:14:54 +00:00
vshift_split.ll
[X86] Regenerate vector shift tests. NFCI.
2020-10-27 13:14:54 +00:00
vshift-1.ll
…
vshift-2.ll
…
vshift-3.ll
…
vshift-4.ll
…
vshift-5.ll
…
vshift-6.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
vshli-simplify-demanded-bits.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
vsplit-and.ll
…
vzero-excess.ll
[CodeGen][regalloc] Don't align stack slots if the stack can't be realigned
2021-06-11 16:49:12 +01:00
waitpkg-intrinsics.ll
…
warn-stack.ll
Improve the diagnostic of DiagnosticInfoResourceLimit (and warn-stack-size in particular)
2021-06-22 09:55:20 -07:00
wbinvd-intrinsic.ll
…
wbnoinvd-intrinsic.ll
…
weak_def_can_be_hidden.ll
…
weak-undef.ll
…
weak.ll
…
webkit-jscc.ll
…
wide-fma-contraction.ll
…
wide-integer-cmp.ll
Revert "[BPI] Improve static heuristics for integer comparisons"
2020-08-17 20:44:33 +02:00
wide-integer-fold.ll
…
widen_arith-1.ll
…
widen_arith-2.ll
…
widen_arith-3.ll
…
widen_arith-4.ll
…
widen_arith-5.ll
…
widen_arith-6.ll
…
widen_bitops-0.ll
…
widen_bitops-1.ll
…
widen_cast-1.ll
…
widen_cast-2.ll
…
widen_cast-3.ll
…
widen_cast-4.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
widen_cast-5.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
widen_cast-6.ll
…
widen_compare-1.ll
…
widen_conv-1.ll
…
widen_conv-2.ll
…
widen_conv-3.ll
…
widen_conv-4.ll
…
widen_conversions.ll
…
widen_extract-1.ll
…
widen_load-0.ll
…
widen_load-1.ll
…
widen_load-2.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
widen_load-3.ll
…
widen_mul.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
widen_shuffle-1.ll
…
WidenArith.ll
…
widened-broadcast.ll
…
win32_sret.ll
…
win32-bool.ll
…
win32-eh-available-externally.ll
…
win32-eh-states.ll
…
win32-eh.ll
…
win32-pic-jumptable.ll
…
win32-preemption.ll
…
win32-seh-catchpad-realign.ll
…
win32-seh-catchpad.ll
…
win32-seh-nested-finally.ll
…
win32-spill-xmm.ll
[X86][MS] Fix the aligement mismatch of vector variable arguments on Win32
2021-09-08 09:26:44 +08:00
win32-ssp.ll
…
win64_alloca_dynalloca.ll
…
win64_call_epi.ll
…
win64_eh_leaf2.ll
…
win64_eh_leaf.ll
…
win64_eh.ll
…
win64_frame.ll
…
win64_nonvol.ll
…
win64_params.ll
…
win64_regcall.ll
…
win64_sibcall.ll
…
win64_vararg.ll
…
win64-bool.ll
…
win64-byval.ll
…
win64-eh-empty-block-2.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
win64-eh-empty-block.ll
…
win64-funclet-savexmm.ll
…
win64-jumptable.ll
…
win64-long-double.ll
…
win64-nosse-csrs.ll
…
win64-stackprobe-overflow.ll
[X86] [Win64] Avoid truncating large (> 32 bit) stack allocations
2019-11-27 10:44:42 +02:00
win_chkstk.ll
…
win_coreclr_chkstk_liveins.mir
…
win_coreclr_chkstk.ll
…
win_cst_pool.ll
…
win-alloca-expander.ll
…
win-catchpad-csrs.ll
…
win-catchpad-nested-cxx.ll
…
win-catchpad-nested.ll
…
win-catchpad-varargs.ll
…
win-catchpad.ll
…
win-cleanuppad.ll
…
win-funclet-cfi.ll
…
win-mixed-ehpersonality.ll
…
win-smallparams.ll
…
windows-itanium-alloca.ll
…
wineh-coreclr.ll
…
wineh-exceptionpointer.ll
…
wineh-no-ehpads.ll
…
x32-cet-intrinsics.ll
…
x32-function_pointer-1.ll
[test] Add explicit dso_local to constant/global variable declarations
2020-12-04 13:51:01 -08:00
x32-function_pointer-2.ll
[X86] Zero-extend pointers to i64 for x86_64
2020-11-30 18:51:23 +00:00
x32-function_pointer-3.ll
…
x32-indirectbr.ll
…
x32-landingpad.ll
…
x32-lea-1.ll
[X32] Add Triple::isX32(), use it.
2021-06-07 20:48:39 +01:00
x32-movtopush64.ll
…
x32-va_start.ll
…
x64-cet-intrinsics.ll
…
x86_64-mul-by-const.ll
…
x86-16.ll
…
x86-32-intrcc.ll
…
x86-32-vector-calling-conv.ll
…
x86-64-and-mask.ll
…
x86-64-arg.ll
…
x86-64-asm.ll
…
x86-64-baseptr.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
x86-64-bittest-logic.ll
…
x86-64-call.ll
…
x86-64-disp.ll
…
x86-64-double-precision-shift-left.ll
…
x86-64-double-precision-shift-right.ll
…
x86-64-double-shifts-Oz-Os-O2.ll
…
x86-64-double-shifts-var.ll
…
x86-64-extend-shift.ll
…
x86-64-flags-intrinsics.ll
…
x86-64-gv-offset.ll
…
x86-64-intrcc-nosse.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
x86-64-intrcc-uintr.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
x86-64-intrcc.ll
…
x86-64-jumps.ll
…
x86-64-mem.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
x86-64-ms_abi-vararg.ll
…
x86-64-pic-1.ll
…
x86-64-pic-2.ll
…
x86-64-pic-3.ll
…
x86-64-pic-4.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
x86-64-pic-5.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
x86-64-pic-6.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
x86-64-pic-7.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
x86-64-pic-8.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
x86-64-pic-9.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
x86-64-pic-10.ll
…
x86-64-pic-11.ll
…
x86-64-pic-12.ll
…
x86-64-pic.ll
…
x86-64-plt-relative-reloc.ll
…
x86-64-psub.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
x86-64-ptr-arg-simple.ll
…
x86-64-ret0.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
x86-64-shortint.ll
…
x86-64-sret-return-2.ll
…
x86-64-sret-return.ll
…
x86-64-stack-and-frame-ptr.ll
…
x86-64-static-relo-movl.ll
…
x86-64-tls-1.ll
…
x86-64-varargs.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
x86-64-veccallcc.ll
…
x86-64-xmm-spill-unaligned.ll
reland [IR] make -stack-alignment= into a module attr
2021-06-08 10:59:46 -07:00
x86-big-ret.ll
…
x86-cmov-converter.ll
[X86] Update MachineLoopInfo in CMOV conversion.
2021-07-21 10:53:46 +08:00
x86-flags-intrinsics.ll
…
x86-fold-pshufb.ll
…
x86-framelowering-trap.ll
…
x86-inline-asm-validation.ll
…
x86-interleaved-access.ll
[DAG] Fold concat_vectors(concat_vectors(x,y),concat_vectors(a,b)) -> concat_vectors(x,y,a,b)
2021-08-16 16:06:54 +01:00
x86-interleaved-check.ll
…
x86-interrupt_cc.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
x86-interrupt_cld.ll
…
x86-interrupt_vzeroupper.ll
…
x86-mixed-alignment-dagcombine.ll
…
x86-no_callee_saved_registers.ll
…
x86-no_caller_saved_registers-preserve.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
x86-no_caller_saved_registers.ll
…
x86-plt-relative-reloc.ll
…
x86-regcall-got.ll
…
x86-repmov-copy-eflags.ll
…
x86-sanitizer-shrink-wrapping.ll
…
x86-setcc-int-to-fp-combine.ll
…
x86-shifts.ll
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
x86-shrink-wrap-unwind.ll
…
x86-shrink-wrapping.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
x86-store-gv-addr.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
x86-upgrade-avx2-vbroadcast.ll
…
x86-upgrade-avx-vbroadcast.ll
…
x86-win64-shrink-wrapping.ll
…
x87-reg-usage.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
x87.ll
…
xaluo128.ll
…
xaluo.ll
…
xchg-nofold.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
xmm-r64.ll
…
xmm-vararg-noopt.ll
…
xmulo.ll
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
xop-ifma.ll
…
xop-intrinsics-fast-isel.ll
…
xop-intrinsics-x86_64-upgrade.ll
…
xop-intrinsics-x86_64.ll
…
xop-mask-comments.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
xop-pcmov.ll
…
xor-combine-debugloc.ll
…
xor-icmp.ll
…
xor-select-i1-combine.ll
…
xor-with-overflow.ll
…
xor.ll
…
xray-attribute-instrumentation.ll
…
xray-custom-log.ll
…
xray-empty-firstmbb.mir
…
xray-ignore-loop-detection.ll
…
xray-log-args.ll
…
xray-loop-detection.ll
…
xray-multiplerets-in-blocks.mir
…
xray-partial-instrumentation-skip-entry.ll
…
xray-partial-instrumentation-skip-exit.ll
…
xray-section-group.ll
…
xray-selective-instrumentation-miss.ll
…
xray-selective-instrumentation.ll
…
xray-tail-call-sled.ll
…
xtest.ll
…
ymm-ordering.ll
[Test] We can benefit from pipelining of ymm load/stores
2021-07-15 17:15:14 +07:00
zero-initialized-in-bss.ll
…
zero-remat.ll
…
zext-demanded.ll
…
zext-extract_subreg.ll
…
zext-fold.ll
[NFC][X86][Codegen] Megacommit: mass-regenerate all check lines that were already autogenerated
2021-06-11 23:57:02 +03:00
zext-inreg-0.ll
…
zext-inreg-1.ll
…
zext-logicop-shift-load.ll
…
zext-sext.ll
[X86] Canonicalize SGT/UGT compares with constants to use SGE/UGE to reduce the number of EFLAGs reads. (PR48760)
2021-06-30 18:46:50 +01:00
zext-shl.ll
…
zext-trunc.ll
[LiveIntervals] Improve repair after convertToThreeAddress
2021-09-28 08:10:08 +01:00
zlib-longest-match.ll
…
znver3-gather.ll
[NFC][X86] Add 'gather' optsize/minsize test coverage
2021-09-27 23:49:10 +03:00