Files
clang-p2996/llvm/utils/TableGen/CodeGenTarget.cpp
Alexandros Lamprineas 3094e5389b [AArch64] Add a Machine Value Type for 8 consecutive registers
Adds MVT::i64x8, a Machine Value Type needed for lowering inline assembly
operands which materialize a sequence of eight general purpose registers.

Differential Revision: https://reviews.llvm.org/D94096
2021-07-31 09:51:28 +01:00

35 KiB