yingopq af1e2a374e [Mips] Support llvm.readcyclecounter intrinsic (#127553) ...

The llvm.readcyclecounter intrinsic can be implemented via the `rdhwr
$2, $hwr_cc` instruction.
$hwr_cc: High-resolution cycle counter. This register provides read
access to the coprocessor 0 Count Register.

Fix #106318.

2025-02-18 11:57:23 +08:00

200 KiB

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