cba70550cc
The "topological" sorting was behaving incorrectly in some cases: the exit of a loop could have a lower rank than a node in the loop. This causes issues when structurizing some patterns, and also codegen issues as we could generate BBs in the incorrect order in regard to the SPIR-V spec. Fixing this ordering alone broke other parts of the structurizer, which by luck worked. Had to fix those. Added more test cases, especially to test basic patterns. I also needed to tweak/disable some tests for 2 reasons: - SPIR-V now required reg2mem/mem2reg to run. Meaning dead stores are optimized away. Some tests require tweaks to avoid having the whole function removed. - Mem2Reg will generate variable & load/stores. This generates G_BITCAST in several cases. And there is currently something wrong we do with G_BITCAST which causes MIR verifier to complain. Until this is resolved, I disabled -verify-machineinstrs flag on those tests. --------- Signed-off-by: Nathan Gauër <brioche@google.com>
167 lines
5.4 KiB
LLVM
167 lines
5.4 KiB
LLVM
; RUN: %if spirv-tools %{ llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | spirv-as --preserve-numeric-ids - -o - | spirv-val %}
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;
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; Source HLSL:
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;
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; int foo() { return true; }
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;
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; int process() {
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; int val = 0;
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; int i = 0;
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;
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; do {
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; ++i;
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; if (i > 5) {
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; {
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; {
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; continue;
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; }
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; }
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; val = i; // No SPIR-V should be emitted for this statement.
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; while(true); // No SPIR-V should be emitted for this statement.
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; }
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; val = i;
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; continue;
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; val = val * 2; // No SPIR-V should be emitted for this statement.
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; continue; // No SPIR-V should be emitted for this statement.
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;
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; } while (i < 10);
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;
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; //////////////////////////////////////////////////////////////////////////////////////
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; // Nested do-while loops with continue statements //
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; // Each continue statement should branch to the corresponding loop's continue block //
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; //////////////////////////////////////////////////////////////////////////////////////
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;
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; do {
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; ++i;
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; do {
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; ++val;
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; continue;
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; } while (i < 10);
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;
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; --i;
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; continue;
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; continue; // No SPIR-V should be emitted for this statement.
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;
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; } while(val < 10);
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;
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; return val;
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; }
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;
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; [numthreads(1, 1, 1)]
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; void main() {
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; process();
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; }
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target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
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target triple = "spirv-unknown-vulkan1.3-compute"
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; Function Attrs: convergent noinline nounwind optnone
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define spir_func noundef i32 @_Z3foov() #0 {
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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ret i32 1
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}
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; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)
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declare token @llvm.experimental.convergence.entry() #1
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; Function Attrs: convergent noinline nounwind optnone
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define spir_func noundef i32 @_Z7processv() #0 {
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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%val = alloca i32, align 4
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%i = alloca i32, align 4
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store i32 0, ptr %val, align 4
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store i32 0, ptr %i, align 4
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br label %do.body
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do.body: ; preds = %do.cond, %entry
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%1 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ]
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%2 = load i32, ptr %i, align 4
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%inc = add nsw i32 %2, 1
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store i32 %inc, ptr %i, align 4
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%3 = load i32, ptr %i, align 4
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%cmp = icmp sgt i32 %3, 5
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %do.body
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br label %do.cond
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if.end: ; preds = %do.body
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%4 = load i32, ptr %i, align 4
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store i32 %4, ptr %val, align 4
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br label %do.cond
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do.cond: ; preds = %if.end, %if.then
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%5 = load i32, ptr %i, align 4
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%cmp1 = icmp slt i32 %5, 10
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br i1 %cmp1, label %do.body, label %do.end
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do.end: ; preds = %do.cond
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br label %do.body2
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do.body2: ; preds = %do.cond9, %do.end
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%6 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %0) ]
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%7 = load i32, ptr %i, align 4
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%inc3 = add nsw i32 %7, 1
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store i32 %inc3, ptr %i, align 4
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br label %do.body4
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do.body4: ; preds = %do.cond6, %do.body2
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%8 = call token @llvm.experimental.convergence.loop() [ "convergencectrl"(token %6) ]
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%9 = load i32, ptr %val, align 4
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%inc5 = add nsw i32 %9, 1
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store i32 %inc5, ptr %val, align 4
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br label %do.cond6
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do.cond6: ; preds = %do.body4
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%10 = load i32, ptr %i, align 4
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%cmp7 = icmp slt i32 %10, 10
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br i1 %cmp7, label %do.body4, label %do.end8
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do.end8: ; preds = %do.cond6
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%11 = load i32, ptr %i, align 4
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%dec = add nsw i32 %11, -1
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store i32 %dec, ptr %i, align 4
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br label %do.cond9
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do.cond9: ; preds = %do.end8
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%12 = load i32, ptr %val, align 4
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%cmp10 = icmp slt i32 %12, 10
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br i1 %cmp10, label %do.body2, label %do.end11
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do.end11: ; preds = %do.cond9
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%13 = load i32, ptr %val, align 4
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ret i32 %13
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}
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; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)
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declare token @llvm.experimental.convergence.loop() #1
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; Function Attrs: convergent noinline norecurse nounwind optnone
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define internal spir_func void @main() #2 {
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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%call1 = call spir_func noundef i32 @_Z7processv() #4 [ "convergencectrl"(token %0) ]
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ret void
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}
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; Function Attrs: convergent norecurse
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define void @main.1() #3 {
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entry:
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call void @main()
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ret void
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}
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attributes #0 = { convergent noinline nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }
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attributes #2 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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attributes #3 = { convergent norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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attributes #4 = { convergent }
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!llvm.module.flags = !{!0, !1, !2}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 4, !"dx.disable_optimizations", i32 1}
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!2 = !{i32 7, !"frame-pointer", i32 2}
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