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clang-p2996/llvm/test/CodeGen/SystemZ/vec-unpack-01.ll
Ulrich Weigand 4a4987be36 [SystemZ] Optimize vector zero/sign extensions 
Generate more efficient code for zero or sign extensions where
the source is a subvector generated via SHUFFLE_VECTOR.

Specifically, recognize patterns corresponding to (series of)
VECTOR UNPACK instructions, or the VECTOR SIGN EXTEND TO
DOUBLEWORD instruction.

As a special case, also handle zero or sign extensions of a
vector element to i128.

Fixes: https://github.com/llvm/llvm-project/issues/129576
Fixes: https://github.com/llvm/llvm-project/issues/129899
2025-03-15 18:28:44 +01:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
define <8 x i16> @f1(<16 x i8> %a) {
; CHECK-LABEL: f1:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuphb %v24, %v24
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%1 = sext <8 x i8> %0 to <8 x i16>
ret <8 x i16> %1
}
define <8 x i16> @f2(<16 x i8> %a) {
; CHECK-LABEL: f2:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuplb %v24, %v24
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%1 = sext <8 x i8> %0 to <8 x i16>
ret <8 x i16> %1
}
define <4 x i32> @f3(<8 x i16> %a) {
; CHECK-LABEL: f3:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuphh %v24, %v24
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%1 = sext <4 x i16> %0 to <4 x i32>
ret <4 x i32> %1
}
define <4 x i32> @f4(<8 x i16> %a) {
; CHECK-LABEL: f4:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuplhw %v24, %v24
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%1 = sext <4 x i16> %0 to <4 x i32>
ret <4 x i32> %1
}
define <4 x i32> @f5(<16 x i8> %a) {
; CHECK-LABEL: f5:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuphb %v0, %v24
; CHECK-NEXT: vuphh %v24, %v0
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%1 = sext <4 x i8> %0 to <4 x i32>
ret <4 x i32> %1
}
define <4 x i32> @f6(<16 x i8> %a) {
; CHECK-LABEL: f6:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuphb %v0, %v24
; CHECK-NEXT: vuplhw %v24, %v0
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
%1 = sext <4 x i8> %0 to <4 x i32>
ret <4 x i32> %1
}
define <4 x i32> @f7(<16 x i8> %a) {
; CHECK-LABEL: f7:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuplb %v0, %v24
; CHECK-NEXT: vuphh %v24, %v0
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <4 x i32> <i32 8, i32 9, i32 10, i32 11>
%1 = sext <4 x i8> %0 to <4 x i32>
ret <4 x i32> %1
}
define <4 x i32> @f8(<16 x i8> %a) {
; CHECK-LABEL: f8:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuplb %v0, %v24
; CHECK-NEXT: vuplhw %v24, %v0
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <4 x i32> <i32 12, i32 13, i32 14, i32 15>
%1 = sext <4 x i8> %0 to <4 x i32>
ret <4 x i32> %1
}
define <2 x i64> @f9(<4 x i32> %a) {
; CHECK-LABEL: f9:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuphf %v24, %v24
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 0, i32 1>
%1 = sext <2 x i32> %0 to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @f10(<4 x i32> %a) {
; CHECK-LABEL: f10:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuplf %v24, %v24
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <4 x i32> %a, <4 x i32> poison, <2 x i32> <i32 2, i32 3>
%1 = sext <2 x i32> %0 to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @f11(<8 x i16> %a) {
; CHECK-LABEL: f11:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuphh %v0, %v24
; CHECK-NEXT: vuphf %v24, %v0
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <2 x i32> <i32 0, i32 1>
%1 = sext <2 x i16> %0 to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @f12(<8 x i16> %a) {
; CHECK-LABEL: f12:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuphh %v0, %v24
; CHECK-NEXT: vuplf %v24, %v0
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <2 x i32> <i32 2, i32 3>
%1 = sext <2 x i16> %0 to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @f13(<8 x i16> %a) {
; CHECK-LABEL: f13:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuplhw %v0, %v24
; CHECK-NEXT: vuphf %v24, %v0
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <2 x i32> <i32 4, i32 5>
%1 = sext <2 x i16> %0 to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @f14(<8 x i16> %a) {
; CHECK-LABEL: f14:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuplhw %v0, %v24
; CHECK-NEXT: vuplf %v24, %v0
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <8 x i16> %a, <8 x i16> poison, <2 x i32> <i32 6, i32 7>
%1 = sext <2 x i16> %0 to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @f15(<16 x i8> %a) {
; CHECK-LABEL: f15:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuphb %v0, %v24
; CHECK-NEXT: vuphh %v0, %v0
; CHECK-NEXT: vuphf %v24, %v0
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 0, i32 1>
%1 = sext <2 x i8> %0 to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @f16(<16 x i8> %a) {
; CHECK-LABEL: f16:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuphb %v0, %v24
; CHECK-NEXT: vuphh %v0, %v0
; CHECK-NEXT: vuplf %v24, %v0
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 2, i32 3>
%1 = sext <2 x i8> %0 to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @f17(<16 x i8> %a) {
; CHECK-LABEL: f17:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuphb %v0, %v24
; CHECK-NEXT: vuplhw %v0, %v0
; CHECK-NEXT: vuphf %v24, %v0
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 4, i32 5>
%1 = sext <2 x i8> %0 to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @f18(<16 x i8> %a) {
; CHECK-LABEL: f18:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuphb %v0, %v24
; CHECK-NEXT: vuplhw %v0, %v0
; CHECK-NEXT: vuplf %v24, %v0
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 6, i32 7>
%1 = sext <2 x i8> %0 to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @f19(<16 x i8> %a) {
; CHECK-LABEL: f19:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuplb %v0, %v24
; CHECK-NEXT: vuphh %v0, %v0
; CHECK-NEXT: vuphf %v24, %v0
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 8, i32 9>
%1 = sext <2 x i8> %0 to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @f20(<16 x i8> %a) {
; CHECK-LABEL: f20:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuplb %v0, %v24
; CHECK-NEXT: vuphh %v0, %v0
; CHECK-NEXT: vuplf %v24, %v0
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 10, i32 11>
%1 = sext <2 x i8> %0 to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @f21(<16 x i8> %a) {
; CHECK-LABEL: f21:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuplb %v0, %v24
; CHECK-NEXT: vuplhw %v0, %v0
; CHECK-NEXT: vuphf %v24, %v0
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 12, i32 13>
%1 = sext <2 x i8> %0 to <2 x i64>
ret <2 x i64> %1
}
define <2 x i64> @f22(<16 x i8> %a) {
; CHECK-LABEL: f22:
; CHECK: # %bb.0: # %start
; CHECK-NEXT: vuplb %v0, %v24
; CHECK-NEXT: vuplhw %v0, %v0
; CHECK-NEXT: vuplf %v24, %v0
; CHECK-NEXT: br %r14
start:
%0 = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 14, i32 15>
%1 = sext <2 x i8> %0 to <2 x i64>
ret <2 x i64> %1
}
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