10d10102a4
During legalisation we can end up with some pretty strange nodes, like shifts of 0. We need to make sure we don't try to make long shifts of these, ending up with invalid assembly instructions. A long shift with a zero immediate actually encodes a shift by 32. Differential Revision: https://reviews.llvm.org/D67664 llvm-svn: 372839
49 lines
1.6 KiB
LLVM
49 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
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define void @_Z4loopPxS_iS_i(i64* %d) {
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; CHECK-LABEL: _Z4loopPxS_iS_i:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q0, [r0]
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; CHECK-NEXT: vmov r1, s2
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; CHECK-NEXT: vmov r2, s0
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; CHECK-NEXT: sxth r1, r1
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; CHECK-NEXT: sxth r2, r2
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; CHECK-NEXT: rsbs r1, r1, #0
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; CHECK-NEXT: rsbs r2, r2, #0
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; CHECK-NEXT: sxth r1, r1
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; CHECK-NEXT: sxth r2, r2
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; CHECK-NEXT: asr.w r12, r1, #31
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; CHECK-NEXT: asrs r3, r2, #31
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; CHECK-NEXT: strd r2, r3, [r0]
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; CHECK-NEXT: strd r1, r12, [r0, #8]
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; CHECK-NEXT: bx lr
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entry:
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%wide.load = load <2 x i64>, <2 x i64>* undef, align 8
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%0 = trunc <2 x i64> %wide.load to <2 x i32>
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%1 = shl <2 x i32> %0, <i32 16, i32 16>
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%2 = ashr exact <2 x i32> %1, <i32 16, i32 16>
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%3 = sub <2 x i32> %2, %0
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%4 = and <2 x i32> %3, <i32 7, i32 7>
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%5 = shl <2 x i32> %2, %4
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%6 = extractelement <2 x i32> %5, i32 0
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%7 = zext i32 %6 to i64
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%8 = select i1 false, i64 %7, i64 undef
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%9 = trunc i64 %8 to i16
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%10 = sub i16 0, %9
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%11 = sext i16 %10 to i64
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%12 = getelementptr inbounds i64, i64* %d, i64 undef
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store i64 %11, i64* %12, align 8
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%13 = extractelement <2 x i32> %5, i32 1
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%14 = zext i32 %13 to i64
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%15 = select i1 false, i64 %14, i64 undef
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%16 = trunc i64 %15 to i16
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%17 = sub i16 0, %16
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%18 = sext i16 %17 to i64
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%19 = or i32 0, 1
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%20 = sext i32 %19 to i64
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%21 = getelementptr inbounds i64, i64* %d, i64 %20
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store i64 %18, i64* %21, align 8
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ret void
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}
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