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clang-p2996/llvm/lib/Target/RISCV
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Alexander Romanov eb5e66b82d [RISCV] Change type of Zicbop prefetch operand to GPRMem (#139888) 
Prior to this commit PREFETCH_* instructions considered their operand
register to be a simple GPR which is not entirely correct as it is a
base address for possible prefetching operation (According to cmobase
v1.0.1)
2025-05-15 11:18:22 +03:00
..
AsmParser
[RISCV][MC] Add support for Q extension (#139369)
2025-05-15 10:51:06 +08:00
Disassembler
[RISCV][MC] Add support for Q extension (#139369)
2025-05-15 10:51:06 +08:00
GISel
[GlobalISel] Add a GISelValueTracker printing pass (#139687)
2025-05-14 11:05:04 +01:00
MCA
…
MCTargetDesc
[RISCV] Emit .note.gnu.property section when Zicfiss-based shadow stack is enabled (#127036)
2025-05-14 11:48:59 +08:00
TargetInfo
…
CMakeLists.txt
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCV.h
Register assembly printer passes (#138348)
2025-05-06 18:01:17 -07:00
RISCV.td
[RISCV] Add scheduler definitions for SpacemiT-X60 (#137343)
2025-05-06 13:30:57 -03:00
RISCVAsmPrinter.cpp
[RISCV] Emit .note.gnu.property section when Zicfiss-based shadow stack is enabled (#127036)
2025-05-14 11:48:59 +08:00
RISCVCallingConv.cpp
…
RISCVCallingConv.h
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RISCVCallingConv.td
…
RISCVCodeGenPrepare.cpp
[RISCV] Widen i1 AnyOf reductions (#134898)
2025-04-28 10:07:51 +08:00
RISCVCombine.td
…
RISCVConstantPoolValue.cpp
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RISCVConstantPoolValue.h
…
RISCVDeadRegisterDefinitions.cpp
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RISCVExpandAtomicPseudoInsts.cpp
[NFC][LLVM][RISCV] Cleanup pass initialization for RISCV (#134279)
2025-04-03 11:28:45 -07:00
RISCVExpandPseudoInsts.cpp
[RISCV] Use vsetvli instead of vlenb in Prologue/Epilogue (#113756)
2025-03-21 17:22:32 +08:00
RISCVFeatures.td
[RISCV][MC] Add support for Q extension (#139369)
2025-05-15 10:51:06 +08:00
RISCVFoldMemOffset.cpp
[RISCV] Clear kill flags after replaceRegWith in RISCVFoldMemOffset. (#136762)
2025-04-22 19:24:29 -07:00
RISCVFrameLowering.cpp
[RISCV] Fix Defs/Uses for SiFive CLIC Support (#137724)
2025-04-28 19:35:11 -07:00
RISCVFrameLowering.h
…
RISCVGatherScatterLowering.cpp
…
RISCVGISel.td
[Targets] Migrate from atomic_load_8/16/32/64 to atomic_load_nonext_8/16/32/64. NFC (#137428)
2025-04-28 09:26:34 -07:00
RISCVIndirectBranchTracking.cpp
…
RISCVInsertReadWriteCSR.cpp
…
RISCVInsertVSETVLI.cpp
[RISCV][InsertVSETVLI] Improve LMUL formatting in debug messages
2025-05-13 08:00:14 -07:00
RISCVInsertWriteVXRM.cpp
[RISCV][NFC] Convert some predicates to TIIPredicate (#129658)
2025-04-30 16:59:05 +08:00
RISCVInstrFormats.td
[RISCV] Support Load/Store Global assembler pseudos for Zilsd. (#134950)
2025-04-08 21:33:08 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
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RISCVInstrGISel.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfo.cpp
[RISCV] Use X9 instead of X27 in RISCVInstrInfo::insertIndirectBranch for RVE (#139214)
2025-05-09 08:41:14 -07:00
RISCVInstrInfo.h
[RISCV][TII] Add and use new hook to simplify/canonicalize instructions after MachineCopyPropagation (#137973)
2025-05-08 12:33:14 +01:00
RISCVInstrInfo.td
[RISCV][MC] Add support for Q extension (#139369)
2025-05-15 10:51:06 +08:00
RISCVInstrInfoA.td
[RISCV] Remove AND mask generated by ( zext ( atomic_load ) ) by replacing the load with zextload for orderings not stronger then monotonic. (#136502)
2025-04-28 08:35:51 -07:00
RISCVInstrInfoC.td
[RISCV] Add Andes XAndesperf (Andes Performance) extension. (#135110)
2025-04-28 17:23:51 +08:00
RISCVInstrInfoD.td
[RISCV] Add isel patterns to use Zilsd for f64 load/store for Zdinx on RV32. (#139935)
2025-05-14 12:19:38 -07:00
RISCVInstrInfoF.td
[RISCV][MC] Add support for Q extension (#139369)
2025-05-15 10:51:06 +08:00
RISCVInstrInfoM.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoQ.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVInstrInfoSFB.td
[RISCV] Fix the operand types for shift instructions in RISCVInstrInfoSFB.td. NFC
2025-03-30 22:38:26 -07:00
RISCVInstrInfoV.td
[RISCV][NFC] Fix the comment for VALUVINoVm (#132730)
2025-03-24 17:49:53 +01:00
RISCVInstrInfoVPseudos.td
[RISCV] Handle more (add x, C) -> (sub x, -C) cases (#138705)
2025-05-13 09:12:24 +02:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Handle more (add x, C) -> (sub x, -C) cases (#138705)
2025-05-13 09:12:24 +02:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Handle more (add x, C) -> (sub x, -C) cases (#138705)
2025-05-13 09:12:24 +02:00
RISCVInstrInfoXAndes.td
[RISCV] Support LLVM IR intrinsics for XAndesVPackFPH (#139860)
2025-05-15 10:21:27 +08:00
RISCVInstrInfoXCV.td
[RISCV] Check that both registers of a CV Reg-Reg memory address are GPRs. (#136079)
2025-04-17 12:39:40 -07:00
RISCVInstrInfoXMips.td
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
RISCVInstrInfoXqccmp.td
[RISCV] Prefer RegList over Rlist in assembler. NFC
2025-04-04 09:37:52 -07:00
RISCVInstrInfoXqci.td
[RISCV] Add a couple of more compress patterns for QC_E_ADDI (#139734)
2025-05-14 08:59:16 +05:30
RISCVInstrInfoXRivos.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoXSf.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoXTHead.td
[RISCV] Remove unneeded isel (sext_inreg $rs1, i32) isel pattern from RISCVInstrInfoXTHead.td. NFC
2025-05-13 09:06:04 -07:00
RISCVInstrInfoXVentana.td
…
RISCVInstrInfoXwch.td
…
RISCVInstrInfoZa.td
[RISCV] Rename some DecoderNamespaces and cleanup debug messages. NFC (#131409)
2025-03-17 12:49:08 -07:00
RISCVInstrInfoZalasr.td
[TableGen][SelectionDAG][GISel][RISCV] Support IsNonExtLoad for IsAtomic PatFrags. (#137401)
2025-04-25 15:45:43 -07:00
RISCVInstrInfoZb.td
[RISCV] Implement codegen for XAndesPerf lea instructions (#137925)
2025-05-12 10:41:53 +08:00
RISCVInstrInfoZc.td
[RISCV] Rename Spimm to StackAdj in most places. NFC
2025-04-04 12:49:09 -07:00
RISCVInstrInfoZclsd.td
[RISCV] Reuse existing tablegen classes for Zilsd/Zclsd. NFC (#134946)
2025-04-08 17:53:39 -07:00
RISCVInstrInfoZcmop.td
…
RISCVInstrInfoZfa.td
[RISCV][MC] Add Q support for Zfa (#139508)
2025-05-15 10:54:16 +08:00
RISCVInstrInfoZfbfmin.td
…
RISCVInstrInfoZfh.td
[NFC][RISCV] Remove extra space in RISCVInstrInfoZfh.td
2025-05-13 13:53:38 +08:00
RISCVInstrInfoZicbo.td
[RISCV] Change type of Zicbop prefetch operand to GPRMem (#139888)
2025-05-15 11:18:22 +03:00
RISCVInstrInfoZicfiss.td
…
RISCVInstrInfoZicond.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoZilsd.td
[RISCV] Lower i64 load/stores to ld/sd with Zilsd. (#139808)
2025-05-14 09:54:07 -07:00
RISCVInstrInfoZimop.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoZk.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrInfoZvfbf.td
…
RISCVInstrInfoZvk.td
[RISCV] Add vector hasAndNot to enable optimizations (#132438)
2025-03-26 10:40:00 +01:00
RISCVInstrInfoZvqdotq.td
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVInstrPredicates.td
[RISCV][NFC] Move VLDSX0Pred to RISCVInstrPredicates.td (#137938)
2025-05-12 12:05:50 +08:00
RISCVISelDAGToDAG.cpp
[RISCV] Lower i64 load/stores to ld/sd with Zilsd. (#139808)
2025-05-14 09:54:07 -07:00
RISCVISelDAGToDAG.h
[RISCV] Handle more (add x, C) -> (sub x, -C) cases (#138705)
2025-05-13 09:12:24 +02:00
RISCVISelLowering.cpp
[llvm] Construct SmallVector with ArrayRef (NFC) (#139992)
2025-05-14 22:30:38 -07:00
RISCVISelLowering.h
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVLandingPadSetup.cpp
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RISCVLateBranchOpt.cpp
[RISCV] Add late optimization pass for riscv (#133256)
2025-03-27 19:31:38 -03:00
RISCVLoadStoreOptimizer.cpp
[llvm] Remove redundant calls to std::unique_ptr<T>::get (NFC) (#138236)
2025-05-02 08:53:53 -07:00
RISCVMachineFunctionInfo.cpp
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
RISCVMachineFunctionInfo.h
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
RISCVMacroFusion.td
…
RISCVMakeCompressible.cpp
…
RISCVMergeBaseOffset.cpp
[RISCV] Don't fold offsets into auipc if offset is larger than the reference global variable. (#135297)
2025-04-11 16:12:19 -07:00
RISCVMoveMerger.cpp
…
RISCVOptWInstrs.cpp
[RISCV][NFC] Convert some predicates to TIIPredicate (#129658)
2025-04-30 16:59:05 +08:00
RISCVPfmCounters.td
…
RISCVPostRAExpandPseudoInsts.cpp
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RISCVProcessors.td
[RISCV] Add scheduler definitions for SpacemiT-X60 (#137343)
2025-05-06 13:30:57 -03:00
RISCVProfiles.td
[RISCV][NFC] Add Zicsr to profiles explicitly (#136134)
2025-04-18 10:59:32 +08:00
RISCVPushPopOptimizer.cpp
…
RISCVRedundantCopyElimination.cpp
[NFC][LLVM][RISCV] Cleanup pass initialization for RISCV (#134279)
2025-04-03 11:28:45 -07:00
RISCVRegisterInfo.cpp
[RISCV][MC] Add support for Q extension (#139369)
2025-05-15 10:51:06 +08:00
RISCVRegisterInfo.h
[RISCV][RegAlloc] Add getCSRFirstUseCost for RISC-V (#131349)
2025-03-20 15:20:04 -04:00
RISCVRegisterInfo.td
[RISCV][MC] Add support for Q extension (#139369)
2025-05-15 10:51:06 +08:00
RISCVSchedGenericOOO.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedMIPSP8700.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedRocket.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedSiFive7.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedSiFiveP400.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedSiFiveP500.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedSiFiveP600.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedSpacemitX60.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedSyntacoreSCR1.td
…
RISCVSchedSyntacoreSCR7.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedSyntacoreSCR345.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedTTAscalonD8.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSchedule.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVScheduleV.td
[RISCV][NFC] Move VLDSX0Pred to RISCVInstrPredicates.td (#137938)
2025-05-12 12:05:50 +08:00
RISCVScheduleXSf.td
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RISCVScheduleZb.td
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RISCVScheduleZvk.td
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RISCVSchedXiangShanNanHu.td
[RISCV][Scheduler] Add scheduler definitions for the Q extension (#139495)
2025-05-15 10:58:13 +08:00
RISCVSelectionDAGInfo.cpp
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVSelectionDAGInfo.h
[RISCV] TableGen-erate RISC-V SDNodes (#138381)
2025-05-09 12:36:59 -07:00
RISCVSubtarget.cpp
[RISCV] Fix xmipscmov extension name (#135647)
2025-04-15 23:17:03 +02:00
RISCVSubtarget.h
[RISCV] Enable prefetching writes (#130561)
2025-03-11 11:39:21 +08:00
RISCVSystemOperands.td
[RISCV] SiFive CLIC Support (#132481)
2025-04-25 17:12:27 -07:00
RISCVTargetMachine.cpp
[LV][EVL] Introduce the EVLIndVarSimplify Pass for EVL-vectorized loops (#131005)
2025-05-14 13:49:50 -07:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel
2025-03-29 11:08:13 -07:00
RISCVTargetObjectFile.h
[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel
2025-03-29 11:08:13 -07:00
RISCVTargetTransformInfo.cpp
[CostModel] Make Op0 and Op1 const in getVectorInstrCost. NFC (#137631)
2025-05-01 15:55:08 +01:00
RISCVTargetTransformInfo.h
[CostModel] Make Op0 and Op1 const in getVectorInstrCost. NFC (#137631)
2025-05-01 15:55:08 +01:00
RISCVVectorMaskDAGMutation.cpp
…
RISCVVectorPeephole.cpp
[RISCV][Peephole] Checking regclass compatibility in VMV (#138844)
2025-05-12 13:00:51 +08:00
RISCVVLOptimizer.cpp
[RISCV][VLOPT] Consider EMUL if it is unknown in EMULAndEEWAreEqual (#139670)
2025-05-14 18:03:35 +08:00
RISCVVMV0Elimination.cpp
[RISCV] Remove skipFunction from RISCVVMV0Elimination. (#136080)
2025-04-17 07:34:38 -07:00
RISCVZacasABIFix.cpp
…