sstwcw 369e8762b4 [clang-format] Stop comment disrupting indentation of Verilog ports ...

Before:

```
module x
    #( //
        parameter x)
    ( //
        input y);
endmodule
```

After:

```
module x
    #(//
      parameter x)
    (//
     input y);
endmodule
```

If the first line in a port or parameter list is not a comment, the
following lines will be aligned to the first line as intended:

```
module x
    #(parameter x1,
      parameter x2)
    (input y,
     input y2);
endmodule
```

Previously, the indentation would be changed to an extra continuation
indentation relative to the start of the parenthesis or the hash if
the first token inside the parentheses was a comment.  It is a feature
introduced in ddaa9be978.  The feature enabled one to insert a `//`
comment right after an opening parentheses to put the function
arguments on a new line with a small indentation regardless of how
long the function name is, like this:

```
someFunction(anotherFunction( // Force break.
    parameter));
```

People are unlikely to use this feature in a Verilog port list because
the formatter already puts the port list on its own lines.  A comment
at the start of a port list is probably a comment for the port on the
next line.

We also removed the space before the comment so that its indentation
would be same as that for a line comment anywhere else in the port
list.

Reviewed By: HazardyKnusperkeks

Differential Revision: https://reviews.llvm.org/D149562

2023-05-16 02:56:58 +00:00

113 KiB

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