In some rare corner cases where in between the div/rem pair there's a def of the second instruction's source (but a different vreg due to the combine's eqivalence checks), it will place the DIVREM at the first instruction's point, causing a use-before-def. There wasn't an obvious fix that stood out to me without doing more involved analysis than a combine should really be doing. Fixes issue #60516 I'm open to new suggestions on how to approach this, as I'm not too happy at bailing out here. It's not the first time we run into issues with value liveness that the DAG world isn't affected by. Differential Revision: https://reviews.llvm.org/D144336
214 KiB
214 KiB