9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
136 lines
4.7 KiB
LLVM
136 lines
4.7 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=tahiti -stop-after=instruction-select -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX6 %s
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; RUN: llc -mtriple=amdgcn -mcpu=fiji -stop-after=instruction-select -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8PLUS %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -stop-after=instruction-select -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8PLUS %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-vopd=0 -stop-after=instruction-select -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX8PLUS %s
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; GCN-LABEL: name: s_shl_i32
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; GCN: S_LSHL_B32
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define amdgpu_kernel void @s_shl_i32(ptr addrspace(1) %out, i32 %lhs, i32 %rhs) {
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%result = shl i32 %lhs, %rhs
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: name: v_shl_i32
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; GFX6: V_LSHL_B32_e32
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; GFX8PLUS: V_LSHLREV_B32_e32
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define amdgpu_kernel void @v_shl_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%b_ptr = getelementptr i32, ptr addrspace(1) %in, i32 %tid
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%a = load i32, ptr addrspace(1) %in
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%b = load i32, ptr addrspace(1) %b_ptr
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%result = shl i32 %a, %b
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: name: s_lshr_i32
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; GCN: S_LSHR_B32
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define amdgpu_kernel void @s_lshr_i32(ptr addrspace(1) %out, i32 %lhs, i32 %rhs) {
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%result = lshr i32 %lhs, %rhs
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: name: v_lshr_i32
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; GFX6: V_LSHR_B32_e32
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; GFX8PLUS: V_LSHRREV_B32_e64
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define amdgpu_kernel void @v_lshr_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%b_ptr = getelementptr i32, ptr addrspace(1) %in, i32 %tid
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%a = load i32, ptr addrspace(1) %in
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%b = load i32, ptr addrspace(1) %b_ptr
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%result = lshr i32 %a, %b
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: name: s_ashr_i32
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; GCN: S_ASHR_I32
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define amdgpu_kernel void @s_ashr_i32(ptr addrspace(1) %out, i32 %lhs, i32 %rhs) #0 {
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%result = ashr i32 %lhs, %rhs
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: name: v_ashr_i32
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; GFX6: V_ASHR_I32_e32
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; GFX8PLUS: V_ASHRREV_I32_e64
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define amdgpu_kernel void @v_ashr_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%b_ptr = getelementptr i32, ptr addrspace(1) %in, i32 %tid
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%a = load i32, ptr addrspace(1) %in
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%b = load i32, ptr addrspace(1) %b_ptr
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%result = ashr i32 %a, %b
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store i32 %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: name: s_shl_i64
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; GCN: S_LSHL_B64
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define amdgpu_kernel void @s_shl_i64(ptr addrspace(1) %out, i64 %lhs, i64 %rhs) {
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%result = shl i64 %lhs, %rhs
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store i64 %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: name: v_shl_i64
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; GFX6: V_LSHL_B64
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; GFX8: V_LSHLREV_B64
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define amdgpu_kernel void @v_shl_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%idx = zext i32 %tid to i64
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%b_ptr = getelementptr i64, ptr addrspace(1) %in, i64 %idx
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%a = load i64, ptr addrspace(1) %in
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%b = load i64, ptr addrspace(1) %b_ptr
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%result = shl i64 %a, %b
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store i64 %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: name: s_lshr_i64
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; GCN: S_LSHR_B64
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define amdgpu_kernel void @s_lshr_i64(ptr addrspace(1) %out, i64 %lhs, i64 %rhs) {
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%result = lshr i64 %lhs, %rhs
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store i64 %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: name: v_lshr_i64
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; GFX6: V_LSHR_B64
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; GFX8: V_LSHRREV_B64
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define amdgpu_kernel void @v_lshr_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%idx = zext i32 %tid to i64
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%b_ptr = getelementptr i64, ptr addrspace(1) %in, i64 %idx
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%a = load i64, ptr addrspace(1) %in
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%b = load i64, ptr addrspace(1) %b_ptr
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%result = lshr i64 %a, %b
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store i64 %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: name: s_ashr_i64
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; GCN: S_ASHR_I64
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define amdgpu_kernel void @s_ashr_i64(ptr addrspace(1) %out, i64 %lhs, i64 %rhs) {
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%result = ashr i64 %lhs, %rhs
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store i64 %result, ptr addrspace(1) %out
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ret void
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}
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; GCN-LABEL: name: v_ashr_i64
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; GFX6: V_ASHR_I64
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; GFX8: V_ASHRREV_I64
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define amdgpu_kernel void @v_ashr_i64(ptr addrspace(1) %out, ptr addrspace(1) %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%idx = zext i32 %tid to i64
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%b_ptr = getelementptr i64, ptr addrspace(1) %in, i64 %idx
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%a = load i64, ptr addrspace(1) %in
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%b = load i64, ptr addrspace(1) %b_ptr
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%result = ashr i64 %a, %b
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store i64 %result, ptr addrspace(1) %out
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x()
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