4a4987be36
Generate more efficient code for zero or sign extensions where the source is a subvector generated via SHUFFLE_VECTOR. Specifically, recognize patterns corresponding to (series of) VECTOR UNPACK instructions, or the VECTOR SIGN EXTEND TO DOUBLEWORD instruction. As a special case, also handle zero or sign extensions of a vector element to i128. Fixes: https://github.com/llvm/llvm-project/issues/129576 Fixes: https://github.com/llvm/llvm-project/issues/129899
80 lines
1.9 KiB
LLVM
80 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s
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define i128 @f1(<2 x i64> %a) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: vuplhg %v0, %v24
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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start:
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%0 = extractelement <2 x i64> %a, i32 0
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%1 = zext i64 %0 to i128
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ret i128 %1
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}
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define i128 @f2(<2 x i64> %a) {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: vupllg %v0, %v24
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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start:
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%0 = extractelement <2 x i64> %a, i32 1
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%1 = zext i64 %0 to i128
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ret i128 %1
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}
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define i128 @f3(<4 x i32> %a) {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: vuplhf %v0, %v24
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; CHECK-NEXT: vuplhg %v0, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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start:
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%0 = extractelement <4 x i32> %a, i32 0
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%1 = zext i32 %0 to i128
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ret i128 %1
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}
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define i128 @f4(<4 x i32> %a) {
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; CHECK-LABEL: f4:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: vupllf %v0, %v24
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; CHECK-NEXT: vuplhg %v0, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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start:
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%0 = extractelement <4 x i32> %a, i32 1
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%1 = zext i32 %0 to i128
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ret i128 %1
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}
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define i128 @f5(<4 x i32> %a) {
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; CHECK-LABEL: f5:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: vuplhf %v0, %v24
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; CHECK-NEXT: vupllg %v0, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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start:
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%0 = extractelement <4 x i32> %a, i32 2
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%1 = zext i32 %0 to i128
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ret i128 %1
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}
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define i128 @f6(<4 x i32> %a) {
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; CHECK-LABEL: f6:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: vupllf %v0, %v24
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; CHECK-NEXT: vupllg %v0, %v0
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; CHECK-NEXT: vst %v0, 0(%r2), 3
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; CHECK-NEXT: br %r14
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start:
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%0 = extractelement <4 x i32> %a, i32 3
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%1 = zext i32 %0 to i128
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ret i128 %1
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}
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