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clang-p2996/llvm/test/CodeGen/AMDGPU/GlobalISel
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Abinav Puthan Purayil 7f6489d0e3 [AMDGPU] Regenerate checks in a mir test
2022-05-09 13:28:09 +05:30
..
add_shl.ll
…
add.v2i16.ll
[AMDGPU] Switch PostRA sched to MachineSched
2021-09-14 15:11:27 -04:00
addo.ll
GlobalISel: Implement computeKnownBits for overflow bool results
2022-04-11 19:43:37 -04:00
amdgpu-irtranslator.ll
…
andn2.ll
[AMDGPU] Switch PostRA sched to MachineSched
2021-09-14 15:11:27 -04:00
artifact-combiner-anyext.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
artifact-combiner-asserts.ll
GlobalISel: Fix assert on unmerge to different element of casted vector
2022-01-19 10:13:31 -05:00
artifact-combiner-build-vector.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
artifact-combiner-concat-vectors.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
artifact-combiner-cse-leaves-dead-cast.mir
GlobalISel: Fix legalization error where CSE leaves behind dead defs
2022-01-18 17:04:40 -05:00
artifact-combiner-extract.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
artifact-combiner-sext.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
artifact-combiner-trunc.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
artifact-combiner-unmerge-values.mir
GlobalISel: Fix assert on unmerge to different element of casted vector
2022-01-19 10:13:31 -05:00
artifact-combiner-zext.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
ashr.ll
AMDGPU/GlobalISel: Fix legalization failure for s65 shifts
2022-01-17 10:04:41 -05:00
assert-align.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
atomic_load_local.ll
[AMDGPU] Add patterns for i8/i16 local atomic load/store
2021-10-18 11:23:10 +02:00
atomic_optimizations_mul_one.ll
[AMDGPU] Do not generate ELF symbols for the local branch target labels
2021-11-20 10:32:41 +05:30
atomic_store_local.ll
[AMDGPU] Add patterns for i8/i16 local atomic load/store
2021-10-18 11:23:10 +02:00
bool-legalization.ll
[AMDGPU] Do not generate ELF symbols for the local branch target labels
2021-11-20 10:32:41 +05:30
bswap.ll
[AArch64][GlobalISel] combine and + [la]sr => ubfx
2021-10-18 10:33:01 -07:00
buffer-schedule.ll
[AMDGPU][GISel] Fix MMO for raw/struct buffer access with non-constant offset
2021-07-26 14:27:30 +01:00
bug-legalization-artifact-combiner-dead-def.ll
GlobalISel: Fix infinite loop in legalization artifact combiner
2021-08-02 12:58:10 +02:00
bug-legalization-artifact-combiner-dead-def.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
call-outgoing-stack-args.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
clamp-fmed3-const-combine.ll
AMDGPU/GlobalISel: Add clamp combine
2021-12-03 12:49:39 +01:00
clamp-minmax-const-combine.ll
AMDGPU/GlobalISel: Add clamp combine
2021-12-03 12:49:39 +01:00
combine-add-nullptr.mir
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combine-add-to-ptradd.mir
AMDGPU/GlobalISel: Regenerate base test checks
2022-01-18 11:26:47 -05:00
combine-amdgpu-cvt-f32-ubyte.mir
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combine-ashr-narrow.mir
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combine-ext-legalizer.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
combine-fabs-fneg.mir
[GlobalISel] Combine fabs(fneg(x)) to fabs(x)
2021-10-05 13:43:39 +02:00
combine-fcanonicalize.mir
AMDGPU/GlobalISel: Do not fcanonicalize const splat padded with undef
2021-12-03 12:49:38 +01:00
combine-fma-add-ext-fma.ll
[AMDGPU][GlobalISel] Transform (fadd (fma x, y, (fpext (fmul u, v))), z) -> (fma x, y, (fma (fpext u), (fpext v), z))
2021-11-29 16:27:21 +01:00
combine-fma-add-ext-mul.ll
[AMDGPU][GlobalISel] Transform (fadd (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), z)
2021-11-29 16:27:21 +01:00
combine-fma-add-fma-mul.ll
[AMDGPU] Use v_fma_f16 on GFX10
2021-12-15 13:14:48 +00:00
combine-fma-add-mul-post-legalize.mir
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
combine-fma-add-mul-pre-legalize.mir
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
combine-fma-add-mul.ll
GlobalIsel: Fix fma combine when one of the operands comes from unmerge
2022-01-12 17:47:25 +01:00
combine-fma-sub-ext-mul.ll
[AMDGPU][GlobalISel] Transform (fsub (fpext (fmul x, y)), z) -> (fma (fpext x), (fpext y), (fneg z))
2021-11-29 16:27:22 +01:00
combine-fma-sub-ext-neg-mul.ll
[AMDGPU][GlobalISel] Transform (fsub (fpext (fneg (fmul x, y))), z) -> (fneg (fma (fpext x), (fpext y), z))
2021-11-29 16:27:22 +01:00
combine-fma-sub-mul.ll
[AMDGPU][GlobalISel] Transform (fsub (fmul x, y), z) -> (fma x, y, -z)
2021-11-29 16:27:22 +01:00
combine-fma-sub-neg-mul.ll
[AMDGPU][GlobalISel] Transform (fsub (fneg (fmul, x, y)), z) -> (fma (fneg x), y, (fneg z))
2021-11-29 16:27:22 +01:00
combine-fma-unmerge-values.mir
GlobalIsel: Fix fma combine when one of the operands comes from unmerge
2022-01-12 17:47:25 +01:00
combine-fold-binop-into-select.mir
GlobalISel: Constant fold G_PTR_ADD
2022-02-08 19:21:06 -05:00
combine-foldable-fneg.mir
[AMDGPU][GlobalISel] Fix insert point in FoldableFneg combine
2022-02-11 12:09:40 +01:00
combine-fsh.mir
[AMDGPU][GlobalISel] Remove the post ':' part of vreg operands in fsh combine tests.
2022-01-24 16:30:40 +05:30
combine-itofp.mir
[AMDGPU] Regenerate some MIR checks
2022-01-20 12:41:40 +00:00
combine-lshr-narrow.mir
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combine-or-redundant.mir
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combine-redundant-and.mir
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combine-redundant-neg.mir
[GlobalISel] Combine for eliminating redundant operand negations
2021-10-08 14:29:22 +02:00
combine-rot.mir
[AMDGPU][GlobalISel] Remove the post ':' part of vreg operands in fsh combine tests.
2022-01-24 16:30:40 +05:30
combine-rsq.ll
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
combine-rsq.mir
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
combine-sext-inreg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
combine-shift-imm-chain-illegal-types.mir
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
combine-shift-imm-chain-shlsat.mir
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combine-shift-imm-chain.ll
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combine-shift-of-shifted-logic-shlsat.mir
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combine-shift-of-shifted-logic.ll
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combine-shl-from-extend-narrow.postlegal.mir
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combine-shl-from-extend-narrow.prelegal.mir
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combine-shl-narrow.mir
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combine-short-clamp.ll
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combine-trunc-shl.mir
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combine-urem-pow-2.mir
[GlobalISel] Verify operand types for G_SHL, G_LSHR, G_ASHR
2021-12-21 11:59:33 +00:00
combine-zext-trunc.mir
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combiner-crash.ll
GlobalISel: Fix CSEMIRBuilder mishandling constant folds of vectors
2022-01-18 17:21:02 -05:00
constant-bus-restriction.ll
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crash-stack-address-O0.ll
GlobalISel: Always enable GISelKnownBits for InstructionSelect
2022-01-12 18:57:24 -05:00
cvt_f32_ubyte.ll
AMDGPU/GlobalISel: Stop using NarrowScalar/FewerElements for unaligned splitting
2021-12-20 18:07:11 -05:00
divergent-control-flow.ll
[StructurizeCFG] Clean up some boolean not instructions
2022-02-01 09:35:37 +00:00
dropped_debug_info_assert.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
dummy-target.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
dynamic-alloca-divergent.ll
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dynamic-alloca-uniform.ll
AMDGPU: Mark prolog/epilog SCC defs as dead
2021-11-15 21:35:06 -05:00
extractelement-stack-lower.ll
[AMDGPU] Do not reserve any VGPR for SGPR spills
2022-01-11 22:14:59 -08:00
extractelement.i8.ll
[AMDGPU] Set most sched model resource's BufferSize to one
2021-12-01 22:31:28 -08:00
extractelement.i16.ll
[AMDGPU] Switch PostRA sched to MachineSched
2021-09-14 15:11:27 -04:00
extractelement.i128.ll
[AMDGPU] Set most sched model resource's BufferSize to one
2021-12-01 22:31:28 -08:00
extractelement.ll
AMDGPU: Optimize out implicit kernarg argument allocation if unused
2021-12-04 10:38:25 -05:00
fdiv.f16.ll
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fdiv.f32.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
fdiv.f64.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
flat-scratch-init.gfx.ll
[AMDGPU] Make enable-flat-scratch a subtarget feature
2022-02-11 18:23:07 +01:00
flat-scratch-init.ll
[AMDGPU] flat scratch SVS addressing mode for gfx940
2022-03-14 15:23:36 -07:00
flat-scratch.ll
[AMDGPU] flat scratch SVS addressing mode for gfx940
2022-03-14 15:23:36 -07:00
floor.f64.ll
[AMDGPU] Switch PostRA sched to MachineSched
2021-09-14 15:11:27 -04:00
fma.ll
[AMDGPU] Use v_fma_f16 on GFX10
2021-12-15 13:14:48 +00:00
fmax_legacy.ll
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fmed3-min-max-const-combine.ll
AMDGPU/GlobalISel: Fix introducing f16 fmed3 for gfx8
2022-01-19 10:43:21 -05:00
fmed3.ll
[AMDGPU] Set most sched model resource's BufferSize to one
2021-12-01 22:31:28 -08:00
fmin_legacy.ll
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fmul.v2f16.ll
[GlobalISel] Combine for eliminating redundant operand negations
2021-10-08 14:29:22 +02:00
fp64-atomics-gfx90a.ll
[AMDGPU] Select no-return atomic intrinsics in tblgen
2022-04-22 09:37:40 +05:30
fp-atomics-gfx940.ll
[AMDGPU] new gfx940 fp atomics
2022-03-07 12:32:02 -08:00
fpow.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
frem.ll
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fshl.ll
AMDGPU/GlobalISel: Fix isVCC for uniform s1 with reg class on wave32
2022-04-21 16:12:04 +02:00
fshr.ll
AMDGPU/GlobalISel: Fix isVCC for uniform s1 with reg class on wave32
2022-04-21 16:12:04 +02:00
function-returns.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
function-returns.v2i65.ll
AMDGPU/GlobalISel: Add failing ABI lowering testcases
2022-01-17 09:38:35 -05:00
global-value.illegal.ll
AMDGPU/GlobalISel: Explicitly set -global-isel-abort in failure tests
2022-01-20 12:56:53 -05:00
global-value.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
hip.extern.shared.array.ll
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i1-copy.ll
AMDGPU/GlobalISel: Fix isVCC for uniform s1 with reg class on wave32
2022-04-21 16:12:04 +02:00
image-waterfall-loop-O0.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
implicit-kernarg-backend-usage-global-isel.ll
AMDGPU: Use the implicit kernargs for code object version 5
2022-03-17 14:12:36 -07:00
inline-asm-mismatched-size.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
inline-asm.ll
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insertelement-stack-lower.ll
AMDGPU: Don't consider whether amdgpu-flat-work-group-size was set
2021-10-22 16:23:50 -04:00
insertelement.i8.ll
[AMDGPU] Set most sched model resource's BufferSize to one
2021-12-01 22:31:28 -08:00
insertelement.i16.ll
GlobalISel: Constant fold G_PTR_ADD
2022-02-08 19:21:06 -05:00
insertelement.large.ll
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
insertelement.ll
[AMDGPU] Switch PostRA sched to MachineSched
2021-09-14 15:11:27 -04:00
inst-select-abs.mir
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inst-select-add.mir
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inst-select-add.s16.mir
[AMDGPU][GFX10] Enabled op_sel for v_add_nc_u16 and v_sub_nc_u16
2022-04-13 13:48:42 +03:00
inst-select-amdgcn.class.mir
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
2021-10-30 07:20:45 -04:00
inst-select-amdgcn.class.s16.mir
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
2021-10-30 07:20:45 -04:00
inst-select-amdgcn.cos.mir
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inst-select-amdgcn.cos.s16.mir
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inst-select-amdgcn.cvt.pk.i16.mir
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inst-select-amdgcn.cvt.pk.u16.mir
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inst-select-amdgcn.cvt.pknorm.i16.mir
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inst-select-amdgcn.cvt.pknorm.u16.mir
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inst-select-amdgcn.cvt.pkrtz.mir
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inst-select-amdgcn.ds.swizzle.mir
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inst-select-amdgcn.exp.mir
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inst-select-amdgcn.fmad.ftz.mir
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inst-select-amdgcn.fmed3.mir
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inst-select-amdgcn.fmed3.s16.mir
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inst-select-amdgcn.fract.mir
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inst-select-amdgcn.fract.s16.mir
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inst-select-amdgcn.groupstaticsize.mir
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inst-select-amdgcn.ldexp.mir
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inst-select-amdgcn.ldexp.s16.mir
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inst-select-amdgcn.mbcnt.lo.mir
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inst-select-amdgcn.mul.u24.mir
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inst-select-amdgcn.mulhi.i24.mir
[AMDGPU] Implement llvm.amdgcn.mulhi.[i,u]24 intrinsics.
2021-10-26 18:53:07 +05:30
inst-select-amdgcn.mulhi.u24.mir
[AMDGPU] Implement llvm.amdgcn.mulhi.[i,u]24 intrinsics.
2021-10-26 18:53:07 +05:30
inst-select-amdgcn.rcp.legacy.mir
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inst-select-amdgcn.rcp.mir
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inst-select-amdgcn.rcp.s16.mir
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inst-select-amdgcn.readfirstlane.mir
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inst-select-amdgcn.reloc.constant.mir
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inst-select-amdgcn.rsq.clamp.mir
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inst-select-amdgcn.rsq.legacy.mir
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inst-select-amdgcn.rsq.mir
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inst-select-amdgcn.rsq.s16.mir
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inst-select-amdgcn.s.barrier.mir
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inst-select-amdgcn.s.sendmsg.mir
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inst-select-amdgcn.sffbh.mir
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inst-select-amdgcn.sin.mir
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inst-select-amdgcn.sin.s16.mir
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inst-select-amdgpu-atomic-cmpxchg-flat.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
inst-select-amdgpu-atomic-cmpxchg-global.mir
[AMDGPU] Use COPY_TO_REGCLASS for buffer_atomic_cmpswap selection
2022-03-18 08:56:23 +05:30
inst-select-amdgpu-ffbh-u32.mir
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inst-select-amdgpu-ffbl-b32.mir
[AMDGPU][GlobalISel] Add G_AMDGPU_FFBL_B32
2021-08-06 09:40:48 +01:00
inst-select-amdgpu-wave-address.mir
AMDGPU/GlobalISel: Introduce pseudo to copy sp in call sequences
2022-01-19 10:13:31 -05:00
inst-select-and.mir
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
2021-10-30 07:20:45 -04:00
inst-select-anyext.mir
[AMDGPU][GlobalISel] Add more sign/zero/any-extension tests
2022-01-24 10:16:51 +00:00
inst-select-ashr.mir
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inst-select-ashr.s16.mir
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inst-select-ashr.v2s16.mir
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inst-select-atomic-cmpxchg-local.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
inst-select-atomic-cmpxchg-region.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
inst-select-atomicrmw-add-flat.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
inst-select-atomicrmw-add-global.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
inst-select-atomicrmw-fadd-local.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
inst-select-atomicrmw-fadd-region.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
inst-select-atomicrmw-xchg-local.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
inst-select-atomicrmw-xchg-region.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
inst-select-bitcast.mir
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inst-select-bitreverse.mir
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inst-select-br.mir
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inst-select-brcond.mir
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
2021-10-30 07:20:45 -04:00
inst-select-bswap.mir
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inst-select-build-vector-trunc.v2s16.mir
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inst-select-build-vector.mir
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inst-select-concat-vectors.mir
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inst-select-constant.mir
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
2021-10-30 07:20:45 -04:00
inst-select-copy.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-ctlz-zero-undef.mir
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inst-select-ctpop.mir
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inst-select-cttz-zero-undef.mir
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inst-select-extract-vector-elt.mir
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inst-select-extract.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
inst-select-fabs.mir
[AMDGPU] Enable fneg and fabs divergence-driven instruction selection.
2021-11-23 19:37:07 +03:00
inst-select-fadd.s16.mir
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inst-select-fadd.s32.mir
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inst-select-fadd.s64.mir
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inst-select-fcanonicalize.mir
[AMDGPU] Enable fneg and fabs divergence-driven instruction selection.
2021-11-23 19:37:07 +03:00
inst-select-fceil.mir
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inst-select-fceil.s16.mir
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inst-select-fcmp.mir
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
2021-10-30 07:20:45 -04:00
inst-select-fcmp.s16.mir
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
2021-10-30 07:20:45 -04:00
inst-select-fconstant.mir
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inst-select-fexp2.mir
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inst-select-ffloor.s16.mir
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inst-select-ffloor.s32.mir
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inst-select-ffloor.s64.mir
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inst-select-fma.s32.mir
[AMDGPU] Prefer v_fmac over v_fma only when no source modifiers are used
2021-09-21 11:57:45 +01:00
inst-select-fmad.s32.mir
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inst-select-fmaxnum-ieee.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-fmaxnum-ieee.s16.mir
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inst-select-fmaxnum-ieee.v2s16.mir
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inst-select-fmaxnum.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-fmaxnum.s16.mir
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inst-select-fmaxnum.v2s16.mir
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inst-select-fminnum-ieee.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-fminnum-ieee.s16.mir
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inst-select-fminnum-ieee.v2s16.mir
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inst-select-fminnum.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-fminnum.s16.mir
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inst-select-fminnum.v2s16.mir
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inst-select-fmul.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-fmul.v2s16.mir
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inst-select-fneg.mir
[AMDGPU] Enable fneg and fabs divergence-driven instruction selection.
2021-11-23 19:37:07 +03:00
inst-select-fptosi.mir
[AMDGPU] Enable fneg and fabs divergence-driven instruction selection.
2021-11-23 19:37:07 +03:00
inst-select-fptoui.mir
[AMDGPU] Enable fneg and fabs divergence-driven instruction selection.
2021-11-23 19:37:07 +03:00
inst-select-fract.f64.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
inst-select-frame-index.mir
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inst-select-freeze.mir
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inst-select-frint.mir
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inst-select-frint.s16.mir
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inst-select-fshr.mir
…
inst-select-i1-copy.mir
AMDGPU/GlobalISel: Fix isVCC for uniform s1 with reg class on wave32
2022-04-21 16:12:04 +02:00
inst-select-icmp.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-icmp.s16.mir
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
2021-10-30 07:20:45 -04:00
inst-select-icmp.s64.mir
…
inst-select-implicit-def.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-insert-vector-elt.mir
…
inst-select-insert.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
inst-select-intrinsic-trunc.mir
…
inst-select-intrinsic-trunc.s16.mir
…
inst-select-inttoptr.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-load-atomic-flat.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
inst-select-load-atomic-global.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-load-atomic-local.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
inst-select-load-constant.mir
[AMDGPU] Make v8i16/v8f16 legal
2022-01-24 11:51:08 -08:00
inst-select-load-flat.mir
[AMDGPU] Make v8i16/v8f16 legal
2022-01-24 11:51:08 -08:00
inst-select-load-global-saddr.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
inst-select-load-global.mir
[AMDGPU] Make v8i16/v8f16 legal
2022-01-24 11:51:08 -08:00
inst-select-load-global.s96.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
inst-select-load-local-128.mir
[AMDGPU] Fix handling of gfx10 LDS misaligned access bug
2022-04-07 15:08:29 -07:00
inst-select-load-local.mir
[AMDGPU] Fix handling of gfx10 LDS misaligned access bug
2022-04-07 15:08:29 -07:00
inst-select-load-private.mir
GlobalISel: Always enable GISelKnownBits for InstructionSelect
2022-01-12 18:57:24 -05:00
inst-select-load-smrd.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-lshr.mir
…
inst-select-lshr.s16.mir
…
inst-select-lshr.v2s16.mir
…
inst-select-merge-values.mir
…
inst-select-mul.mir
…
inst-select-or.mir
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
2021-10-30 07:20:45 -04:00
inst-select-pattern-add3.mir
…
inst-select-pattern-and-or.mir
…
inst-select-pattern-or3.mir
…
inst-select-pattern-smed3.mir
…
inst-select-pattern-smed3.s16.mir
…
inst-select-pattern-umed3.mir
…
inst-select-pattern-umed3.s16.mir
…
inst-select-pattern-xor3.mir
…
inst-select-phi.mir
…
inst-select-ptr-add.mir
…
inst-select-ptrmask.mir
AMDGPU/GlobalISel: Try to use s_and_b64 in ptrmask selection
2022-01-20 12:56:53 -05:00
inst-select-ptrtoint.mir
…
inst-select-returnaddress.mir
…
inst-select-sbfx.mir
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
inst-select-scalar-packed.xfail.mir
…
inst-select-select.mir
[AMDGPU] Enable fneg and fabs divergence-driven instruction selection.
2021-11-23 19:37:07 +03:00
inst-select-sext-inreg.mir
…
inst-select-sext.mir
[AMDGPU][GlobalISel] Add more sign/zero/any-extension tests
2022-01-24 10:16:51 +00:00
inst-select-sextload-local.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
inst-select-shl.mir
…
inst-select-shl.s16.mir
…
inst-select-shl.v2s16.mir
…
inst-select-shuffle-vector.v2s16.mir
…
inst-select-sitofp.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
inst-select-smax.mir
…
inst-select-smin.mir
…
inst-select-smulh.mir
…
inst-select-store-atomic-flat.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
inst-select-store-atomic-local.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
inst-select-store-flat.mir
[AMDGPU] Make v8i16/v8f16 legal
2022-01-24 11:51:08 -08:00
inst-select-store-global.mir
[AMDGPU] Make v8i16/v8f16 legal
2022-01-24 11:51:08 -08:00
inst-select-store-global.s96.mir
[AMDGPU] Remove unused GFX6 check lines
2022-01-27 10:48:32 +00:00
inst-select-store-local.mir
[AMDGPU] Fix handling of gfx10 LDS misaligned access bug
2022-04-07 15:08:29 -07:00
inst-select-store-private.mir
[AMDGPU] Reenable some disabled RUN lines
2022-02-15 11:28:24 +00:00
inst-select-sub.mir
…
inst-select-trunc.mir
…
inst-select-trunc.v2s16.mir
…
inst-select-uadde.gfx10.mir
…
inst-select-uadde.mir
…
inst-select-uaddo.mir
…
inst-select-ubfx.mir
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
inst-select-uitofp.mir
…
inst-select-umax.mir
…
inst-select-umin.mir
…
inst-select-umulh.mir
…
inst-select-unmerge-values.mir
…
inst-select-usube.gfx10.mir
…
inst-select-usube.mir
…
inst-select-usubo.mir
…
inst-select-xor.mir
GlobalISel/Utils: Use incoming regbank while constraining the superclasses
2021-10-30 07:20:45 -04:00
inst-select-zext.mir
[AMDGPU][GlobalISel] Add more sign/zero/any-extension tests
2022-01-24 10:16:51 +00:00
inst-select-zextload-local.mir
AMDGPU/GlobalISel: Regenerate mir test checks
2022-01-12 13:44:06 -05:00
irtranslator-amdgcn-sendmsg.ll
AMDGPU: Regenerate more mir test checks with -NEXT
2021-12-18 11:38:30 -05:00
irtranslator-amdgpu_kernel-system-sgprs.ll
…
irtranslator-amdgpu_kernel.ll
[AMDGPU] Simplify AMDGPUAnnotateUniformValues::visitLoadInst
2022-02-03 16:27:48 +00:00
irtranslator-amdgpu_ps.ll
AMDGPU: Regenerate more mir test checks with -NEXT
2021-12-18 11:38:30 -05:00
irtranslator-amdgpu_vs.ll
AMDGPU: Regenerate more mir test checks with -NEXT
2021-12-18 11:38:30 -05:00
irtranslator-assert-align.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-atomicrmw.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-call-abi-attribute-hints.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-call-implicit-args.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-call-non-fixed.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-call-return-values.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-call-sret.ll
AMDGPU/GlobalISel: Introduce pseudo to copy sp in call sequences
2022-01-19 10:13:31 -05:00
irtranslator-call.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-constant-fold-vector-op.ll
GlobalISel: Fix CSEMIRBuilder mishandling constant folds of vectors
2022-01-18 17:21:02 -05:00
irtranslator-constantexpr.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-constrained-fp.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-fast-math-flags.ll
…
irtranslator-fence.ll
AMDGPU: Regenerate more mir test checks with -NEXT
2021-12-18 11:38:30 -05:00
irtranslator-fixed-function-abi-vgpr-args.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-function-args.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-function-args.v2i65.ll
AMDGPU/GlobalISel: Add failing ABI lowering testcases
2022-01-17 09:38:35 -05:00
irtranslator-getelementptr.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-indirect-call.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-inline-asm.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-memory-intrinsics.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-metadata.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-non-integral-address-spaces.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-ptrmask.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-readnone-intrinsic-callsite.ll
…
irtranslator-sat.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-sibling-call.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
irtranslator-struct-return-intrinsics.ll
AMDGPU: Regenerate more mir test checks with -NEXT
2021-12-18 11:38:30 -05:00
irtranslator-tail-call.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
lds-global-non-entry-func.ll
AMDGPU: Enable fixed function ABI by default
2021-12-04 10:49:18 -05:00
lds-global-value.ll
[AMDGPU] Set most sched model resource's BufferSize to one
2021-12-01 22:31:28 -08:00
lds-misaligned-bug.ll
[AMDGPU] Fix handling of gfx10 LDS misaligned access bug
2022-04-07 15:08:29 -07:00
lds-relocs.ll
…
lds-size.ll
…
lds-zero-initializer.ll
[AMDGPU] Legalize initialized LDS variables
2021-09-23 22:53:20 -04:00
legalize-add.mir
AMDGPU/GlobalISel: Regenerate test checks
2021-12-21 10:57:46 -05:00
legalize-addrspacecast.mir
AMDGPU: Avoid null check during addrspacecast lowering
2022-01-10 13:27:39 -05:00
legalize-amdgcn.if-invalid.mir
…
legalize-amdgcn.if.xfail.mir
…
legalize-amdgcn.rsq.clamp.mir
…
legalize-amdgcn.wavefrontsize.mir
…
legalize-amdgcn.workitem.id.mir
AMDGPU: Directly implement computeKnownBits for workitem intrinsics
2022-04-22 10:49:50 -04:00
legalize-and.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-anyext.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-ashr.mir
AMDGPU/GlobalISel: Fix legalization failure for s65 shifts
2022-01-17 10:04:41 -05:00
legalize-atomic-cmpxchg-with-success.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-atomic-cmpxchg.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-atomicrmw-add.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-atomicrmw-and.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-atomicrmw-fadd-global.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-atomicrmw-fadd-local.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-atomicrmw-max.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-atomicrmw-min.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-atomicrmw-nand.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-atomicrmw-or.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-atomicrmw-sub.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-atomicrmw-umax.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-atomicrmw-umin.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-atomicrmw-xchg-flat.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-atomicrmw-xchg.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-atomicrmw-xor.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-bitcast.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-bitreverse.mir
AMDGPU/GlobalISel: Regenerate base test checks
2022-01-18 11:26:47 -05:00
legalize-block-addr.mir
…
legalize-brcond.mir
[GlobalISel] Improve elimination of dead instructions in legalizer
2021-09-20 13:00:58 +02:00
legalize-bswap.mir
[GlobalISel] Improve elimination of dead instructions in legalizer
2021-09-20 13:00:58 +02:00
legalize-build-vector-trunc.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-build-vector.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-build-vector.s16.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-concat-vectors.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-constant.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-ctlz-zero-undef.mir
AMDGPU/GlobalISel: Regenerate base test checks
2022-01-18 11:26:47 -05:00
legalize-ctlz.mir
AMDGPU/GlobalISel: Regenerate base test checks
2022-01-18 11:26:47 -05:00
legalize-ctpop.mir
AMDGPU/GlobalISel: Fix legalize failure on i65 ctpop
2022-01-19 10:26:28 -05:00
legalize-cttz-zero-undef.mir
AMDGPU/GlobalISel: Regenerate base test checks
2022-01-18 11:26:47 -05:00
legalize-cttz.mir
AMDGPU/GlobalISel: Regenerate base test checks
2022-01-18 11:26:47 -05:00
legalize-extract-vector-elt.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-extract.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-fabs.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-fadd.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-fcanonicalize.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-fceil.mir
AMDGPU/GlobalISel: Fix custom legalizatation for fceil
2022-01-13 14:29:30 +01:00
legalize-fcmp.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-fconstant.mir
…
legalize-fcopysign.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-fcos.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-fdiv.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-fexp2.mir
…
legalize-fexp.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-ffloor.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-flog2.mir
…
legalize-flog10.mir
…
legalize-flog.mir
…
legalize-fma.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-fmad.s16.mir
…
legalize-fmad.s32.mir
…
legalize-fmad.s64.mir
…
legalize-fmaxnum.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-fminnum.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-fmul.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-fneg.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-fpext.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-fpow.mir
…
legalize-fpowi.mir
…
legalize-fptosi.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-fptoui.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-fptrunc.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-freeze.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-frint.mir
[NFC][AMDGPU][GlobalISel] Fix some legalizer tests
2021-11-17 14:25:15 +01:00
legalize-fshl.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-fshr.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-fsin.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-fsqrt.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-fsub.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-icmp.mir
[GlobalISel] Improve elimination of dead instructions in legalizer
2021-09-20 13:00:58 +02:00
legalize-implicit-def-s1025.mir
[GlobalISel] Improve elimination of dead instructions in legalizer
2021-09-20 13:00:58 +02:00
legalize-implicit-def.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-insert-vector-elt.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-insert.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-intrinsic-amdgcn-fdiv-fast.mir
…
legalize-intrinsic-round.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-intrinsic-trunc.mir
[NFC][AMDGPU][GlobalISel] Fix some legalizer tests
2021-11-17 14:25:15 +01:00
legalize-inttoptr.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-jump-table.mir
…
legalize-llvm.amdgcn.image.atomic.dim.a16.ll
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-llvm.amdgcn.image.dim.a16.ll
[GlobalISel] Improve elimination of dead instructions in legalizer
2021-09-20 13:00:58 +02:00
legalize-llvm.amdgcn.image.load.2d.d16.ll
AMDGPU/GlobalISel: Explicitly track d16 for image legalization
2022-01-10 14:25:14 -05:00
legalize-llvm.amdgcn.image.load.2d.ll
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-llvm.amdgcn.image.load.2darraymsaa.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-llvm.amdgcn.image.load.3d.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
legalize-llvm.amdgcn.image.sample.a16.ll
[AMDGPU] Fixes in ISelDAG path and GlobalISel path for 'bias' operand with A16 bit on
2021-12-17 16:11:51 +05:30
legalize-llvm.amdgcn.image.sample.g16.ll
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-llvm.amdgcn.image.store.2d.d16.ll
AMDGPU/GlobalISel: Explicitly track d16 for image legalization
2022-01-10 14:25:14 -05:00
legalize-llvm.amdgcn.s.buffer.load.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-load-constant-32bit.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-load-constant.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-load-flat.mir
AMDGPU/GlobalISel: Fix assertions on legalize queries with huge align
2022-01-12 18:21:44 -05:00
legalize-load-global.mir
[AMDGPU] Remove unused CI check lines
2022-01-27 10:53:42 +00:00
legalize-load-local.mir
[AMDGPU] Fix handling of gfx10 LDS misaligned access bug
2022-04-07 15:08:29 -07:00
legalize-load-memory-metadata.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-load-private.mir
AMDGPU/GlobalISel: Fix test not matching test name
2022-01-17 09:38:35 -05:00
legalize-lshr.mir
AMDGPU/GlobalISel: Fix legalization failure for s65 shifts
2022-01-17 10:04:41 -05:00
legalize-memcpy.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-memcpyinline.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-memmove.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-memset.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-merge-values-build-vector.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-merge-values.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-mul.mir
AMDGPU/GISel: Update some MIR tests to reduce future churn
2022-05-03 07:08:56 -05:00
legalize-or.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-phi.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-ptr-add.mir
AMDGPU/GlobalISel: Regenerate test checks
2021-12-21 10:57:46 -05:00
legalize-ptrmask.mir
AMDGPU/GlobalISel: Regenerate test checks
2021-12-21 10:57:46 -05:00
legalize-ptrtoint.mir
AMDGPU/GlobalISel: Regenerate test checks
2021-12-21 10:57:46 -05:00
legalize-rotl-rotr.mir
[AMDGPU][GlobalISel] Legalization of G_ROTL and G_ROTR
2021-09-07 16:33:24 +02:00
legalize-sadde.mir
[AMDGPU][GlobalISel] Scalarize add/sub with overflow ops in the legalizer
2022-03-31 21:46:34 +05:30
legalize-saddo.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-saddsat.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-sbfx.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-sdiv.mir
AMDGPU/GISel: Update some MIR tests to reduce future churn
2022-05-03 07:08:56 -05:00
legalize-select.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-sext-inreg.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-sext.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-sextload-constant-32bit.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-sextload-flat.mir
[AMDGPU] Fix some confusing check prefixes. NFC.
2022-03-09 17:05:49 +00:00
legalize-sextload-global.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-sextload-local.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-sextload-private.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-shl.mir
AMDGPU/GlobalISel: Fix legalization failure for s65 shifts
2022-01-17 10:04:41 -05:00
legalize-shuffle-vector.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-shuffle-vector.s16.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-sitofp.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-smax.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-smin.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-smulh.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-smulo.mir
[GlobalISel] Improve elimination of dead instructions in legalizer
2021-09-20 13:00:58 +02:00
legalize-srem.mir
AMDGPU/GISel: Update some MIR tests to reduce future churn
2022-05-03 07:08:56 -05:00
legalize-sshlsat.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-ssube.mir
[AMDGPU][GlobalISel] Scalarize add/sub with overflow ops in the legalizer
2022-03-31 21:46:34 +05:30
legalize-ssubo.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-ssubsat.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-store-global.mir
[AMDGPU] Update MachineMemOperands syntax in commented out tests
2022-01-27 10:56:35 +00:00
legalize-store.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-sub.mir
AMDGPU/GlobalISel: Regenerate test checks
2021-12-21 10:57:46 -05:00
legalize-trunc.mir
AMDGPU/GlobalISel: Regenerate base test checks
2022-01-18 11:26:47 -05:00
legalize-uadde.mir
[AMDGPU][GlobalISel] Scalarize add/sub with overflow ops in the legalizer
2022-03-31 21:46:34 +05:30
legalize-uaddo.mir
[AMDGPU][GlobalISel] Scalarize add/sub with overflow ops in the legalizer
2022-03-31 21:46:34 +05:30
legalize-uaddsat.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-ubfx.mir
GlobalISel: Regen vector mir tests, add tests for vector arg lowering
2021-12-23 14:30:01 +01:00
legalize-udiv.mir
AMDGPU/GISel: Update some MIR tests to reduce future churn
2022-05-03 07:08:56 -05:00
legalize-uitofp.mir
[GlobalISel] Avoid creating COPY in LegalizationArtifactCombiner
2021-08-24 11:09:56 +02:00
legalize-umax.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-umin.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-umulh.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-umulo.mir
AMDGPU/GISel: Update some MIR tests to reduce future churn
2022-05-03 07:08:56 -05:00
legalize-unmerge-values.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-urem.mir
AMDGPU/GISel: Update some MIR tests to reduce future churn
2022-05-03 07:08:56 -05:00
legalize-ushlsat.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-usube.mir
[AMDGPU][GlobalISel] Scalarize add/sub with overflow ops in the legalizer
2022-03-31 21:46:34 +05:30
legalize-usubo.mir
[AMDGPU][GlobalISel] Scalarize add/sub with overflow ops in the legalizer
2022-03-31 21:46:34 +05:30
legalize-usubsat.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-vector-args-gfx7.mir
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
legalize-vector-args-gfx8-plus.mir
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
legalize-xor.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-zext.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
legalize-zextload-constant-32bit.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-zextload-flat.mir
[AMDGPU] Fix some confusing check prefixes. NFC.
2022-03-09 17:05:49 +00:00
legalize-zextload-global.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-zextload-local.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
legalize-zextload-private.mir
AMDGPU: Regenerate some mir test checks with -NEXT
2021-12-18 10:46:15 -05:00
llvm.abs.ll
GlobalISel: Implement computeKnownBits for overflow bool results
2022-04-11 19:43:37 -04:00
llvm.amdgcn.atomic.dec.ll
[AMDGPU] Set most sched model resource's BufferSize to one
2021-12-01 22:31:28 -08:00
llvm.amdgcn.atomic.inc.ll
[AMDGPU] Set most sched model resource's BufferSize to one
2021-12-01 22:31:28 -08:00
llvm.amdgcn.ballot.i32.ll
AMDGPU: Add codegen test for ctpop(ballot(x))
2022-04-08 15:00:05 -05:00
llvm.amdgcn.ballot.i64.ll
AMDGPU: Add codegen test for ctpop(ballot(x))
2022-04-08 15:00:05 -05:00
llvm.amdgcn.dispatch.id.ll
[CodeGen] Remove unneeded regex escaping in FileCheck patterns. NFC.
2022-02-18 16:10:56 +00:00
llvm.amdgcn.dispatch.ptr.ll
…
llvm.amdgcn.div.fmas.ll
AMDGPU: Stop reserving 36-bytes before kernel arguments for amdpal
2022-01-20 12:12:05 -05:00
llvm.amdgcn.div.scale.ll
[AMDGPU] Set most sched model resource's BufferSize to one
2021-12-01 22:31:28 -08:00
llvm.amdgcn.ds.append.ll
…
llvm.amdgcn.ds.consume.ll
…
llvm.amdgcn.ds.fadd.ll
…
llvm.amdgcn.ds.fmax.ll
[AMDGPU] Regenerate checks in a mir test
2022-05-09 13:28:09 +05:30
llvm.amdgcn.ds.fmin.ll
…
llvm.amdgcn.ds.gws.barrier.ll
…
llvm.amdgcn.ds.gws.init.ll
…
llvm.amdgcn.ds.gws.sema.br.ll
…
llvm.amdgcn.ds.gws.sema.release.all.ll
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.ds.gws.sema.v.ll
…
llvm.amdgcn.ds.ordered.add.gfx10.ll
…
llvm.amdgcn.ds.ordered.add.ll
…
llvm.amdgcn.ds.ordered.swap.ll
…
llvm.amdgcn.end.cf.i32.ll
[AMDGPU] Do not generate ELF symbols for the local branch target labels
2021-11-20 10:32:41 +05:30
llvm.amdgcn.end.cf.i64.ll
[AMDGPU] Do not generate ELF symbols for the local branch target labels
2021-11-20 10:32:41 +05:30
llvm.amdgcn.fdot2.ll
…
llvm.amdgcn.fmul.legacy.ll
[AMDGPU] Handle legacy multiply-accumulate opcodes in convertToThreeAddress
2022-03-01 16:58:00 +00:00
llvm.amdgcn.global.atomic.csub.ll
[AMDGPU] Add S_MOV_B64_IMM_PSEUDO for wide constants
2021-06-30 11:45:38 -07:00
llvm.amdgcn.global.atomic.fadd-with-ret.ll
…
llvm.amdgcn.global.atomic.fadd.ll
[AMDGPU] Select no-return atomic intrinsics in tblgen
2022-04-22 09:37:40 +05:30
llvm.amdgcn.icmp.ll
AMDGPU/GlobalISel: Fix assert on invalid cond code for llvm.amdgcn.icmp
2022-01-27 10:34:06 -05:00
llvm.amdgcn.if.break.i32.ll
…
llvm.amdgcn.if.break.i64.ll
…
llvm.amdgcn.image.atomic.dim.a16.ll
[AMDGPU] Switch PostRA sched to MachineSched
2021-09-14 15:11:27 -04:00
llvm.amdgcn.image.atomic.dim.ll
…
llvm.amdgcn.image.atomic.dim.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
llvm.amdgcn.image.gather4.a16.dim.ll
[AMDGPU] Fixes in ISelDAG path and GlobalISel path for 'bias' operand with A16 bit on
2021-12-17 16:11:51 +05:30
llvm.amdgcn.image.gather4.dim.ll
[AMDGPU] Switch PostRA sched to MachineSched
2021-09-14 15:11:27 -04:00
llvm.amdgcn.image.gather4.o.dim.ll
[AMDGPU] Switch PostRA sched to MachineSched
2021-09-14 15:11:27 -04:00
llvm.amdgcn.image.getresinfo.a16.ll
…
llvm.amdgcn.image.getresinfo.ll
…
llvm.amdgcn.image.load.1d.d16.ll
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
llvm.amdgcn.image.load.1d.ll
…
llvm.amdgcn.image.load.2d.ll
[AMDGPU] Switch PostRA sched to MachineSched
2021-09-14 15:11:27 -04:00
llvm.amdgcn.image.load.2darraymsaa.a16.ll
[AMDGPU] Switch PostRA sched to MachineSched
2021-09-14 15:11:27 -04:00
llvm.amdgcn.image.load.2darraymsaa.ll
[AMDGPU] Switch PostRA sched to MachineSched
2021-09-14 15:11:27 -04:00
llvm.amdgcn.image.load.3d.a16.ll
[AMDGPU] Switch PostRA sched to MachineSched
2021-09-14 15:11:27 -04:00
llvm.amdgcn.image.load.3d.ll
[AMDGPU] Switch PostRA sched to MachineSched
2021-09-14 15:11:27 -04:00
llvm.amdgcn.image.sample.g16.ll
[AMDGPU] Switch PostRA sched to MachineSched
2021-09-14 15:11:27 -04:00
llvm.amdgcn.image.store.2d.d16.ll
[AMDGPU] Switch PostRA sched to MachineSched
2021-09-14 15:11:27 -04:00
llvm.amdgcn.image.store.2d.ll
AMDGPU/GlobalISel: Explicitly track d16 for image legalization
2022-01-10 14:25:14 -05:00
llvm.amdgcn.implicit.buffer.ptr.ll
…
llvm.amdgcn.init.exec.ll
…
llvm.amdgcn.init.exec.wave32.ll
[AMDGPU] Add some more GFX10 GlobalISel test coverage
2021-12-03 13:40:27 +00:00
llvm.amdgcn.interp.p1.f16.ll
…
llvm.amdgcn.intersect_ray.ll
[GlobalISel] Fold or of shifts with constant amount to funnel shift.
2022-01-24 10:43:32 +05:30
llvm.amdgcn.is.private.ll
AMDGPU: Set up User SGPRs for queue_ptr only when necessary
2022-03-09 10:14:05 -08:00
llvm.amdgcn.is.shared.ll
AMDGPU: Set up User SGPRs for queue_ptr only when necessary
2022-03-09 10:14:05 -08:00
llvm.amdgcn.kernarg.segment.ptr.ll
AMDGPU: Assume all amdhsa kernarg passed implicit arguments by default
2021-12-04 10:38:25 -05:00
llvm.amdgcn.mfma.gfx90a.ll
[AMDGPU] Allow v_accvgpr_write to use SGPR on gfx90a
2022-03-22 13:52:29 -07:00
llvm.amdgcn.mov.dpp8.ll
…
llvm.amdgcn.mov.dpp.ll
[AMDGPU] Set most sched model resource's BufferSize to one
2021-12-01 22:31:28 -08:00
llvm.amdgcn.permlane.ll
…
llvm.amdgcn.queue.ptr.ll
…
llvm.amdgcn.raw.buffer.atomic.add.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
AMDGPU/GlobalISel: Directly diagnose return value use for FP atomics
2022-01-20 12:46:45 -05:00
llvm.amdgcn.raw.buffer.atomic.fadd.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.raw.buffer.load.format.f16.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.raw.buffer.load.format.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.raw.buffer.load.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.raw.buffer.store.format.f16.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.raw.buffer.store.format.f32.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.raw.buffer.store.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.raw.tbuffer.load.f16.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.raw.tbuffer.load.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.raw.tbuffer.store.f16.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.raw.tbuffer.store.i8.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.raw.tbuffer.store.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.rsq.clamp.ll
…
llvm.amdgcn.s.buffer.load.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.s.setreg.ll
…
llvm.amdgcn.s.sleep.ll
…
llvm.amdgcn.sbfe.ll
AMDGPU: Stop reserving 36-bytes before kernel arguments for amdpal
2022-01-20 12:12:05 -05:00
llvm.amdgcn.sdot2.ll
…
llvm.amdgcn.sdot4.ll
…
llvm.amdgcn.sdot8.ll
…
llvm.amdgcn.set.inactive.ll
AMDGPU: Don't clobber source register for V_SET_INACTIVE_*
2022-02-06 12:38:26 +08:00
llvm.amdgcn.softwqm.ll
…
llvm.amdgcn.struct.buffer.atomic.add.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
AMDGPU/GlobalISel: Directly diagnose return value use for FP atomics
2022-01-20 12:46:45 -05:00
llvm.amdgcn.struct.buffer.atomic.fadd.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.struct.buffer.load.format.f16.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.struct.buffer.load.format.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.struct.buffer.load.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.struct.buffer.store.format.f16.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.struct.buffer.store.format.f32.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.struct.buffer.store.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.struct.tbuffer.load.f16.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.struct.tbuffer.load.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
llvm.amdgcn.trig.preop.ll
[AMDGPU] Set most sched model resource's BufferSize to one
2021-12-01 22:31:28 -08:00
llvm.amdgcn.ubfe.ll
AMDGPU: Stop reserving 36-bytes before kernel arguments for amdpal
2022-01-20 12:12:05 -05:00
llvm.amdgcn.udot2.ll
…
llvm.amdgcn.udot4.ll
…
llvm.amdgcn.udot8.ll
…
llvm.amdgcn.update.dpp.ll
[AMDGPU] Set most sched model resource's BufferSize to one
2021-12-01 22:31:28 -08:00
llvm.amdgcn.workgroup.id.ll
…
llvm.amdgcn.workitem.id.ll
AMDGPU: Avoid enabling kernel workitem IDs with reqd_work_group_size
2022-01-18 13:52:04 -05:00
llvm.amdgcn.wqm.demote.ll
[AMDGPU] Do not generate ELF symbols for the local branch target labels
2021-11-20 10:32:41 +05:30
llvm.amdgcn.wqm.ll
…
llvm.amdgcn.wqm.vote.ll
…
llvm.amdgcn.writelane.ll
…
llvm.amdgcn.wwm.ll
…
llvm.memcpy.inline.ll
[AMDGPU][GlobalISel] Legalize memcpy family of intrinsics
2021-09-07 12:24:07 +02:00
llvm.memcpy.ll
AMDGPU/GlobalISel: Stop using NarrowScalar/FewerElements for unaligned splitting
2021-12-20 18:07:11 -05:00
llvm.memmove.ll
[AMDGPU] Do not generate ELF symbols for the local branch target labels
2021-11-20 10:32:41 +05:30
llvm.memset.ll
[AMDGPU] Do not generate ELF symbols for the local branch target labels
2021-11-20 10:32:41 +05:30
llvm.powi.ll
[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder
2021-07-27 11:27:58 +01:00
llvm.trap.ll
…
load-constant32bit.ll
AMDGPU/GlobalISel: Fix selection of constant 32-bit addrspace loads
2022-01-17 10:06:33 -05:00
load-constant.96.ll
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
load-local.96.ll
AMDGPU/GlobalISel: Stop using NarrowScalar/FewerElements for unaligned splitting
2021-12-20 18:07:11 -05:00
load-local.128.ll
[AMDGPU] Fix handling of gfx10 LDS misaligned access bug
2022-04-07 15:08:29 -07:00
load-unaligned.ll
[AMDGPU] Split unaligned 4 DWORD DS operations
2022-04-12 16:07:13 -07:00
localizer-wrong-insert-point.mir
GlobalISel: Fix insert point in localizer
2022-01-12 13:44:05 -05:00
localizer.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
lshr.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
memory-legalizer-atomic-fence.ll
…
merge-buffer-stores.ll
…
minmaxabs.ll
…
mubuf-global.ll
[AArch64][GlobalISel] Add a new reassociation for G_PTR_ADDs.
2021-09-14 23:57:41 -07:00
mul.ll
GlobalISel: Implement computeKnownBits for overflow bool results
2022-04-11 19:43:37 -04:00
mul.v2i16.ll
…
no-cse-nonlocal-convergent-instrs.mir
…
no-legalize-atomic.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
non-entry-alloca.ll
AMDGPU: Enable fixed function ABI by default
2021-12-04 10:49:18 -05:00
orn2.ll
[AMDGPU] Switch PostRA sched to MachineSched
2021-09-14 15:11:27 -04:00
postlegalizer-combiner-divrem.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
postlegalizer-combiner-sextload-from-sextinreg.mir
AMDGPU/GlobalISel: Add more tests for inreg extend + load combine
2022-04-11 19:43:37 -04:00
postlegalizer-combiner-unmerge-undef.mir
[AMDGPU][GlobalISel] Combine unmerge of undef
2022-01-26 12:30:36 +01:00
postlegalizer-combiner-zextload-from-and.mir
AMDGPU/GlobalISel: Add more tests for inreg extend + load combine
2022-04-11 19:43:37 -04:00
postlegalizercombiner-and.mir
[GlobalISel] Add a combine for and(load , mask) -> zextload
2021-09-16 10:42:46 +02:00
postlegalizercombiner-load-and-mask.mir
[AMDGPU] Regenerate some MIR checks
2022-01-20 12:41:40 +00:00
postlegalizercombiner-sbfx.mir
[AMDGPU] Regenerate MIR checks for G_[SU]BFX
2022-01-07 12:04:56 +00:00
postlegalizercombiner-select.mir
[AMDGPU][GlobalISel] Combine unmerge of undef
2022-01-26 12:30:36 +01:00
postlegalizercombiner-ubfx.mir
[GlobalISel] Use getPreferredShiftAmountTy in one more G_UBFX combine
2022-01-08 09:20:44 +00:00
prelegalizer-combiner-divrem.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
read_register.ll
…
readcyclecounter.ll
…
regbankcombiner-clamp-fmed3-const.mir
AMDGPU/GlobalISel: Add clamp combine
2021-12-03 12:49:39 +01:00
regbankcombiner-clamp-minmax-const.mir
AMDGPU/GlobalISel: Add clamp combine
2021-12-03 12:49:39 +01:00
regbankcombiner-fmed3-minmax-const.mir
AMDGPU/GlobalISel: Add floating point med3 combine
2021-12-03 12:49:39 +01:00
regbankcombiner-smed3.mir
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
regbankcombiner-umed3.mir
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
regbankselect-add.s16.mir
…
regbankselect-add.s32.mir
…
regbankselect-add.v2s16.mir
…
regbankselect-amdgcn-exp-compr.mir
…
regbankselect-amdgcn-exp.mir
…
regbankselect-amdgcn-s-buffer-load.mir
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
regbankselect-amdgcn.ballot.i64.mir
…
regbankselect-amdgcn.class.mir
…
regbankselect-amdgcn.cvt.pkrtz.mir
…
regbankselect-amdgcn.div.fmas.mir
…
regbankselect-amdgcn.div.scale.mir
…
regbankselect-amdgcn.ds.append.mir
…
regbankselect-amdgcn.ds.bpermute.mir
…
regbankselect-amdgcn.ds.consume.mir
…
regbankselect-amdgcn.ds.gws.init.mir
…
regbankselect-amdgcn.ds.gws.sema.v.mir
…
regbankselect-amdgcn.ds.ordered.add.mir
…
regbankselect-amdgcn.ds.ordered.swap.mir
…
regbankselect-amdgcn.ds.permute.mir
…
regbankselect-amdgcn.ds.swizzle.mir
…
regbankselect-amdgcn.else.32.mir
…
regbankselect-amdgcn.else.64.mir
[AMDGPU] Fix typo in RUN line
2022-03-31 16:23:40 +01:00
regbankselect-amdgcn.fcmp.mir
…
regbankselect-amdgcn.fmul.legacy.mir
…
regbankselect-amdgcn.groupstaticsize.mir
…
regbankselect-amdgcn.icmp.mir
…
regbankselect-amdgcn.image.load.1d.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
regbankselect-amdgcn.image.sample.1d.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
regbankselect-amdgcn.interp.mov.mir
…
regbankselect-amdgcn.interp.p1.f16.mir
…
regbankselect-amdgcn.interp.p1.mir
…
regbankselect-amdgcn.interp.p2.f16.mir
…
regbankselect-amdgcn.interp.p2.mir
…
regbankselect-amdgcn.kernarg.segment.ptr.mir
…
regbankselect-amdgcn.kill.mir
…
regbankselect-amdgcn.live.mask.mir
…
regbankselect-amdgcn.mfma.gfx90a.mir
…
regbankselect-amdgcn.mfma.gfx940.mir
[AMDGPU] Support gfx940 smfmac instructions
2022-03-24 12:40:42 -07:00
regbankselect-amdgcn.mfma.mir
…
regbankselect-amdgcn.ps.live.mir
…
regbankselect-amdgcn.raw.buffer.load.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
regbankselect-amdgcn.readfirstlane.mir
…
regbankselect-amdgcn.readlane.mir
…
regbankselect-amdgcn.s.buffer.load.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
regbankselect-amdgcn.s.buffer.load.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
…
regbankselect-amdgcn.s.getpc.mir
…
regbankselect-amdgcn.s.getreg.mir
…
regbankselect-amdgcn.s.memrealtime.mir
…
regbankselect-amdgcn.s.memtime.mir
…
regbankselect-amdgcn.s.sendmsg.mir
…
regbankselect-amdgcn.s.sendmsghalt.mir
[AMDGPU] Reenable some disabled RUN lines
2022-02-15 11:28:24 +00:00
regbankselect-amdgcn.struct.buffer.load.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
regbankselect-amdgcn.struct.buffer.store.ll
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
regbankselect-amdgcn.update.dpp.mir
…
regbankselect-amdgcn.wqm.demote.mir
…
regbankselect-amdgcn.wqm.mir
…
regbankselect-amdgcn.wqm.vote.mir
…
regbankselect-amdgcn.writelane.mir
…
regbankselect-amdgcn.wwm.mir
…
regbankselect-amdgpu-ffbh-u32.mir
[AMDGPU][GlobalISel] Better legalization of 32-bit ctlz/cttz
2021-08-06 09:40:48 +01:00
regbankselect-amdgpu-ffbl-b32.mir
[AMDGPU][GlobalISel] Better legalization of 32-bit ctlz/cttz
2021-08-06 09:40:48 +01:00
regbankselect-amdgpu-wave-address.mir
AMDGPU/GlobalISel: Introduce pseudo to copy sp in call sequences
2022-01-19 10:13:31 -05:00
regbankselect-and-s1.mir
…
regbankselect-and.mir
…
regbankselect-anyext.mir
…
regbankselect-ashr.mir
…
regbankselect-assert-align.mir
Reapply "Revert "GlobalISel: Add G_ASSERT_ALIGN hint instruction"
2022-01-24 09:26:52 -05:00
regbankselect-assert-zext.mir
GlobalISel: Relax handling of G_ASSERT_* with source register classes
2022-04-22 10:49:50 -04:00
regbankselect-atomic-cmpxchg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-add.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-and.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-fadd.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-max.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-min.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-or.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-sub.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-umax.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-umin.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-xchg.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-atomicrmw-xor.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-bitcast.mir
…
regbankselect-bitreverse.mir
…
regbankselect-block-addr.mir
…
regbankselect-brcond.mir
…
regbankselect-bswap.mir
…
regbankselect-build-vector-trunc.mir
…
regbankselect-build-vector-trunc.v2s16.mir
…
regbankselect-build-vector.mir
…
regbankselect-concat-vector.mir
…
regbankselect-constant.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-copy.mir
…
regbankselect-ctlz-zero-undef.mir
[AMDGPU][GlobalISel] Improve regbankselect for 64-bit VGPR ctlz_zero_undef/cttz_zero_undef
2021-08-06 09:40:48 +01:00
regbankselect-ctpop.mir
…
regbankselect-cttz-zero-undef.mir
[AMDGPU] Fix lowering of AMDGPU::G_CTTZ_ZERO_UNDEF to AMDGPU::G_AMDGPU_FFBL_B32
2021-08-17 18:09:57 +01:00
regbankselect-default.mir
…
regbankselect-dyn-stackalloc.mir
[AMDGPU] Reenable some disabled RUN lines
2022-02-15 11:28:24 +00:00
regbankselect-extract-vector-elt.mir
[AMDGPU] Reenable some disabled RUN lines
2022-02-15 11:28:24 +00:00
regbankselect-extract.mir
…
regbankselect-fabs.mir
…
regbankselect-fadd.mir
…
regbankselect-fcanonicalize.mir
…
regbankselect-fceil.mir
…
regbankselect-fcmp.mir
…
regbankselect-fexp2.mir
…
regbankselect-flog2.mir
…
regbankselect-fma.mir
…
regbankselect-fmul.mir
…
regbankselect-fneg.mir
…
regbankselect-fpext.mir
…
regbankselect-fptosi.mir
…
regbankselect-fptoui.mir
…
regbankselect-fptrunc.mir
…
regbankselect-frame-index.mir
…
regbankselect-freeze.mir
…
regbankselect-frint.mir
…
regbankselect-fshr.mir
…
regbankselect-fsqrt.mir
…
regbankselect-fsub.mir
…
regbankselect-icmp.mir
…
regbankselect-icmp.s16.mir
…
regbankselect-illegal-copy.mir
…
regbankselect-insert-vector-elt.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-insert.mir
…
regbankselect-intrinsic-trunc.mir
…
regbankselect-inttoptr.mir
…
regbankselect-load.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
regbankselect-lshr.mir
…
regbankselect-merge-values.mir
…
regbankselect-mul.mir
…
regbankselect-or.mir
…
regbankselect-phi-s1.mir
…
regbankselect-phi.mir
…
regbankselect-ptr-add.mir
…
regbankselect-ptrmask.mir
…
regbankselect-ptrtoint.mir
…
regbankselect-reg-sequence.mir
…
regbankselect-sadde.mir
…
regbankselect-sbfx.mir
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
regbankselect-select.mir
…
regbankselect-sext-inreg.mir
…
regbankselect-sext.mir
…
regbankselect-sextload.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-shl.mir
…
regbankselect-shuffle-vector.mir
…
regbankselect-sitofp.mir
…
regbankselect-smax.mir
…
regbankselect-smin.mir
…
regbankselect-smulh.mir
…
regbankselect-split-scalar-load-metadata.mir
[GlobalISel] Rework more/fewer elements for vectors
2021-12-23 14:30:02 +01:00
regbankselect-ssube.mir
…
regbankselect-sub.mir
…
regbankselect-trunc.mir
…
regbankselect-uadde.mir
…
regbankselect-uaddo.mir
…
regbankselect-ubfx.mir
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
2021-06-28 09:06:44 -04:00
regbankselect-uitofp.mir
…
regbankselect-umax.mir
…
regbankselect-umin.mir
…
regbankselect-umulh.mir
[AMDGPU] Reenable some disabled RUN lines
2022-02-15 11:28:24 +00:00
regbankselect-uniform-load-noclobber.mir
GlobalISel: Preserve memory type when reducing load/store width
2021-06-30 17:05:29 -04:00
regbankselect-unmerge-values.mir
…
regbankselect-usube.mir
…
regbankselect-usubo.mir
…
regbankselect-waterfall-agpr.mir
[AMDGPU] Split waterfall loop exec manipulation
2022-03-28 17:44:54 +09:00
regbankselect-widen-scalar-loads.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect-xor.mir
…
regbankselect-zext.mir
…
regbankselect-zextload.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
regbankselect.mir
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
ret.ll
…
roundeven.ll
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
saddsat.ll
GlobalISel: Implement computeKnownBits for overflow bool results
2022-04-11 19:43:37 -04:00
sbfx.ll
[AMDGPU] Regenerate G_[SU]BFX checks using some common prefixes
2022-01-07 12:04:56 +00:00
sdiv.i32.ll
[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder
2021-07-27 11:27:58 +01:00
sdiv.i64.ll
GlobalISel: Implement computeKnownBits for overflow bool results
2022-04-11 19:43:37 -04:00
sdivrem.ll
GlobalISel: Implement computeKnownBits for overflow bool results
2022-04-11 19:43:37 -04:00
shader-epilogs.ll
…
shl-ext-reduce.ll
AMDGPU: Stop reserving 36-bytes before kernel arguments for amdpal
2022-01-20 12:12:05 -05:00
shl.ll
AMDGPU/GlobalISel: Fix legalization failure for s65 shifts
2022-01-17 10:04:41 -05:00
shlN_add.ll
…
smed3.ll
AMDGPU/GlobalISel: Fix constant bus restriction errors for med3
2021-12-01 21:36:37 +01:00
smrd.ll
…
srem.i32.ll
[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder
2021-07-27 11:27:58 +01:00
srem.i64.ll
GlobalISel: Implement computeKnownBits for overflow bool results
2022-04-11 19:43:37 -04:00
ssubsat.ll
GlobalISel: Implement computeKnownBits for overflow bool results
2022-04-11 19:43:37 -04:00
store-local.96.ll
AMDGPU: Stop reserving 36-bytes before kernel arguments for amdpal
2022-01-20 12:12:05 -05:00
store-local.128.ll
[AMDGPU] Fix handling of gfx10 LDS misaligned access bug
2022-04-07 15:08:29 -07:00
subo.ll
GlobalISel: Implement computeKnownBits for overflow bool results
2022-04-11 19:43:37 -04:00
trunc.ll
…
uaddsat.ll
GlobalISel: Implement computeKnownBits for overflow bool results
2022-04-11 19:43:37 -04:00
ubfx.ll
[GlobalISel] Use getPreferredShiftAmountTy in one more G_UBFX combine
2022-01-08 09:20:44 +00:00
udiv.i32.ll
[GlobalISel] Combine G_UMULH x, (1 << c)) -> x >> (bitwidth - c)
2021-10-07 23:51:37 -07:00
udiv.i64.ll
GlobalISel: Implement computeKnownBits for overflow bool results
2022-04-11 19:43:37 -04:00
udivrem.ll
GlobalISel: Implement computeKnownBits for overflow bool results
2022-04-11 19:43:37 -04:00
umed3.ll
AMDGPU/GlobalISel: Fix constant bus restriction errors for med3
2021-12-01 21:36:37 +01:00
urem.i32.ll
[GlobalISel] Constant fold G_SITOFP and G_UITOFP in CSEMIRBuilder
2021-07-27 11:27:58 +01:00
urem.i64.ll
GlobalISel: Implement computeKnownBits for overflow bool results
2022-04-11 19:43:37 -04:00
usubsat.ll
GlobalISel: Implement computeKnownBits for overflow bool results
2022-04-11 19:43:37 -04:00
widen-i8-i16-scalar-loads.ll
[AMDGPU] Set MemoryVT for truncstores in tblgen.
2022-01-20 19:05:12 +05:30
write_register.ll
…
xnor.ll
GlobalISel: Implement computeKnownBits for overflow bool results
2022-04-11 19:43:37 -04:00
zextload.ll
AMDGPU/GlobalISel: Add some additional IR tests for zextload
2022-04-11 19:43:37 -04:00