18f9351223
The compiler was generating symbols in the final code object for local branch target labels. This bloats the code object, slows down the loader, and is only used to simplify disassembly. Use '--symbolize-operands' with llvm-objdump to improve readability of the branch target operands in disassembly. Fixes: SWDEV-312223 Reviewed By: scott.linder Differential Revision: https://reviews.llvm.org/D114273
126 lines
3.7 KiB
LLVM
126 lines
3.7 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -verify-machineinstrs -O0 < %s
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; GCN-LABEL: {{^}}test_loop:
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; GCN: s_and_b64 s[0:1], exec, -1
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; GCN: [[LABEL:.LBB[0-9]+_[0-9]+]]: ; %for.body{{$}}
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; GCN: ds_read_b32
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; GCN: ds_write_b32
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; GCN: s_cbranch_vccnz [[LABEL]]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_loop(float addrspace(3)* %ptr, i32 %n) nounwind {
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entry:
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%cmp = icmp eq i32 %n, -1
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br i1 %cmp, label %for.exit, label %for.body
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for.exit:
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ret void
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
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%vecload = load float, float addrspace(3)* %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, float addrspace(3)* %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br label %for.body
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}
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; GCN-LABEL: @loop_const_true
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; GCN: [[LABEL:.LBB[0-9]+_[0-9]+]]:
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; GCN: ds_read_b32
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; GCN: ds_write_b32
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; GCN: s_branch [[LABEL]]
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define amdgpu_kernel void @loop_const_true(float addrspace(3)* %ptr, i32 %n) nounwind {
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entry:
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br label %for.body
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for.exit:
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ret void
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
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%vecload = load float, float addrspace(3)* %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, float addrspace(3)* %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br i1 true, label %for.body, label %for.exit
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}
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; GCN-LABEL: {{^}}loop_const_false:
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; GCN-NOT: s_branch
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; GCN: s_endpgm
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define amdgpu_kernel void @loop_const_false(float addrspace(3)* %ptr, i32 %n) nounwind {
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entry:
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br label %for.body
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for.exit:
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ret void
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; XXX - Should there be an S_ENDPGM?
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
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%vecload = load float, float addrspace(3)* %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, float addrspace(3)* %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br i1 false, label %for.body, label %for.exit
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}
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; GCN-LABEL: {{^}}loop_const_undef:
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; GCN-NOT: s_branch
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; GCN: s_endpgm
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define amdgpu_kernel void @loop_const_undef(float addrspace(3)* %ptr, i32 %n) nounwind {
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entry:
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br label %for.body
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for.exit:
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ret void
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; XXX - Should there be an s_endpgm?
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
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%vecload = load float, float addrspace(3)* %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, float addrspace(3)* %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br i1 undef, label %for.body, label %for.exit
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}
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; GCN-LABEL: {{^}}loop_arg_0:
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; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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; GCN: v_cmp_eq_u32{{[^,]*}}, 1,
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; GCN: s_add_i32 s2, s0, 0x80
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; GCN: [[LOOPBB:.LBB[0-9]+_[0-9]+]]
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; GCN: _add_i32_e32 v0, vcc, 4, v0
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; GCN: s_cbranch_{{vccz|vccnz}} [[LOOPBB]]
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; GCN-NEXT: ; %bb.2
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @loop_arg_0(float addrspace(3)* %ptr, i32 %n) nounwind {
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entry:
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%cond = load volatile i1, i1 addrspace(3)* null
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br label %for.body
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for.exit:
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ret void
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
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%vecload = load float, float addrspace(3)* %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, float addrspace(3)* %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br i1 %cond, label %for.body, label %for.exit
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}
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