871418c5b0
Useful in showing Thumb2 and Thumb1 rev instructions as well as the arm already tested, as well as testing the more canonical llvm.bswap.i16 form.
184 lines
4.7 KiB
LLVM
184 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-ARM
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; RUN: llc -mtriple=thumbv6m-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-V6
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; RUN: llc -mtriple=thumbv7m-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-V7
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define i32 @test1(i32 %X) nounwind {
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; CHECK-LABEL: test1:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: rev16 r0, r0
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; CHECK-NEXT: bx lr
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%tmp1 = lshr i32 %X, 8
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%X15 = bitcast i32 %X to i32
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%tmp4 = shl i32 %X15, 8
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%tmp2 = and i32 %tmp1, 16711680
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%tmp5 = and i32 %tmp4, -16777216
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%tmp9 = and i32 %tmp1, 255
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%tmp13 = and i32 %tmp4, 65280
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%tmp6 = or i32 %tmp5, %tmp2
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%tmp10 = or i32 %tmp6, %tmp13
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%tmp14 = or i32 %tmp10, %tmp9
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ret i32 %tmp14
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}
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define i32 @test2(i32 %X) nounwind {
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; CHECK-LABEL: test2:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: revsh r0, r0
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; CHECK-NEXT: bx lr
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%tmp1 = lshr i32 %X, 8
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%tmp1.upgrd.1 = trunc i32 %tmp1 to i16
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%tmp3 = trunc i32 %X to i16
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%tmp2 = and i16 %tmp1.upgrd.1, 255
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%tmp4 = shl i16 %tmp3, 8
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%tmp5 = or i16 %tmp2, %tmp4
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%tmp5.upgrd.2 = sext i16 %tmp5 to i32
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ret i32 %tmp5.upgrd.2
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}
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; rdar://9147637
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define i32 @test3(i16 zeroext %a) nounwind {
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; CHECK-LABEL: test3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: revsh r0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = tail call i16 @llvm.bswap.i16(i16 %a)
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%1 = sext i16 %0 to i32
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ret i32 %1
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}
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declare i16 @llvm.bswap.i16(i16) nounwind readnone
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define i32 @test4(i16 zeroext %a) nounwind {
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; CHECK-LABEL: test4:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: revsh r0, r0
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; CHECK-NEXT: bx lr
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entry:
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%conv = zext i16 %a to i32
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%shr9 = lshr i16 %a, 8
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%conv2 = zext i16 %shr9 to i32
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%shl = shl nuw nsw i32 %conv, 8
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%or = or i32 %conv2, %shl
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%sext = shl i32 %or, 16
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%conv8 = ashr exact i32 %sext, 16
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ret i32 %conv8
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}
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; rdar://9609059
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define i32 @test5(i32 %i) nounwind readnone {
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; CHECK-ARM-LABEL: test5:
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; CHECK-ARM: @ %bb.0: @ %entry
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; CHECK-ARM-NEXT: revsh r0, r0
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; CHECK-ARM-NEXT: bx lr
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;
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; CHECK-V6-LABEL: test5:
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; CHECK-V6: @ %bb.0: @ %entry
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; CHECK-V6-NEXT: lsrs r1, r0, #8
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; CHECK-V6-NEXT: uxtb r1, r1
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; CHECK-V6-NEXT: lsls r0, r0, #24
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; CHECK-V6-NEXT: asrs r0, r0, #16
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; CHECK-V6-NEXT: adds r0, r0, r1
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; CHECK-V6-NEXT: bx lr
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;
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; CHECK-V7-LABEL: test5:
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; CHECK-V7: @ %bb.0: @ %entry
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; CHECK-V7-NEXT: revsh r0, r0
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; CHECK-V7-NEXT: bx lr
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entry:
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%shl = shl i32 %i, 24
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%shr = ashr exact i32 %shl, 16
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%shr23 = lshr i32 %i, 8
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%and = and i32 %shr23, 255
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%or = or i32 %shr, %and
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ret i32 %or
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}
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; rdar://9609108
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define i32 @test6(i32 %x) nounwind readnone {
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; CHECK-LABEL: test6:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: rev16 r0, r0
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; CHECK-NEXT: bx lr
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entry:
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%and = shl i32 %x, 8
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%shl = and i32 %and, 65280
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%and2 = lshr i32 %x, 8
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%shr11 = and i32 %and2, 255
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%shr5 = and i32 %and2, 16711680
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%shl9 = and i32 %and, -16777216
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%or = or i32 %shr5, %shl9
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%or6 = or i32 %or, %shr11
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%or10 = or i32 %or6, %shl
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ret i32 %or10
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}
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; rdar://9164521
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define i32 @test7(i32 %a) nounwind readnone {
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; CHECK-ARM-LABEL: test7:
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; CHECK-ARM: @ %bb.0: @ %entry
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; CHECK-ARM-NEXT: rev r0, r0
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; CHECK-ARM-NEXT: lsr r0, r0, #16
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; CHECK-ARM-NEXT: bx lr
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;
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; CHECK-V6-LABEL: test7:
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; CHECK-V6: @ %bb.0: @ %entry
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; CHECK-V6-NEXT: rev r0, r0
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; CHECK-V6-NEXT: lsrs r0, r0, #16
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; CHECK-V6-NEXT: bx lr
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;
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; CHECK-V7-LABEL: test7:
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; CHECK-V7: @ %bb.0: @ %entry
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; CHECK-V7-NEXT: rev r0, r0
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; CHECK-V7-NEXT: lsrs r0, r0, #16
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; CHECK-V7-NEXT: bx lr
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entry:
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%and = lshr i32 %a, 8
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%shr3 = and i32 %and, 255
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%and2 = shl i32 %a, 8
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%shl = and i32 %and2, 65280
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%or = or i32 %shr3, %shl
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ret i32 %or
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}
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define i32 @test8(i32 %a) nounwind readnone {
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; CHECK-LABEL: test8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: revsh r0, r0
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; CHECK-NEXT: bx lr
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entry:
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%and = lshr i32 %a, 8
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%shr4 = and i32 %and, 255
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%and2 = shl i32 %a, 8
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%or = or i32 %shr4, %and2
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%sext = shl i32 %or, 16
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%conv3 = ashr exact i32 %sext, 16
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ret i32 %conv3
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}
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; rdar://10750814
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define zeroext i16 @test9(i16 zeroext %v) nounwind readnone {
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; CHECK-LABEL: test9:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: rev16 r0, r0
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; CHECK-NEXT: bx lr
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entry:
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%conv = zext i16 %v to i32
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%shr4 = lshr i32 %conv, 8
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%shl = shl nuw nsw i32 %conv, 8
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%or = or i32 %shr4, %shl
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%conv3 = trunc i32 %or to i16
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ret i16 %conv3
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}
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define zeroext i16 @test10(i16 zeroext %v) nounwind readnone {
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; CHECK-LABEL: test10:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: rev16 r0, r0
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; CHECK-NEXT: bx lr
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entry:
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%conv3 = call i16 @llvm.bswap.i16(i16 %v)
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ret i16 %conv3
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}
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