1bf4bbc492
If we promote the ABS and then Expand in LegalizeDAG, then both the sra and the xor will have their inputs sign extended. This generates extra code on RISCV which lacks an i8 or i16 sign extend instructon. If we expand during type legalization, then only the sra will get its input sign extended. RISCV is able to combine this with the sra by doing a shift left followed by an sra. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D121664
27 lines
781 B
LLVM
27 lines
781 B
LLVM
; RUN: llc < %s -mtriple=wasm32-unknown-unknown | FileCheck %s
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; Regression test for PR41149.
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define void @mod() {
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; CHECK-LABEL: mod:
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; CHECK-NEXT: .functype mod () -> ()
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; CHECK: local.get 0
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: i32.load8_s 0
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; CHECK-NEXT: local.tee 0
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: i32.const 7
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; CHECK-NEXT: i32.shr_s
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; CHECK-NEXT: local.tee 0
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; CHECK-NEXT: i32.xor
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; CHECK-NEXT: local.get 0
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; CHECK-NEXT: i32.sub
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; CHECK-NEXT: i32.store8 0
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%tmp = load <4 x i8>, <4 x i8>* undef
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%tmp2 = icmp slt <4 x i8> %tmp, zeroinitializer
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%tmp3 = sub <4 x i8> zeroinitializer, %tmp
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%tmp4 = select <4 x i1> %tmp2, <4 x i8> %tmp3, <4 x i8> %tmp
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store <4 x i8> %tmp4, <4 x i8>* undef
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ret void
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}
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