1c8d7ea973
Requested SchedGroup pipelines may be non-trivial to satisify. A minimimal example is if the requested pipeline is {2 VMEM, 2 VALU, 2 VMEM} and the original order of SUnits is {VMEM, VALU, VMEM, VALU, VMEM}. Because of existing dependencies, the choice of which SchedGroup the middle VMEM goes into impacts how closely we are able to match the requested pipeline. It seems minimizing the degree of misfit (as measured by the number of edges we can't add) w.r.t the choice we make when mapping an instruction -> SchedGroup is an NP problem. This patch implements the PipelineSolver class which produces a solution for the defined problem for the sched_group_barrier mutation. The solver has both an exponential time exact algorithm and a greedy algorithm. The patch includes some controls which allows the user to select the greedy/exact algorithm.
Differential Revision: https://reviews.llvm.org/D130797
1126 lines
38 KiB
C++
1126 lines
38 KiB
C++
//===--- AMDGPUIGroupLP.cpp - AMDGPU IGroupLP ------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// \file This file defines a set of schedule DAG mutations that can be used to
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// override default scheduler behavior to enforce specific scheduling patterns.
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// They should be used in cases where runtime performance considerations such as
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// inter-wavefront interactions, mean that compile-time heuristics cannot
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// predict the optimal instruction ordering, or in kernels where optimum
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// instruction scheduling is important enough to warrant manual intervention.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUIGroupLP.h"
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#include "AMDGPUTargetMachine.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/ADT/BitmaskEnum.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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using namespace llvm;
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#define DEBUG_TYPE "igrouplp"
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namespace {
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static cl::opt<bool>
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EnableIGroupLP("amdgpu-igrouplp",
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cl::desc("Enable construction of Instruction Groups and "
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"their ordering for scheduling"),
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cl::init(false));
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static cl::opt<bool> EnableExactSolver(
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"amdgpu-igrouplp-exact-solver", cl::Hidden,
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cl::desc("Whether to use the exponential time solver to fit "
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"the instructions to the pipeline as closely as "
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"possible."),
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cl::init(false));
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static cl::opt<unsigned> CutoffForExact(
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"amdgpu-igrouplp-exact-solver-cutoff", cl::init(0), cl::Hidden,
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cl::desc("The maximum number of scheduling group conflicts "
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"which we attempt to solve with the exponential time "
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"exact solver. Problem sizes greater than this will"
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"be solved by the less accurate greedy algorithm. Selecting "
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"solver by size is superseded by manually selecting "
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"the solver (e.g. by amdgpu-igrouplp-exact-solver"));
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static cl::opt<uint64_t> MaxBranchesExplored(
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"amdgpu-igrouplp-exact-solver-max-branches", cl::init(0), cl::Hidden,
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cl::desc("The amount of branches that we are willing to explore with"
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"the exact algorithm before giving up."));
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static cl::opt<bool> UseCostHeur(
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"amdgpu-igrouplp-exact-solver-cost-heur", cl::init(true), cl::Hidden,
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cl::desc("Whether to use the cost heuristic to make choices as we "
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"traverse the search space using the exact solver. Defaulted "
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"to on, and if turned off, we will use the node order -- "
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"attempting to put the later nodes in the later sched groups. "
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"Experimentally, results are mixed, so this should be set on a "
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"case-by-case basis."));
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// Components of the mask that determines which instruction types may be may be
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// classified into a SchedGroup.
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enum class SchedGroupMask {
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NONE = 0u,
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ALU = 1u << 0,
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VALU = 1u << 1,
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SALU = 1u << 2,
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MFMA = 1u << 3,
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VMEM = 1u << 4,
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VMEM_READ = 1u << 5,
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VMEM_WRITE = 1u << 6,
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DS = 1u << 7,
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DS_READ = 1u << 8,
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DS_WRITE = 1u << 9,
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ALL = ALU | VALU | SALU | MFMA | VMEM | VMEM_READ | VMEM_WRITE | DS |
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DS_READ | DS_WRITE,
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LLVM_MARK_AS_BITMASK_ENUM(/* LargestFlag = */ ALL)
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};
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typedef DenseMap<SUnit *, SmallVector<int, 4>> SUnitsToCandidateSGsMap;
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// Classify instructions into groups to enable fine tuned control over the
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// scheduler. These groups may be more specific than current SchedModel
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// instruction classes.
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class SchedGroup {
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private:
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// Mask that defines which instruction types can be classified into this
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// SchedGroup. The instruction types correspond to the mask from SCHED_BARRIER
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// and SCHED_GROUP_BARRIER.
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SchedGroupMask SGMask;
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// Maximum number of SUnits that can be added to this group.
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Optional<unsigned> MaxSize;
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// SchedGroups will only synchronize with other SchedGroups that have the same
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// SyncID.
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int SyncID = 0;
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// SGID is used to map instructions to candidate SchedGroups
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int SGID;
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ScheduleDAGInstrs *DAG;
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const SIInstrInfo *TII;
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// Try to add and edge from SU A to SU B.
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bool tryAddEdge(SUnit *A, SUnit *B);
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// Use SGMask to determine whether we can classify MI as a member of this
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// SchedGroup object.
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bool canAddMI(const MachineInstr &MI) const;
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public:
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// Collection of SUnits that are classified as members of this group.
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SmallVector<SUnit *, 32> Collection;
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// Returns true if SU can be added to this SchedGroup.
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bool canAddSU(SUnit &SU) const;
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// Add DAG dependencies from all SUnits in this SchedGroup and this SU. If
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// MakePred is true, SU will be a predecessor of the SUnits in this
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// SchedGroup, otherwise SU will be a successor.
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void link(SUnit &SU, bool MakePred = false);
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// Add DAG dependencies and track which edges are added, and the count of
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// missed edges
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int link(SUnit &SU, bool MakePred,
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std::vector<std::pair<SUnit *, SUnit *>> &AddedEdges);
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// Add DAG dependencies from all SUnits in this SchedGroup and this SU.
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// Use the predicate to determine whether SU should be a predecessor (P =
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// true) or a successor (P = false) of this SchedGroup.
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void link(SUnit &SU, function_ref<bool(const SUnit *A, const SUnit *B)> P);
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// Add DAG dependencies such that SUnits in this group shall be ordered
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// before SUnits in OtherGroup.
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void link(SchedGroup &OtherGroup);
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// Returns true if no more instructions may be added to this group.
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bool isFull() const { return MaxSize && Collection.size() >= *MaxSize; }
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// Add SU to the SchedGroup.
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void add(SUnit &SU) {
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LLVM_DEBUG(dbgs() << "For SchedGroup with mask "
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<< format_hex((int)SGMask, 10, true) << " adding "
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<< *SU.getInstr());
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Collection.push_back(&SU);
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}
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// Remove last element in the SchedGroup
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void pop() { Collection.pop_back(); }
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// Identify and add all relevant SUs from the DAG to this SchedGroup.
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void initSchedGroup();
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// Add instructions to the SchedGroup bottom up starting from RIter.
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// PipelineInstrs is a set of instructions that should not be added to the
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// SchedGroup even when the other conditions for adding it are satisfied.
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// RIter will be added to the SchedGroup as well, and dependencies will be
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// added so that RIter will always be scheduled at the end of the group.
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void initSchedGroup(std::vector<SUnit>::reverse_iterator RIter,
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SUnitsToCandidateSGsMap &SyncedInstrs);
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void initSchedGroup(SUnitsToCandidateSGsMap &SyncedInstrs);
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int getSyncID() { return SyncID; }
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int getSGID() { return SGID; }
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SchedGroupMask getMask() { return SGMask; }
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SchedGroup(SchedGroupMask SGMask, Optional<unsigned> MaxSize,
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ScheduleDAGInstrs *DAG, const SIInstrInfo *TII)
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: SGMask(SGMask), MaxSize(MaxSize), DAG(DAG), TII(TII) {}
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SchedGroup(SchedGroupMask SGMask, Optional<unsigned> MaxSize, int SyncID,
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int SGID, ScheduleDAGInstrs *DAG, const SIInstrInfo *TII)
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: SGMask(SGMask), MaxSize(MaxSize), SyncID(SyncID), SGID(SGID), DAG(DAG),
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TII(TII) {}
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};
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// Remove all existing edges from a SCHED_BARRIER or SCHED_GROUP_BARRIER.
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static void resetEdges(SUnit &SU, ScheduleDAGInstrs *DAG) {
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assert(SU.getInstr()->getOpcode() == AMDGPU::SCHED_BARRIER ||
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SU.getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER);
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while (!SU.Preds.empty())
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for (auto &P : SU.Preds)
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SU.removePred(P);
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while (!SU.Succs.empty())
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for (auto &S : SU.Succs)
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for (auto &SP : S.getSUnit()->Preds)
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if (SP.getSUnit() == &SU)
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S.getSUnit()->removePred(SP);
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}
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typedef std::pair<SUnit *, SmallVector<int, 4>> SUToCandSGsPair;
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typedef SmallVector<SUToCandSGsPair, 4> SUsToCandSGsVec;
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// The PipelineSolver is used to assign SUnits to SchedGroups in a pipeline
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// in non-trivial cases. For example, if the requested pipeline is
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// {VMEM_READ, VALU, MFMA, VMEM_READ} and we encounter a VMEM_READ instruction
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// in the DAG, then we will have an instruction that can not be trivially
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// assigned to a SchedGroup. The PipelineSolver class implements two algorithms
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// to find a good solution to the pipeline -- a greedy algorithm and an exact
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// algorithm. The exact algorithm has an exponential time complexity and should
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// only be used for small sized problems or medium sized problems where an exact
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// solution is highly desired.
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class PipelineSolver {
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ScheduleDAGMI *DAG;
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// Instructions that can be assigned to multiple SchedGroups
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DenseMap<int, SUnitsToCandidateSGsMap> SyncedInstrs;
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SmallVector<SUsToCandSGsVec, 4> PipelineInstrs;
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DenseMap<int, SmallVector<SchedGroup, 4>> SyncedSchedGroups;
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// The current working pipeline
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SmallVector<SmallVector<SchedGroup, 4>, 4> CurrPipeline;
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// The pipeline that has the best solution found so far
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SmallVector<SmallVector<SchedGroup, 4>, 4> BestPipeline;
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// Whether or not we actually have any SyncedInstrs to try to solve.
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bool NeedsSolver = false;
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// Compute an estimate of the size of search tree -- the true size is
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// the product of each conflictedInst.Matches.size() across all SyncPipelines
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unsigned computeProblemSize();
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// The cost penalty of not assigning a SU to a SchedGroup
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int MissPenalty = 0;
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// Costs in terms of the number of edges we are unable to add
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int BestCost = -1;
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int CurrCost = 0;
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// Index pointing to the conflicting instruction that is currently being
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// fitted
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int CurrConflInstNo = 0;
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// Index to the pipeline that is currently being fitted
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int CurrSyncGroupIdx = 0;
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// The first non trivial pipeline
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int BeginSyncGroupIdx = 0;
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// How many branches we have explored
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uint64_t BranchesExplored = 0;
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// Update indices to fit next conflicting instruction
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void advancePosition();
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// Recede indices to attempt to find better fit for previous conflicting
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// instruction
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void retreatPosition();
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// The exponential time algorithm which finds the provably best fit
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bool solveExact();
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// The polynomial time algorithm which attempts to find a good fit
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bool solveGreedy();
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// Whether or not the current solution is optimal
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bool checkOptimal();
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// Populate the ready list, prioiritizing fewest missed edges first
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void populateReadyList(SUToCandSGsPair &CurrSU,
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SmallVectorImpl<std::pair<int, int>> &ReadyList,
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SmallVectorImpl<SchedGroup> &SyncPipeline);
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// Add edges corresponding to the SchedGroups as assigned by solver
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void makePipeline();
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// Add the edges from the SU to the other SchedGroups in pipeline, and
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// return the number of edges missed.
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int addEdges(SmallVectorImpl<SchedGroup> &SyncPipeline, SUnit *SU, int SGID,
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std::vector<std::pair<SUnit *, SUnit *>> &AddedEdges);
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// Remove the edges passed via AddedEdges
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void removeEdges(const std::vector<std::pair<SUnit *, SUnit *>> &AddedEdges);
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// Convert the passed in maps to arrays for bidirectional iterators
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void convertSyncMapsToArrays();
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void reset();
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public:
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// Invoke the solver to map instructions to instruction groups. Heuristic &&
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// command-line-option determines to use exact or greedy algorithm.
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void solve();
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PipelineSolver(DenseMap<int, SmallVector<SchedGroup, 4>> &SyncedSchedGroups,
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DenseMap<int, SUnitsToCandidateSGsMap> &SyncedInstrs,
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ScheduleDAGMI *DAG)
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: DAG(DAG), SyncedInstrs(SyncedInstrs),
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SyncedSchedGroups(SyncedSchedGroups) {
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for (auto &PipelineInstrs : SyncedInstrs) {
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if (PipelineInstrs.second.size() > 0) {
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NeedsSolver = true;
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break;
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}
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}
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if (!NeedsSolver)
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return;
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convertSyncMapsToArrays();
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CurrPipeline = BestPipeline;
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while (static_cast<size_t>(BeginSyncGroupIdx) < PipelineInstrs.size() &&
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PipelineInstrs[BeginSyncGroupIdx].size() == 0)
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++BeginSyncGroupIdx;
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if (static_cast<size_t>(BeginSyncGroupIdx) >= PipelineInstrs.size())
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return;
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}
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};
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void PipelineSolver::reset() {
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for (auto &SyncPipeline : CurrPipeline) {
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for (auto &SG : SyncPipeline) {
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SmallVector<SUnit *, 32> TempCollection = SG.Collection;
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SG.Collection.clear();
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auto SchedBarr = std::find_if(
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TempCollection.begin(), TempCollection.end(), [](SUnit *SU) {
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return SU->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER;
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});
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if (SchedBarr != TempCollection.end())
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SG.Collection.push_back(*SchedBarr);
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}
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}
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CurrSyncGroupIdx = BeginSyncGroupIdx;
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CurrConflInstNo = 0;
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CurrCost = 0;
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}
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void PipelineSolver::convertSyncMapsToArrays() {
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for (auto &SyncPipe : SyncedSchedGroups) {
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BestPipeline.insert(BestPipeline.begin(), SyncPipe.second);
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}
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int PipelineIDx = SyncedInstrs.size() - 1;
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PipelineInstrs.resize(SyncedInstrs.size());
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for (auto &SyncInstrMap : SyncedInstrs) {
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for (auto &SUsToCandSGs : SyncInstrMap.second) {
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if (PipelineInstrs[PipelineIDx].size() == 0) {
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PipelineInstrs[PipelineIDx].push_back(
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std::make_pair(SUsToCandSGs.first, SUsToCandSGs.second));
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continue;
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}
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auto SortPosition = PipelineInstrs[PipelineIDx].begin();
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// Insert them in sorted order -- this allows for good parsing order in
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// the greedy algorithm
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while (SortPosition != PipelineInstrs[PipelineIDx].end() &&
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SUsToCandSGs.first->NodeNum > SortPosition->first->NodeNum)
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++SortPosition;
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PipelineInstrs[PipelineIDx].insert(
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SortPosition,
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std::make_pair(SUsToCandSGs.first, SUsToCandSGs.second));
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}
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--PipelineIDx;
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}
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}
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void PipelineSolver::makePipeline() {
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// Preserve the order of barrier for subsequent SchedGroupBarrier mutations
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for (auto &SyncPipeline : BestPipeline) {
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for (auto &SG : SyncPipeline) {
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SUnit *SGBarr = nullptr;
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for (auto &SU : SG.Collection) {
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if (SU->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER)
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SGBarr = SU;
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}
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// Command line requested IGroupLP doesn't have SGBarr
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if (!SGBarr)
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continue;
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resetEdges(*SGBarr, DAG);
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SG.link(*SGBarr, false);
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}
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}
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for (auto &SyncPipeline : BestPipeline) {
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auto I = SyncPipeline.rbegin();
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auto E = SyncPipeline.rend();
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for (; I != E; ++I) {
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auto &GroupA = *I;
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for (auto J = std::next(I); J != E; ++J) {
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auto &GroupB = *J;
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GroupA.link(GroupB);
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}
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}
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}
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}
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int PipelineSolver::addEdges(
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SmallVectorImpl<SchedGroup> &SyncPipeline, SUnit *SU, int SGID,
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std::vector<std::pair<SUnit *, SUnit *>> &AddedEdges) {
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int AddedCost = 0;
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bool MakePred = false;
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// The groups in the pipeline are in reverse order. Thus,
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// by traversing them from last to first, we are traversing
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// them in the order as they were introduced in the code. After we
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// pass the group the SU is being assigned to, it should be
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// linked as a predecessor of the subsequent SchedGroups
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auto GroupNo = (int)SyncPipeline.size() - 1;
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for (; GroupNo >= 0; GroupNo--) {
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if (SyncPipeline[GroupNo].getSGID() == SGID) {
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MakePred = true;
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continue;
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}
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auto Group = &SyncPipeline[GroupNo];
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AddedCost += Group->link(*SU, MakePred, AddedEdges);
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assert(AddedCost >= 0);
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}
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return AddedCost;
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}
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void PipelineSolver::removeEdges(
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const std::vector<std::pair<SUnit *, SUnit *>> &EdgesToRemove) {
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// Only remove the edges that we have added when testing
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// the fit.
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for (auto &PredSuccPair : EdgesToRemove) {
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SUnit *Pred = PredSuccPair.first;
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SUnit *Succ = PredSuccPair.second;
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auto Match =
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std::find_if(Succ->Preds.begin(), Succ->Preds.end(),
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[&Pred](SDep &P) { return P.getSUnit() == Pred; });
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if (Match != Succ->Preds.end()) {
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assert(Match->isArtificial());
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Succ->removePred(*Match);
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}
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}
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}
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void PipelineSolver::advancePosition() {
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++CurrConflInstNo;
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if (static_cast<size_t>(CurrConflInstNo) >=
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PipelineInstrs[CurrSyncGroupIdx].size()) {
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CurrConflInstNo = 0;
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++CurrSyncGroupIdx;
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// Advance to next non-trivial pipeline
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while (static_cast<size_t>(CurrSyncGroupIdx) < PipelineInstrs.size() &&
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PipelineInstrs[CurrSyncGroupIdx].size() == 0)
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++CurrSyncGroupIdx;
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}
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}
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void PipelineSolver::retreatPosition() {
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assert(CurrConflInstNo >= 0);
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assert(CurrSyncGroupIdx >= 0);
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if (CurrConflInstNo > 0) {
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--CurrConflInstNo;
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return;
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}
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if (CurrConflInstNo == 0) {
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// If we return to the starting position, we have explored
|
|
// the entire tree
|
|
if (CurrSyncGroupIdx == BeginSyncGroupIdx)
|
|
return;
|
|
|
|
--CurrSyncGroupIdx;
|
|
// Go to previous non-trivial pipeline
|
|
while (PipelineInstrs[CurrSyncGroupIdx].size() == 0)
|
|
--CurrSyncGroupIdx;
|
|
|
|
CurrConflInstNo = PipelineInstrs[CurrSyncGroupIdx].size() - 1;
|
|
}
|
|
}
|
|
|
|
bool PipelineSolver::checkOptimal() {
|
|
if (static_cast<size_t>(CurrSyncGroupIdx) == PipelineInstrs.size()) {
|
|
if (BestCost == -1 || CurrCost < BestCost) {
|
|
BestPipeline = CurrPipeline;
|
|
BestCost = CurrCost;
|
|
LLVM_DEBUG(dbgs() << "Found Fit with cost " << BestCost << "\n");
|
|
}
|
|
assert(BestCost >= 0);
|
|
}
|
|
|
|
bool DoneExploring = false;
|
|
if (MaxBranchesExplored > 0 && BranchesExplored >= MaxBranchesExplored)
|
|
DoneExploring = true;
|
|
|
|
return (DoneExploring || BestCost == 0);
|
|
}
|
|
|
|
void PipelineSolver::populateReadyList(
|
|
SUToCandSGsPair &CurrSU, SmallVectorImpl<std::pair<int, int>> &ReadyList,
|
|
SmallVectorImpl<SchedGroup> &SyncPipeline) {
|
|
assert(CurrSU.second.size() >= 1);
|
|
auto I = CurrSU.second.rbegin();
|
|
auto E = CurrSU.second.rend();
|
|
for (; I != E; ++I) {
|
|
std::vector<std::pair<SUnit *, SUnit *>> AddedEdges;
|
|
int CandSGID = *I;
|
|
SchedGroup *Match;
|
|
for (auto &SG : SyncPipeline) {
|
|
if (SG.getSGID() == CandSGID)
|
|
Match = &SG;
|
|
}
|
|
|
|
if (UseCostHeur) {
|
|
if (Match->isFull()) {
|
|
ReadyList.push_back(std::make_pair(*I, MissPenalty));
|
|
continue;
|
|
}
|
|
|
|
int TempCost = addEdges(SyncPipeline, CurrSU.first, CandSGID, AddedEdges);
|
|
ReadyList.push_back(std::make_pair(*I, TempCost));
|
|
removeEdges(AddedEdges);
|
|
} else
|
|
ReadyList.push_back(std::make_pair(*I, -1));
|
|
}
|
|
|
|
if (UseCostHeur) {
|
|
std::sort(ReadyList.begin(), ReadyList.end(),
|
|
[](std::pair<int, int> A, std::pair<int, int> B) {
|
|
return A.second < B.second;
|
|
});
|
|
}
|
|
|
|
assert(ReadyList.size() == CurrSU.second.size());
|
|
}
|
|
|
|
bool PipelineSolver::solveExact() {
|
|
if (checkOptimal())
|
|
return true;
|
|
|
|
if (static_cast<size_t>(CurrSyncGroupIdx) == PipelineInstrs.size())
|
|
return false;
|
|
|
|
assert(static_cast<size_t>(CurrSyncGroupIdx) < PipelineInstrs.size());
|
|
assert(static_cast<size_t>(CurrConflInstNo) <
|
|
PipelineInstrs[CurrSyncGroupIdx].size());
|
|
SUToCandSGsPair CurrSU = PipelineInstrs[CurrSyncGroupIdx][CurrConflInstNo];
|
|
LLVM_DEBUG(dbgs() << "Fitting SU(" << CurrSU.first->NodeNum
|
|
<< ") in Pipeline # " << CurrSyncGroupIdx << "\n");
|
|
|
|
// SchedGroup -> Cost pairs
|
|
SmallVector<std::pair<int, int>, 4> ReadyList;
|
|
// Prioritize the candidate sched groups in terms of lowest cost first
|
|
populateReadyList(CurrSU, ReadyList, CurrPipeline[CurrSyncGroupIdx]);
|
|
|
|
auto I = ReadyList.begin();
|
|
auto E = ReadyList.end();
|
|
for (; I != E; ++I) {
|
|
// If we are trying SGs in least cost order, and the current SG is cost
|
|
// infeasible, then all subsequent SGs will also be cost infeasible, so we
|
|
// can prune.
|
|
if (BestCost != -1 && (CurrCost + I->second > BestCost))
|
|
return false;
|
|
|
|
int CandSGID = I->first;
|
|
int AddedCost = 0;
|
|
std::vector<std::pair<SUnit *, SUnit *>> AddedEdges;
|
|
auto &SyncPipeline = CurrPipeline[CurrSyncGroupIdx];
|
|
SchedGroup *Match;
|
|
for (auto &SG : SyncPipeline) {
|
|
if (SG.getSGID() == CandSGID)
|
|
Match = &SG;
|
|
}
|
|
|
|
if (Match->isFull())
|
|
continue;
|
|
|
|
LLVM_DEBUG(dbgs() << "Assigning to SchedGroup with Mask "
|
|
<< (int)Match->getMask() << "and ID " << CandSGID
|
|
<< "\n");
|
|
Match->add(*CurrSU.first);
|
|
AddedCost = addEdges(SyncPipeline, CurrSU.first, CandSGID, AddedEdges);
|
|
LLVM_DEBUG(dbgs() << "Cost of Assignment: " << AddedCost << "\n");
|
|
CurrCost += AddedCost;
|
|
advancePosition();
|
|
++BranchesExplored;
|
|
bool FinishedExploring = false;
|
|
// If the Cost after adding edges is greater than a known solution,
|
|
// backtrack
|
|
if (CurrCost < BestCost || BestCost == -1) {
|
|
if (solveExact()) {
|
|
FinishedExploring = BestCost != 0;
|
|
if (!FinishedExploring)
|
|
return true;
|
|
}
|
|
}
|
|
|
|
retreatPosition();
|
|
CurrCost -= AddedCost;
|
|
removeEdges(AddedEdges);
|
|
Match->pop();
|
|
CurrPipeline[CurrSyncGroupIdx] = SyncPipeline;
|
|
if (FinishedExploring)
|
|
return true;
|
|
}
|
|
|
|
// Try the pipeline where the current instruction is omitted
|
|
// Potentially if we omit a problematic instruction from the pipeline,
|
|
// all the other instructions can nicely fit.
|
|
CurrCost += MissPenalty;
|
|
advancePosition();
|
|
|
|
LLVM_DEBUG(dbgs() << "NOT Assigned (" << CurrSU.first->NodeNum << ")\n");
|
|
|
|
bool FinishedExploring = false;
|
|
if (CurrCost < BestCost || BestCost == -1) {
|
|
if (solveExact()) {
|
|
bool FinishedExploring = BestCost != 0;
|
|
if (!FinishedExploring)
|
|
return true;
|
|
}
|
|
}
|
|
|
|
retreatPosition();
|
|
CurrCost -= MissPenalty;
|
|
return FinishedExploring;
|
|
}
|
|
|
|
bool PipelineSolver::solveGreedy() {
|
|
BestCost = 0;
|
|
std::vector<std::pair<SUnit *, SUnit *>> AddedEdges;
|
|
|
|
while (static_cast<size_t>(CurrSyncGroupIdx) < PipelineInstrs.size()) {
|
|
SUToCandSGsPair CurrSU = PipelineInstrs[CurrSyncGroupIdx][CurrConflInstNo];
|
|
int BestNodeCost = -1;
|
|
int TempCost;
|
|
SchedGroup *BestGroup = nullptr;
|
|
int BestGroupID = -1;
|
|
auto &SyncPipeline = CurrPipeline[CurrSyncGroupIdx];
|
|
LLVM_DEBUG(dbgs() << "Fitting SU(" << CurrSU.first->NodeNum
|
|
<< ") in Pipeline # " << CurrSyncGroupIdx << "\n");
|
|
|
|
// Since we have added the potential SchedGroups from bottom up, but
|
|
// traversed the DAG from top down, parse over the groups from last to
|
|
// first. If we fail to do this for the greedy algorithm, the solution will
|
|
// likely not be good in more complex cases.
|
|
auto I = CurrSU.second.rbegin();
|
|
auto E = CurrSU.second.rend();
|
|
for (; I != E; ++I) {
|
|
std::vector<std::pair<SUnit *, SUnit *>> AddedEdges;
|
|
int CandSGID = *I;
|
|
SchedGroup *Match;
|
|
for (auto &SG : SyncPipeline) {
|
|
if (SG.getSGID() == CandSGID)
|
|
Match = &SG;
|
|
}
|
|
|
|
LLVM_DEBUG(dbgs() << "Trying SGID # " << CandSGID << " with Mask "
|
|
<< (int)Match->getMask() << "\n");
|
|
|
|
if (Match->isFull()) {
|
|
LLVM_DEBUG(dbgs() << "SGID # " << CandSGID << " is full\n");
|
|
continue;
|
|
}
|
|
TempCost = addEdges(SyncPipeline, CurrSU.first, CandSGID, AddedEdges);
|
|
LLVM_DEBUG(dbgs() << "Cost of Group " << TempCost << "\n");
|
|
if (TempCost < BestNodeCost || BestNodeCost == -1) {
|
|
BestGroup = Match;
|
|
BestNodeCost = TempCost;
|
|
BestGroupID = CandSGID;
|
|
}
|
|
removeEdges(AddedEdges);
|
|
if (BestNodeCost == 0)
|
|
break;
|
|
}
|
|
|
|
if (BestGroupID != -1) {
|
|
BestGroup->add(*CurrSU.first);
|
|
addEdges(SyncPipeline, CurrSU.first, BestGroupID, AddedEdges);
|
|
LLVM_DEBUG(dbgs() << "Best Group has ID: " << BestGroupID << " and Mask"
|
|
<< (int)BestGroup->getMask() << "\n");
|
|
BestCost += TempCost;
|
|
} else
|
|
BestCost += MissPenalty;
|
|
|
|
CurrPipeline[CurrSyncGroupIdx] = SyncPipeline;
|
|
advancePosition();
|
|
}
|
|
BestPipeline = CurrPipeline;
|
|
removeEdges(AddedEdges);
|
|
return false;
|
|
}
|
|
|
|
unsigned PipelineSolver::computeProblemSize() {
|
|
unsigned ProblemSize = 0;
|
|
for (auto &PipeConflicts : PipelineInstrs) {
|
|
ProblemSize += PipeConflicts.size();
|
|
}
|
|
|
|
return ProblemSize;
|
|
}
|
|
|
|
void PipelineSolver::solve() {
|
|
if (!NeedsSolver)
|
|
return;
|
|
|
|
unsigned ProblemSize = computeProblemSize();
|
|
assert(ProblemSize > 0);
|
|
|
|
bool BelowCutoff = (CutoffForExact > 0) && ProblemSize <= CutoffForExact;
|
|
MissPenalty = (ProblemSize / 2) + 1;
|
|
|
|
LLVM_DEBUG(DAG->dump());
|
|
if (EnableExactSolver || BelowCutoff) {
|
|
LLVM_DEBUG(dbgs() << "Starting Greedy pipeline solver\n");
|
|
solveGreedy();
|
|
reset();
|
|
LLVM_DEBUG(dbgs() << "Greedy produced best cost of " << BestCost << "\n");
|
|
if (BestCost > 0) {
|
|
LLVM_DEBUG(dbgs() << "Starting EXACT pipeline solver\n");
|
|
solveExact();
|
|
LLVM_DEBUG(dbgs() << "Exact produced best cost of " << BestCost << "\n");
|
|
}
|
|
} else { // Use the Greedy Algorithm by default
|
|
LLVM_DEBUG(dbgs() << "Starting GREEDY pipeline solver\n");
|
|
solveGreedy();
|
|
}
|
|
|
|
makePipeline();
|
|
}
|
|
|
|
class IGroupLPDAGMutation : public ScheduleDAGMutation {
|
|
private:
|
|
// Organize lists of SchedGroups by their SyncID. SchedGroups /
|
|
// SCHED_GROUP_BARRIERs with different SyncIDs will have no edges added
|
|
// between then.
|
|
DenseMap<int, SmallVector<SchedGroup, 4>> SyncedSchedGroups;
|
|
|
|
// The number of created sched groups -- also used as SGID
|
|
int NumCreatedSchedGroups = 0;
|
|
|
|
// Used to track instructions that can be mapped to multiple sched groups
|
|
DenseMap<int, SUnitsToCandidateSGsMap> SyncedInstrs;
|
|
|
|
public:
|
|
const SIInstrInfo *TII;
|
|
ScheduleDAGMI *DAG;
|
|
|
|
IGroupLPDAGMutation() = default;
|
|
void apply(ScheduleDAGInstrs *DAGInstrs) override;
|
|
};
|
|
|
|
// DAG mutation that coordinates with the SCHED_BARRIER instruction and
|
|
// corresponding builtin. The mutation adds edges from specific instruction
|
|
// classes determined by the SCHED_BARRIER mask so that they cannot be
|
|
class SchedBarrierDAGMutation : public ScheduleDAGMutation {
|
|
private:
|
|
const SIInstrInfo *TII;
|
|
|
|
ScheduleDAGMI *DAG;
|
|
|
|
// Organize lists of SchedGroups by their SyncID. SchedGroups /
|
|
// SCHED_GROUP_BARRIERs with different SyncIDs will have no edges added
|
|
// between then.
|
|
DenseMap<int, SmallVector<SchedGroup, 4>> SyncedSchedGroups;
|
|
|
|
// The number of create sched groups -- also used as SGID
|
|
int NumCreatedSchedGroups = 0;
|
|
|
|
// Used to track instructions that can be mapped to multiple sched groups
|
|
DenseMap<int, SUnitsToCandidateSGsMap> SyncedInstrs;
|
|
|
|
// Add DAG edges that enforce SCHED_BARRIER ordering.
|
|
void addSchedBarrierEdges(SUnit &SU);
|
|
|
|
// Use a SCHED_BARRIER's mask to identify instruction SchedGroups that should
|
|
// not be reordered accross the SCHED_BARRIER. This is used for the base
|
|
// SCHED_BARRIER, and not SCHED_GROUP_BARRIER. The difference is that
|
|
// SCHED_BARRIER will always block all instructions that can be classified
|
|
// into a particular SchedClass, whereas SCHED_GROUP_BARRIER has a fixed size
|
|
// and may only synchronize with some SchedGroups. Returns the inverse of
|
|
// Mask. SCHED_BARRIER's mask describes which instruction types should be
|
|
// allowed to be scheduled across it. Invert the mask to get the
|
|
// SchedGroupMask of instructions that should be barred.
|
|
SchedGroupMask invertSchedBarrierMask(SchedGroupMask Mask) const;
|
|
|
|
// Create SchedGroups for a SCHED_GROUP_BARRIER.
|
|
void initSchedGroupBarrierPipelineStage(
|
|
std::vector<SUnit>::reverse_iterator RIter);
|
|
|
|
public:
|
|
void apply(ScheduleDAGInstrs *DAGInstrs) override;
|
|
|
|
SchedBarrierDAGMutation() = default;
|
|
};
|
|
|
|
bool SchedGroup::tryAddEdge(SUnit *A, SUnit *B) {
|
|
if (A != B && DAG->canAddEdge(B, A)) {
|
|
DAG->addEdge(B, SDep(A, SDep::Artificial));
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
bool SchedGroup::canAddMI(const MachineInstr &MI) const {
|
|
bool Result = false;
|
|
if (MI.isMetaInstruction())
|
|
Result = false;
|
|
|
|
else if (((SGMask & SchedGroupMask::ALU) != SchedGroupMask::NONE) &&
|
|
(TII->isVALU(MI) || TII->isMFMA(MI) || TII->isSALU(MI)))
|
|
Result = true;
|
|
|
|
else if (((SGMask & SchedGroupMask::VALU) != SchedGroupMask::NONE) &&
|
|
TII->isVALU(MI) && !TII->isMFMA(MI))
|
|
Result = true;
|
|
|
|
else if (((SGMask & SchedGroupMask::SALU) != SchedGroupMask::NONE) &&
|
|
TII->isSALU(MI))
|
|
Result = true;
|
|
|
|
else if (((SGMask & SchedGroupMask::MFMA) != SchedGroupMask::NONE) &&
|
|
TII->isMFMA(MI))
|
|
Result = true;
|
|
|
|
else if (((SGMask & SchedGroupMask::VMEM) != SchedGroupMask::NONE) &&
|
|
(TII->isVMEM(MI) || (TII->isFLAT(MI) && !TII->isDS(MI))))
|
|
Result = true;
|
|
|
|
else if (((SGMask & SchedGroupMask::VMEM_READ) != SchedGroupMask::NONE) &&
|
|
MI.mayLoad() &&
|
|
(TII->isVMEM(MI) || (TII->isFLAT(MI) && !TII->isDS(MI))))
|
|
Result = true;
|
|
|
|
else if (((SGMask & SchedGroupMask::VMEM_WRITE) != SchedGroupMask::NONE) &&
|
|
MI.mayStore() &&
|
|
(TII->isVMEM(MI) || (TII->isFLAT(MI) && !TII->isDS(MI))))
|
|
Result = true;
|
|
|
|
else if (((SGMask & SchedGroupMask::DS) != SchedGroupMask::NONE) &&
|
|
TII->isDS(MI))
|
|
Result = true;
|
|
|
|
else if (((SGMask & SchedGroupMask::DS_READ) != SchedGroupMask::NONE) &&
|
|
MI.mayLoad() && TII->isDS(MI))
|
|
Result = true;
|
|
|
|
else if (((SGMask & SchedGroupMask::DS_WRITE) != SchedGroupMask::NONE) &&
|
|
MI.mayStore() && TII->isDS(MI))
|
|
Result = true;
|
|
|
|
LLVM_DEBUG(
|
|
dbgs() << "For SchedGroup with mask " << format_hex((int)SGMask, 10, true)
|
|
<< (Result ? " could classify " : " unable to classify ") << MI);
|
|
|
|
return Result;
|
|
}
|
|
|
|
int SchedGroup::link(SUnit &SU, bool MakePred,
|
|
std::vector<std::pair<SUnit *, SUnit *>> &AddedEdges) {
|
|
int MissedEdges = 0;
|
|
for (auto A : Collection) {
|
|
SUnit *B = &SU;
|
|
if (A == B || A->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER)
|
|
continue;
|
|
if (MakePred)
|
|
std::swap(A, B);
|
|
|
|
if (DAG->IsReachable(B, A))
|
|
continue;
|
|
// tryAddEdge returns false if there is a dependency that makes adding
|
|
// the A->B edge impossible, otherwise it returns true;
|
|
bool Added = tryAddEdge(A, B);
|
|
if (Added)
|
|
AddedEdges.push_back(std::make_pair(A, B));
|
|
else
|
|
++MissedEdges;
|
|
}
|
|
|
|
return MissedEdges;
|
|
}
|
|
|
|
void SchedGroup::link(SUnit &SU, bool MakePred) {
|
|
for (auto A : Collection) {
|
|
SUnit *B = &SU;
|
|
if (A->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER)
|
|
continue;
|
|
if (MakePred)
|
|
std::swap(A, B);
|
|
|
|
tryAddEdge(A, B);
|
|
}
|
|
}
|
|
|
|
void SchedGroup::link(SUnit &SU,
|
|
function_ref<bool(const SUnit *A, const SUnit *B)> P) {
|
|
for (auto A : Collection) {
|
|
SUnit *B = &SU;
|
|
if (P(A, B))
|
|
std::swap(A, B);
|
|
|
|
tryAddEdge(A, B);
|
|
}
|
|
}
|
|
|
|
void SchedGroup::link(SchedGroup &OtherGroup) {
|
|
for (auto B : OtherGroup.Collection)
|
|
link(*B);
|
|
}
|
|
|
|
bool SchedGroup::canAddSU(SUnit &SU) const {
|
|
MachineInstr &MI = *SU.getInstr();
|
|
if (MI.getOpcode() != TargetOpcode::BUNDLE)
|
|
return canAddMI(MI);
|
|
|
|
// Special case for bundled MIs.
|
|
const MachineBasicBlock *MBB = MI.getParent();
|
|
MachineBasicBlock::instr_iterator B = MI.getIterator(), E = ++B;
|
|
while (E != MBB->end() && E->isBundledWithPred())
|
|
++E;
|
|
|
|
// Return true if all of the bundled MIs can be added to this group.
|
|
return std::all_of(B, E, [this](MachineInstr &MI) { return canAddMI(MI); });
|
|
}
|
|
|
|
void SchedGroup::initSchedGroup() {
|
|
for (auto &SU : DAG->SUnits) {
|
|
if (isFull())
|
|
break;
|
|
|
|
if (canAddSU(SU))
|
|
add(SU);
|
|
}
|
|
}
|
|
|
|
void SchedGroup::initSchedGroup(std::vector<SUnit>::reverse_iterator RIter,
|
|
SUnitsToCandidateSGsMap &SyncedInstrs) {
|
|
SUnit &InitSU = *RIter;
|
|
for (auto E = DAG->SUnits.rend(); RIter != E; ++RIter) {
|
|
auto &SU = *RIter;
|
|
if (isFull())
|
|
break;
|
|
|
|
if (canAddSU(SU))
|
|
SyncedInstrs[&SU].push_back(SGID);
|
|
}
|
|
|
|
add(InitSU);
|
|
assert(MaxSize);
|
|
(*MaxSize)++;
|
|
}
|
|
|
|
void SchedGroup::initSchedGroup(SUnitsToCandidateSGsMap &SyncedInstrs) {
|
|
auto I = DAG->SUnits.rbegin();
|
|
auto E = DAG->SUnits.rend();
|
|
for (; I != E; ++I) {
|
|
auto &SU = *I;
|
|
if (isFull())
|
|
break;
|
|
|
|
if (canAddSU(SU))
|
|
SyncedInstrs[&SU].push_back(SGID);
|
|
}
|
|
}
|
|
|
|
void IGroupLPDAGMutation::apply(ScheduleDAGInstrs *DAGInstrs) {
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const GCNSubtarget &ST = DAGInstrs->MF.getSubtarget<GCNSubtarget>();
|
|
TII = ST.getInstrInfo();
|
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DAG = static_cast<ScheduleDAGMI *>(DAGInstrs);
|
|
|
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// IGroupLP and sched_group_barrier are mutually exclusive mutations.
|
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// Check for sched_group_barriers as that mutation gets priority.
|
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for (auto R = DAG->SUnits.rbegin(), E = DAG->SUnits.rend(); R != E; ++R) {
|
|
if (R->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER) {
|
|
return;
|
|
}
|
|
}
|
|
|
|
SyncedSchedGroups.clear();
|
|
SyncedInstrs.clear();
|
|
const TargetSchedModel *TSchedModel = DAGInstrs->getSchedModel();
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if (!TSchedModel || DAG->SUnits.empty())
|
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return;
|
|
|
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LLVM_DEBUG(dbgs() << "Applying IGroupLPDAGMutation...\n");
|
|
|
|
// The order of InstructionGroups in this vector defines the
|
|
// order in which edges will be added. In other words, given the
|
|
// present ordering, we will try to make each VMEMRead instruction
|
|
// a predecessor of each DSRead instruction, and so on.
|
|
|
|
struct SGParams {
|
|
SchedGroupMask Mask;
|
|
Optional<unsigned> Size;
|
|
int SyncID;
|
|
|
|
SGParams(SchedGroupMask Mask, Optional<unsigned> Size, int SyncID)
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|
: Mask(Mask), Size(Size), SyncID(SyncID) {}
|
|
};
|
|
|
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SmallVector<SGParams, 16> PipelineOrderGroups;
|
|
|
|
for (size_t i = 0; i < DAG->SUnits.size() / 4; i++) {
|
|
PipelineOrderGroups.push_back({SchedGroupMask::DS_READ, 8, 0});
|
|
PipelineOrderGroups.push_back({SchedGroupMask::MFMA, 1, 0});
|
|
PipelineOrderGroups.push_back({SchedGroupMask::DS_WRITE, 8, 0});
|
|
}
|
|
|
|
auto I = PipelineOrderGroups.rbegin();
|
|
auto E = PipelineOrderGroups.rend();
|
|
for (; I < E; I++) {
|
|
auto &SG = SyncedSchedGroups[I->SyncID].emplace_back(
|
|
I->Mask, I->Size, I->SyncID, NumCreatedSchedGroups++, DAG, TII);
|
|
SG.initSchedGroup(SyncedInstrs[SG.getSyncID()]);
|
|
}
|
|
|
|
PipelineSolver PS(SyncedSchedGroups, SyncedInstrs, DAG);
|
|
// PipelineSolver performs the mutation by adding the edges it
|
|
// determined as the best
|
|
PS.solve();
|
|
}
|
|
|
|
void SchedBarrierDAGMutation::apply(ScheduleDAGInstrs *DAGInstrs) {
|
|
const TargetSchedModel *TSchedModel = DAGInstrs->getSchedModel();
|
|
if (!TSchedModel || DAGInstrs->SUnits.empty())
|
|
return;
|
|
|
|
LLVM_DEBUG(dbgs() << "Applying SchedBarrierDAGMutation...\n");
|
|
const GCNSubtarget &ST = DAGInstrs->MF.getSubtarget<GCNSubtarget>();
|
|
TII = ST.getInstrInfo();
|
|
DAG = static_cast<ScheduleDAGMI *>(DAGInstrs);
|
|
SyncedSchedGroups.clear();
|
|
SyncedInstrs.clear();
|
|
for (auto R = DAG->SUnits.rbegin(), E = DAG->SUnits.rend(); R != E; ++R) {
|
|
if (R->getInstr()->getOpcode() == AMDGPU::SCHED_BARRIER)
|
|
addSchedBarrierEdges(*R);
|
|
|
|
else if (R->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER)
|
|
initSchedGroupBarrierPipelineStage(R);
|
|
}
|
|
|
|
PipelineSolver PS(SyncedSchedGroups, SyncedInstrs, DAG);
|
|
// PipelineSolver performs the mutation by adding the edges it
|
|
// determined as the best
|
|
PS.solve();
|
|
}
|
|
|
|
void SchedBarrierDAGMutation::addSchedBarrierEdges(SUnit &SchedBarrier) {
|
|
MachineInstr &MI = *SchedBarrier.getInstr();
|
|
assert(MI.getOpcode() == AMDGPU::SCHED_BARRIER);
|
|
// Remove all existing edges from the SCHED_BARRIER that were added due to the
|
|
// instruction having side effects.
|
|
resetEdges(SchedBarrier, DAG);
|
|
auto InvertedMask =
|
|
invertSchedBarrierMask((SchedGroupMask)MI.getOperand(0).getImm());
|
|
SchedGroup SG(InvertedMask, None, DAG, TII);
|
|
SG.initSchedGroup();
|
|
// Preserve original instruction ordering relative to the SCHED_BARRIER.
|
|
SG.link(
|
|
SchedBarrier,
|
|
(function_ref<bool(const SUnit *A, const SUnit *B)>)[](
|
|
const SUnit *A, const SUnit *B) { return A->NodeNum > B->NodeNum; });
|
|
}
|
|
|
|
SchedGroupMask
|
|
SchedBarrierDAGMutation::invertSchedBarrierMask(SchedGroupMask Mask) const {
|
|
// Invert mask and erase bits for types of instructions that are implied to be
|
|
// allowed past the SCHED_BARRIER.
|
|
SchedGroupMask InvertedMask = ~Mask;
|
|
|
|
// ALU implies VALU, SALU, MFMA.
|
|
if ((InvertedMask & SchedGroupMask::ALU) == SchedGroupMask::NONE)
|
|
InvertedMask &=
|
|
~SchedGroupMask::VALU & ~SchedGroupMask::SALU & ~SchedGroupMask::MFMA;
|
|
// VALU, SALU, MFMA implies ALU.
|
|
else if ((InvertedMask & SchedGroupMask::VALU) == SchedGroupMask::NONE ||
|
|
(InvertedMask & SchedGroupMask::SALU) == SchedGroupMask::NONE ||
|
|
(InvertedMask & SchedGroupMask::MFMA) == SchedGroupMask::NONE)
|
|
InvertedMask &= ~SchedGroupMask::ALU;
|
|
|
|
// VMEM implies VMEM_READ, VMEM_WRITE.
|
|
if ((InvertedMask & SchedGroupMask::VMEM) == SchedGroupMask::NONE)
|
|
InvertedMask &= ~SchedGroupMask::VMEM_READ & ~SchedGroupMask::VMEM_WRITE;
|
|
// VMEM_READ, VMEM_WRITE implies VMEM.
|
|
else if ((InvertedMask & SchedGroupMask::VMEM_READ) == SchedGroupMask::NONE ||
|
|
(InvertedMask & SchedGroupMask::VMEM_WRITE) == SchedGroupMask::NONE)
|
|
InvertedMask &= ~SchedGroupMask::VMEM;
|
|
|
|
// DS implies DS_READ, DS_WRITE.
|
|
if ((InvertedMask & SchedGroupMask::DS) == SchedGroupMask::NONE)
|
|
InvertedMask &= ~SchedGroupMask::DS_READ & ~SchedGroupMask::DS_WRITE;
|
|
// DS_READ, DS_WRITE implies DS.
|
|
else if ((InvertedMask & SchedGroupMask::DS_READ) == SchedGroupMask::NONE ||
|
|
(InvertedMask & SchedGroupMask::DS_WRITE) == SchedGroupMask::NONE)
|
|
InvertedMask &= ~SchedGroupMask::DS;
|
|
|
|
return InvertedMask;
|
|
}
|
|
|
|
void SchedBarrierDAGMutation::initSchedGroupBarrierPipelineStage(
|
|
std::vector<SUnit>::reverse_iterator RIter) {
|
|
// Remove all existing edges from the SCHED_GROUP_BARRIER that were added due
|
|
// to the instruction having side effects.
|
|
resetEdges(*RIter, DAG);
|
|
MachineInstr &SGB = *RIter->getInstr();
|
|
assert(SGB.getOpcode() == AMDGPU::SCHED_GROUP_BARRIER);
|
|
int32_t SGMask = SGB.getOperand(0).getImm();
|
|
int32_t Size = SGB.getOperand(1).getImm();
|
|
int32_t SyncID = SGB.getOperand(2).getImm();
|
|
|
|
auto &SG = SyncedSchedGroups[SyncID].emplace_back(
|
|
(SchedGroupMask)SGMask, Size, SyncID, NumCreatedSchedGroups++, DAG, TII);
|
|
|
|
SG.initSchedGroup(RIter, SyncedInstrs[SG.getSyncID()]);
|
|
}
|
|
|
|
} // namespace
|
|
|
|
namespace llvm {
|
|
|
|
std::unique_ptr<ScheduleDAGMutation> createIGroupLPDAGMutation() {
|
|
return EnableIGroupLP ? std::make_unique<IGroupLPDAGMutation>() : nullptr;
|
|
}
|
|
|
|
std::unique_ptr<ScheduleDAGMutation> createSchedBarrierDAGMutation() {
|
|
return std::make_unique<SchedBarrierDAGMutation>();
|
|
}
|
|
|
|
} // end namespace llvm
|