263f1b2f5d
The combine step for shufflevector will sometimes replace undef in the mask with a defined value. This can cause an infinite loop in some cases as another combine will then put the undef back in the mask. This patch fixes the issue so that undefs are not replaced when doing a combine. Reviewed By: ZarkoCA, amyk, quinnp, saghir Differential Revision: https://reviews.llvm.org/D127439
97 lines
3.4 KiB
LLVM
97 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr10 -verify-machineinstrs \
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; RUN: < %s | FileCheck %s --check-prefix=AIX
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; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr10 -verify-machineinstrs \
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; RUN: < %s | FileCheck %s --check-prefix=AIX-32
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; RUN: llc -verify-machineinstrs -mtriple powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
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; RUN: | FileCheck %s --check-prefix=LE
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; RUN: llc -verify-machineinstrs -mtriple powerpcle-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
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; RUN: | FileCheck %s --check-prefix=LE-32
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; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
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; RUN: | FileCheck %s --check-prefix=BE
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; RUN: llc -verify-machineinstrs -mtriple powerpc-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names < %s \
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; RUN: | FileCheck %s --check-prefix=BE-32
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; Function Attrs: nounwind
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define dso_local <4 x i16> @shufflevector_combine(<4 x i32> %0) #0 {
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; AIX-LABEL: shufflevector_combine:
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; AIX: # %bb.0: # %newFuncRoot
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; AIX-NEXT: ld 3, L..C0(2) # %const.0
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; AIX-NEXT: xxlxor 36, 36, 36
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; AIX-NEXT: lxv 35, 0(3)
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; AIX-NEXT: li 3, 0
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; AIX-NEXT: vperm 2, 4, 2, 3
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; AIX-NEXT: vinsw 2, 3, 8
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; AIX-NEXT: vpkuwum 2, 2, 2
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; AIX-NEXT: blr
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;
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; AIX-32-LABEL: shufflevector_combine:
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; AIX-32: # %bb.0: # %newFuncRoot
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; AIX-32-NEXT: lwz 3, L..C0(2) # %const.0
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; AIX-32-NEXT: xxlxor 36, 36, 36
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; AIX-32-NEXT: lxv 35, 0(3)
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; AIX-32-NEXT: li 3, 0
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; AIX-32-NEXT: vperm 2, 4, 2, 3
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; AIX-32-NEXT: vinsw 2, 3, 8
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; AIX-32-NEXT: vpkuwum 2, 2, 2
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; AIX-32-NEXT: blr
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;
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; LE-LABEL: shufflevector_combine:
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; LE: # %bb.0: # %newFuncRoot
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; LE-NEXT: plxv v3, .LCPI0_0@PCREL(0), 1
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; LE-NEXT: xxlxor v4, v4, v4
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; LE-NEXT: li r3, 0
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; LE-NEXT: vperm v2, v2, v4, v3
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; LE-NEXT: vinsw v2, r3, 4
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; LE-NEXT: vpkuwum v2, v2, v2
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; LE-NEXT: blr
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;
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; LE-32-LABEL: shufflevector_combine:
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; LE-32: # %bb.0: # %newFuncRoot
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; LE-32-NEXT: li r3, .LCPI0_0@l
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; LE-32-NEXT: lis r4, .LCPI0_0@ha
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; LE-32-NEXT: xxlxor v4, v4, v4
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; LE-32-NEXT: lxvx v3, r4, r3
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; LE-32-NEXT: li r3, 0
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; LE-32-NEXT: vperm v2, v2, v4, v3
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; LE-32-NEXT: vinsw v2, r3, 4
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; LE-32-NEXT: vpkuwum v2, v2, v2
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; LE-32-NEXT: blr
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;
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; BE-LABEL: shufflevector_combine:
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; BE: # %bb.0: # %newFuncRoot
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; BE-NEXT: addis r3, r2, .LCPI0_0@toc@ha
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; BE-NEXT: xxlxor v4, v4, v4
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; BE-NEXT: addi r3, r3, .LCPI0_0@toc@l
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; BE-NEXT: lxv v3, 0(r3)
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; BE-NEXT: li r3, 0
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; BE-NEXT: vperm v2, v4, v2, v3
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; BE-NEXT: vinsw v2, r3, 8
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; BE-NEXT: vpkuwum v2, v2, v2
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; BE-NEXT: blr
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;
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; BE-32-LABEL: shufflevector_combine:
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; BE-32: # %bb.0: # %newFuncRoot
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; BE-32-NEXT: li r3, .LCPI0_0@l
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; BE-32-NEXT: lis r4, .LCPI0_0@ha
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; BE-32-NEXT: xxlxor v4, v4, v4
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; BE-32-NEXT: lxvx v3, r4, r3
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; BE-32-NEXT: li r3, 0
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; BE-32-NEXT: vperm v2, v4, v2, v3
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; BE-32-NEXT: vinsw v2, r3, 8
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; BE-32-NEXT: vpkuwum v2, v2, v2
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; BE-32-NEXT: blr
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newFuncRoot:
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%1 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %0, <4 x i32> <i32 0, i32 7, i32 undef, i32 6>
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%2 = insertelement <4 x i32> %1, i32 0, i64 2
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%3 = trunc <4 x i32> %2 to <4 x i16>
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ret <4 x i16> %3
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}
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attributes #0 = { nounwind }
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