2cca53c815
We can process the long shuffles (working across several actual vector registers) in the best way if we take the actual register represantion into account. We can build more correct representation of register shuffles, improve number of recognised buildvector sequences. Also, same function can be used to improve the cost model for the shuffles. in future patches. Part of D100486 Differential Revision: https://reviews.llvm.org/D115653
35 lines
1.3 KiB
LLVM
35 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-linux-gnu -mcpu=pwr8 -mattr=+vsx < %s | FileCheck %s
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define <4 x float> @bar(float* %p, float* %q) {
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; CHECK-LABEL: bar:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li 5, 16
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; CHECK-NEXT: lxvw4x 2, 0, 3
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; CHECK-NEXT: lxvw4x 3, 0, 4
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; CHECK-NEXT: addis 6, 2, .LCPI0_0@toc@ha
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; CHECK-NEXT: lxvw4x 0, 3, 5
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; CHECK-NEXT: lxvw4x 1, 4, 5
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; CHECK-NEXT: li 5, 32
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; CHECK-NEXT: xvsubsp 35, 3, 2
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; CHECK-NEXT: xvsubsp 34, 1, 0
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; CHECK-NEXT: lxvw4x 0, 3, 5
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; CHECK-NEXT: addi 3, 6, .LCPI0_0@toc@l
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; CHECK-NEXT: lxvw4x 1, 4, 5
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; CHECK-NEXT: lxvw4x 36, 0, 3
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; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha
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; CHECK-NEXT: addi 3, 3, .LCPI0_1@toc@l
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; CHECK-NEXT: xvsubsp 37, 1, 0
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; CHECK-NEXT: vperm 2, 3, 2, 4
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; CHECK-NEXT: lxvw4x 35, 0, 3
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; CHECK-NEXT: vperm 2, 2, 5, 3
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; CHECK-NEXT: blr
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%1 = bitcast float* %p to <12 x float>*
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%2 = bitcast float* %q to <12 x float>*
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%3 = load <12 x float>, <12 x float>* %1, align 16
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%4 = load <12 x float>, <12 x float>* %2, align 16
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%5 = fsub <12 x float> %4, %3
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%6 = shufflevector <12 x float> %5, <12 x float> undef, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
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ret <4 x float> %6
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}
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