766ca2c59e
VSX introduced some permute instructions that are direct replacements for Altivec ones except they can target all the VSX registers. We have added code generation for most of these but somehow missed the low/hi word merges (XXMRG[LH]W). This caused some additional spills on some large computationally intensive code. This patch simply adds the missed patterns.
22 lines
909 B
LLVM
22 lines
909 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -ppc-asm-full-reg-names --ppc-vsr-nums-as-vr < %s | FileCheck %s
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define dso_local void @_Z1jjPiPj() local_unnamed_addr #0 {
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; CHECK-LABEL: _Z1jjPiPj:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: ld r3, 0(r3)
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; CHECK-NEXT: std r3, -16(r1)
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; CHECK-NEXT: addi r3, r1, -16
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; CHECK-NEXT: lxvd2x vs0, 0, r3
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; CHECK-NEXT: xxswapd vs0, vs0
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; CHECK-NEXT: xxmrglw vs0, vs0, vs0
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; CHECK-NEXT: xxswapd vs0, vs0
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; CHECK-NEXT: stxvd2x vs0, 0, r3
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; CHECK-NEXT: blr
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entry:
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%wide.load42 = load <2 x i32>, <2 x i32>* undef, align 4
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%interleaved.vec49 = shufflevector <2 x i32> %wide.load42, <2 x i32> undef, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
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store <4 x i32> %interleaved.vec49, <4 x i32>* undef, align 4
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ret void
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}
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