335e8bf100
This patch changes the PowerPC backend to generate VSX load/store instructions for all vector loads/stores on Power8 and earlier (LE) instead of VMX load/store instructions. The reason for this change is because VMX instructions require the vector to be 16-byte aligned. So, a vector load/store will fail with VMX instructions if the vector is misaligned. Also, `gcc` generates VSX instructions in this situation which allow for unaligned access but require a swap instruction after loading/before storing. This is not an issue for BE because we already emit VSX instructions since no swap is required. And this is not an issue on Power9 and up since we have access to `lxv[x]`/`stxv[x]` which allow for unaligned access and do not require swaps. This patch also delays the VSX load/store for LE combines until after LegalizeOps to prioritize other load/store combines. Reviewed By: #powerpc, stefanp Differential Revision: https://reviews.llvm.org/D127309
147 lines
4.3 KiB
LLVM
147 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \
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; RUN: | FileCheck %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mattr=+vsx -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64-unknown-linux-gnu < %s \
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; RUN: | FileCheck %s --check-prefix=CHECK-P8-BE
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mattr=-power9-vector -ppc-vsr-nums-as-vr \
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; RUN: -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu < %s \
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; RUN: | FileCheck --check-prefix=CHECK-P9-VECTOR %s
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; RUN: llc -verify-machineinstrs -mcpu=pwr9 -ppc-vsr-nums-as-vr -ppc-asm-full-reg-names \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s \
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; RUN: --check-prefix=CHECK-P9 --implicit-check-not xxswapd
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define <2 x double> @testi0(<2 x double>* %p1, double* %p2) {
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; CHECK-LABEL: testi0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lxvd2x vs0, 0, r3
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; CHECK-NEXT: lfd f1, 0(r4)
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; CHECK-NEXT: xxswapd vs0, vs0
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; CHECK-NEXT: xxmrghd v2, vs0, vs1
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; CHECK-NEXT: blr
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;
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; CHECK-P8-BE-LABEL: testi0:
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; CHECK-P8-BE: # %bb.0:
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; CHECK-P8-BE-NEXT: lxvd2x vs0, 0, r3
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; CHECK-P8-BE-NEXT: lfd f1, 0(r4)
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; CHECK-P8-BE-NEXT: xxpermdi v2, vs1, vs0, 1
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; CHECK-P8-BE-NEXT: blr
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;
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; CHECK-P9-VECTOR-LABEL: testi0:
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; CHECK-P9-VECTOR: # %bb.0:
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; CHECK-P9-VECTOR-NEXT: lxvd2x vs0, 0, r3
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; CHECK-P9-VECTOR-NEXT: lfd f1, 0(r4)
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; CHECK-P9-VECTOR-NEXT: xxswapd vs0, vs0
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; CHECK-P9-VECTOR-NEXT: xxmrghd v2, vs0, vs1
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; CHECK-P9-VECTOR-NEXT: blr
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;
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; CHECK-P9-LABEL: testi0:
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; CHECK-P9: # %bb.0:
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; CHECK-P9-NEXT: lxv vs0, 0(r3)
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; CHECK-P9-NEXT: lfd f1, 0(r4)
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; CHECK-P9-NEXT: xxmrghd v2, vs0, vs1
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; CHECK-P9-NEXT: blr
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%v = load <2 x double>, <2 x double>* %p1
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%s = load double, double* %p2
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%r = insertelement <2 x double> %v, double %s, i32 0
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ret <2 x double> %r
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}
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define <2 x double> @testi1(<2 x double>* %p1, double* %p2) {
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; CHECK-LABEL: testi1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lxvd2x vs0, 0, r3
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; CHECK-NEXT: lfd f1, 0(r4)
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; CHECK-NEXT: xxswapd vs0, vs0
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; CHECK-NEXT: xxpermdi v2, vs1, vs0, 1
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; CHECK-NEXT: blr
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;
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; CHECK-P8-BE-LABEL: testi1:
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; CHECK-P8-BE: # %bb.0:
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; CHECK-P8-BE-NEXT: lxvd2x vs0, 0, r3
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; CHECK-P8-BE-NEXT: lfd f1, 0(r4)
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; CHECK-P8-BE-NEXT: xxmrghd v2, vs0, vs1
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; CHECK-P8-BE-NEXT: blr
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;
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; CHECK-P9-VECTOR-LABEL: testi1:
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; CHECK-P9-VECTOR: # %bb.0:
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; CHECK-P9-VECTOR-NEXT: lxvd2x vs0, 0, r3
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; CHECK-P9-VECTOR-NEXT: lfd f1, 0(r4)
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; CHECK-P9-VECTOR-NEXT: xxswapd vs0, vs0
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; CHECK-P9-VECTOR-NEXT: xxpermdi v2, vs1, vs0, 1
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; CHECK-P9-VECTOR-NEXT: blr
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;
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; CHECK-P9-LABEL: testi1:
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; CHECK-P9: # %bb.0:
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; CHECK-P9-NEXT: lxv vs0, 0(r3)
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; CHECK-P9-NEXT: lfd f1, 0(r4)
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; CHECK-P9-NEXT: xxpermdi v2, vs1, vs0, 1
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; CHECK-P9-NEXT: blr
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%v = load <2 x double>, <2 x double>* %p1
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%s = load double, double* %p2
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%r = insertelement <2 x double> %v, double %s, i32 1
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ret <2 x double> %r
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}
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define double @teste0(<2 x double>* %p1) {
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; CHECK-LABEL: teste0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lfd f1, 0(r3)
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; CHECK-NEXT: blr
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;
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; CHECK-P8-BE-LABEL: teste0:
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; CHECK-P8-BE: # %bb.0:
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; CHECK-P8-BE-NEXT: lfd f1, 0(r3)
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; CHECK-P8-BE-NEXT: blr
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;
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; CHECK-P9-VECTOR-LABEL: teste0:
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; CHECK-P9-VECTOR: # %bb.0:
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; CHECK-P9-VECTOR-NEXT: lfd f1, 0(r3)
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; CHECK-P9-VECTOR-NEXT: blr
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;
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; CHECK-P9-LABEL: teste0:
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; CHECK-P9: # %bb.0:
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; CHECK-P9-NEXT: lfd f1, 0(r3)
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; CHECK-P9-NEXT: blr
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%v = load <2 x double>, <2 x double>* %p1
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%r = extractelement <2 x double> %v, i32 0
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ret double %r
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}
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define double @teste1(<2 x double>* %p1) {
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; CHECK-LABEL: teste1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lfd f1, 8(r3)
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; CHECK-NEXT: blr
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;
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; CHECK-P8-BE-LABEL: teste1:
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; CHECK-P8-BE: # %bb.0:
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; CHECK-P8-BE-NEXT: lfd f1, 8(r3)
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; CHECK-P8-BE-NEXT: blr
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;
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; CHECK-P9-VECTOR-LABEL: teste1:
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; CHECK-P9-VECTOR: # %bb.0:
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; CHECK-P9-VECTOR-NEXT: lfd f1, 8(r3)
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; CHECK-P9-VECTOR-NEXT: blr
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;
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; CHECK-P9-LABEL: teste1:
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; CHECK-P9: # %bb.0:
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; CHECK-P9-NEXT: lfd f1, 8(r3)
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; CHECK-P9-NEXT: blr
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%v = load <2 x double>, <2 x double>* %p1
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%r = extractelement <2 x double> %v, i32 1
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ret double %r
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}
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