When the arch in the triple in "spirv", the default target codegen is currently used. We should be using the spir-v target codegen. This will be used to have SPIR-V specific lowering of the HLSL types.
75 lines
3.9 KiB
HLSL
75 lines
3.9 KiB
HLSL
// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -fnative-half-type -triple \
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// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o - | \
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// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL
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// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -fnative-half-type -triple \
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// RUN: spirv-pc-vulkan-compute %s -emit-llvm -disable-llvm-passes -o - | \
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// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV
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// Test basic lowering to runtime function call for int values.
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// CHECK-LABEL: test_int
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int test_int(int expr, uint idx) {
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// CHECK-SPIRV: %[[#entry_tok0:]] = call token @llvm.experimental.convergence.entry()
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// CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.readlane.i32([[TY]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok0]]) ]
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// CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.readlane.i32([[TY]] %[[#]], i32 %[[#]])
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// CHECK: ret [[TY]] %[[RET]]
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return WaveReadLaneAt(expr, idx);
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}
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// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.readlane.i32([[TY]], i32) #[[#attr:]]
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// CHECK-SPIRV: declare spir_func [[TY]] @llvm.spv.wave.readlane.i32([[TY]], i32) #[[#attr:]]
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#ifdef __HLSL_ENABLE_16_BIT
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// CHECK-LABEL: test_int16
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int16_t test_int16(int16_t expr, uint idx) {
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// CHECK-SPIRV: %[[#entry_tok1:]] = call token @llvm.experimental.convergence.entry()
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// CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.readlane.i16([[TY]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok1]]) ]
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// CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.readlane.i16([[TY]] %[[#]], i32 %[[#]])
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// CHECK: ret [[TY]] %[[RET]]
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return WaveReadLaneAt(expr, idx);
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}
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// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.readlane.i16([[TY]], i32) #[[#attr:]]
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// CHECK-SPIRV: declare spir_func [[TY]] @llvm.spv.wave.readlane.i16([[TY]], i32) #[[#attr:]]
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#endif
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// Test basic lowering to runtime function call with array and float values.
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// CHECK-LABEL: test_half
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half test_half(half expr, uint idx) {
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// CHECK-SPIRV: %[[#entry_tok2:]] = call token @llvm.experimental.convergence.entry()
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// CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.readlane.f16([[TY]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok2]]) ]
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// CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.readlane.f16([[TY]] %[[#]], i32 %[[#]])
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// CHECK: ret [[TY]] %[[RET]]
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return WaveReadLaneAt(expr, idx);
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}
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// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.readlane.f16([[TY]], i32) #[[#attr:]]
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// CHECK-SPIRV: declare spir_func [[TY]] @llvm.spv.wave.readlane.f16([[TY]], i32) #[[#attr:]]
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// CHECK-LABEL: test_double
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double test_double(double expr, uint idx) {
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// CHECK-SPIRV: %[[#entry_tok3:]] = call token @llvm.experimental.convergence.entry()
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// CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.readlane.f64([[TY]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok3]]) ]
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// CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.readlane.f64([[TY]] %[[#]], i32 %[[#]])
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// CHECK: ret [[TY]] %[[RET]]
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return WaveReadLaneAt(expr, idx);
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}
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// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.readlane.f64([[TY]], i32) #[[#attr:]]
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// CHECK-SPIRV: declare spir_func [[TY]] @llvm.spv.wave.readlane.f64([[TY]], i32) #[[#attr:]]
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// CHECK-LABEL: test_floatv4
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float4 test_floatv4(float4 expr, uint idx) {
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// CHECK-SPIRV: %[[#entry_tok4:]] = call token @llvm.experimental.convergence.entry()
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// CHECK-SPIRV: %[[RET1:.*]] = call spir_func [[TY1:.*]] @llvm.spv.wave.readlane.v4f32([[TY1]] %[[#]], i32 %[[#]]) [ "convergencectrl"(token %[[#entry_tok4]]) ]
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// CHECK-DXIL: %[[RET1:.*]] = call [[TY1:.*]] @llvm.dx.wave.readlane.v4f32([[TY1]] %[[#]], i32 %[[#]])
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// CHECK: ret [[TY1]] %[[RET1]]
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return WaveReadLaneAt(expr, idx);
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}
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// CHECK-DXIL: declare [[TY1]] @llvm.dx.wave.readlane.v4f32([[TY1]], i32) #[[#attr]]
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// CHECK-SPIRV: declare spir_func [[TY1]] @llvm.spv.wave.readlane.v4f32([[TY1]], i32) #[[#attr]]
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// CHECK: attributes #[[#attr]] = {{{.*}} convergent {{.*}}}
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