Files
clang-p2996/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Simon Pilgrim 9fb4bc5bf4 [DAG] SimplifyMultipleUseDemandedBits - ignore SRL node if we're just demanding known sign bits (#114389)
Check to see if we are only demanding (shifted) signbits from a SRL node that are also signbits in the source node.

We can't demand any upper zero bits that the SRL will shift in (up to max shift amount), and the lower demanded bits bound must already be all signbits.
2024-10-31 16:40:29 +00:00

476 KiB