c65b4d64d4
Alignment of an alloca in IR can be lower than the preferred alignment on purpose, but this override essentially treats the preferred alignment as the minimum alignment. The patch changes this behavior to always use the specified alignment. If alignment is not set explicitly in LLVM IR, it is set to DL.getPrefTypeAlign(Ty) in computeAllocaDefaultAlign. Tests are changed as well: explicit alignment is increased to match the preferred alignment if it changes output, or omitted when it is hard to determine the right value (e.g. for pointers, some structs, or weird types). Differential Revision: https://reviews.llvm.org/D135462
31 lines
1.0 KiB
LLVM
31 lines
1.0 KiB
LLVM
; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel-abort=3 -mcpu=mips32r2 \
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; RUN: < %s -verify-machineinstrs | FileCheck %s
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%struct.x = type { i32 }
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@i = common global i32 0, align 4
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define i32 @foobar(i32 signext %x) {
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entry:
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; CHECK-LABEL: foobar:
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%retval = alloca i32, align 4
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%x.addr = alloca i32, align 4
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%a = alloca %struct.x, align 8
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%c = alloca ptr, align 8
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store i32 %x, ptr %x.addr, align 4
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%0 = load i32, ptr %x.addr, align 4
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store i32 %0, ptr %a, align 4
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store ptr %a, ptr %c, align 4
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%1 = load ptr, ptr %c, align 4
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%2 = load i32, ptr %1, align 4
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store i32 %2, ptr @i, align 4
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%3 = load i32, ptr %retval
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; CHECK: addiu $[[A_ADDR:[0-9]+]], $sp, 8
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; CHECK-DAG: lw $[[I_ADDR:[0-9]+]], %got(i)($[[REG_GP:[0-9]+]])
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; CHECK-DAG: sw $[[A_ADDR]], [[A_ADDR_FI:[0-9]+]]($sp)
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; CHECK-DAG: lw $[[A_ADDR2:[0-9]+]], [[A_ADDR_FI]]($sp)
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; CHECK-DAG: lw $[[A_X:[0-9]+]], 0($[[A_ADDR2]])
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; CHECK-DAG: sw $[[A_X]], 0($[[I_ADDR]])
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ret i32 %3
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}
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