23c0850d2e
https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/56 Resolved https://github.com/llvm/llvm-project/issues/106700. This enables inline asm to have vcix_state to be a clobbered register thus disable reordering between VCIX intrinsics and inline asm.
23 lines
1.0 KiB
LLVM
23 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+xsfvcp \
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; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+xsfvcp \
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; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
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; VCIX instructions can not reorder between each other.
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define void @test_reorder(<vscale x 1 x i64> %vreg) {
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; CHECK-LABEL: test_reorder:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetivli zero, 0, e64, m1, ta, ma
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; CHECK-NEXT: sf.vc.iv 0, 0, v8, 0
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; CHECK-NEXT: #APP
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; CHECK-NEXT: sf.vc.vv 3, 0, v8, v8
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; CHECK-EMPTY:
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; CHECK-NEXT: #NO_APP
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; CHECK-NEXT: ret
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entry:
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call void @llvm.riscv.sf.vc.iv.se.iXLen.nxv1i64.iXLen.iXLen(iXLen 0, iXLen 0, <vscale x 1 x i64> %vreg, iXLen 0, iXLen 0)
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call iXLen asm sideeffect "sf.vc.vv 0x3, 0x0, $1, $1;", "=r,^vr,~{memory},~{vl},~{sf.vcix_state}"(<vscale x 1 x i64> %vreg)
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ret void
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}
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