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clang-p2996/llvm/test/CodeGen/RISCV
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Luke Lau faa385a9f4 [RISCV] Add tests for length changing shuffles 
Tests taken from Luke's 88147 with minimal changes by me (preames).

The main case of interest here is when mask length is less than source
length (i.e. length is decreasing).  We often scalarize these, which
on RISCV can be quite painful.
2024-11-01 09:51:39 -07:00
..
GlobalISel
[RISCV][GISEL] Fix operand on RISCV::G_VMV_V_V_VL
2024-10-21 06:58:12 -07:00
intrinsics
…
rvv
[RISCV] Add tests for length changing shuffles
2024-11-01 09:51:39 -07:00
abds-neg.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
abds.ll
Reapply "[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes." (#112203)
2024-10-15 21:07:06 +08:00
abdu-neg.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
abdu.ll
Reapply "[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes." (#112203)
2024-10-15 21:07:06 +08:00
add-before-shl.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
add-imm.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
addc-adde-sube-subc.ll
…
addcarry.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
addimm-mulimm.ll
[RISCV] Use RISCVISD::SHL_ADD in transformAddShlImm (#89832)
2024-05-13 09:48:46 -07:00
addrspacecast.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
aext-to-sext.ll
…
aext.ll
Add RV64 constraint to SRLIW (#69416)
2023-10-18 15:01:17 +08:00
align-loops.ll
[RISCV] Add searchable table for tune information (#66193)
2023-09-26 12:26:35 +08:00
align.ll
[RISCV] Add searchable table for tune information (#66193)
2023-09-26 12:26:35 +08:00
alloca.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
allow-check.ll
[CodeGen] Add default lowering for llvm.allow.{runtime,ubsan}.check() (#86049)
2024-03-31 22:19:33 -07:00
alu8.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
alu16.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
alu32.ll
[RISCV] Generate pseudo instruction li
2021-11-22 14:01:37 +08:00
alu64.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
analyze-branch.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
and-add-lsr.ll
…
and.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
arith-with-overflow.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
atomic-cmpxchg-branch-on-result.ll
[RISCV] Mark Zacas as non-experimental (#109651)
2024-09-25 06:14:43 +01:00
atomic-cmpxchg-flag.ll
…
atomic-cmpxchg.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
atomic-fence.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
atomic-load-store.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
atomic-rmw-discard.ll
[RISCV] Enable load clustering by default (#73789)
2024-10-01 13:45:30 +01:00
atomic-rmw-sub.ll
…
atomic-rmw.ll
[RISCV] Enable load clustering by default (#73789)
2024-10-01 13:45:30 +01:00
atomic-signext.ll
[RISCV] Enable load clustering by default (#73789)
2024-10-01 13:45:30 +01:00
atomicrmw-cond-sub-clamp.ll
[RISCV] Enable load clustering by default (#73789)
2024-10-01 13:45:30 +01:00
atomicrmw-uinc-udec-wrap.ll
[RISCV] Enable load clustering by default (#73789)
2024-10-01 13:45:30 +01:00
attributes-module-flag.ll
[RISCV] Make M imply Zmmul (#95070)
2024-06-21 11:11:10 +08:00
attributes.ll
[RISCV] Mark RVB23U64 and RVB23S64 as non-experimental (#113918)
2024-10-29 07:57:34 +00:00
avgceils.ll
[RISCV] Add scalar type test coverage for ISD::AVG nodes
2024-06-15 16:15:50 +01:00
avgceilu.ll
[RISCV] Add scalar type test coverage for ISD::AVG nodes
2024-06-15 16:15:50 +01:00
avgfloors.ll
[RISCV] Add scalar type test coverage for ISD::AVG nodes
2024-06-15 16:15:50 +01:00
avgflooru.ll
Recommit "[DAG] Reducing instructions by better legalization handling of AVGFLOORU for illegal data types" (#101223)
2024-07-30 19:00:46 -07:00
bf16-promote.ll
…
bfloat-arith.ll
[RISCV] Custom legalize f16/bf16 FCOPYSIGN with Zfhmin/Zbfmin. (#107039)
2024-09-02 22:04:09 -07:00
bfloat-br-fcmp.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-convert.ll
[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions. (#107011)
2024-09-03 15:34:25 -07:00
bfloat-fcmp.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-frem.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-imm.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-isnan.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-mem.ll
[RISCV] Remove experimental for bf16 extensions (#97996)
2024-07-09 14:34:03 +08:00
bfloat-select-fcmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
bfloat-select-icmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
bfloat.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
bitextract-mac.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
bitreverse-shift.ll
[DAG] Fold bitreverse(shl/srl(bitreverse(x),y)) -> srl/shl(x,y) (#89897)
2024-05-06 11:13:05 +01:00
bittest.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
blockaddress.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
branch_zero.ll
[RISCV] Omit SRA in case of setlt or setge with zero constant
2022-12-21 14:19:49 +03:00
branch-on-zero.ll
Revert "[LSR][TTI][RISCV] Disable terminator folding for RISC-V."
2024-01-11 13:20:02 -08:00
branch-opt.ll
[RISCV] CSE by swapping conditional branches (#71111)
2023-11-03 09:03:52 -07:00
branch-opt.mir
[RISCV] Make sure ADDI replacement in optimizeCondBranch has a virtual reg destination. (#81938)
2024-02-15 16:34:40 -08:00
branch-relaxation.ll
[RISCV] fix SP recovery in a function epilogue (#110809)
2024-10-04 12:22:11 +03:00
branch.ll
[RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
2023-09-20 01:02:19 +08:00
bswap-bitreverse.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
bswap-shift.ll
[RISCV] ISel (and (shift X, C1), C2)) to shift pair in more cases
2022-03-30 11:46:42 -07:00
byval.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
callee-saved-fpr32s.ll
[RISCV] Enable load clustering by default (#73789)
2024-10-01 13:45:30 +01:00
callee-saved-fpr64s.ll
[RISCV] Enable load clustering by default (#73789)
2024-10-01 13:45:30 +01:00
callee-saved-gprs.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
calling-conv-half.ll
[RISCV] Add constant folding combine for FMV_X_ANYEXTW/H. (#106653)
2024-08-30 09:43:42 -07:00
calling-conv-ilp32-ilp32f-common.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
calling-conv-ilp32.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
calling-conv-ilp32d.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
calling-conv-ilp32e.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
calling-conv-ilp32f-ilp32d-common.ll
…
calling-conv-lp64-lp64f-common.ll
…
calling-conv-lp64-lp64f-lp64d-common.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
calling-conv-lp64.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
calling-conv-lp64e.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
calling-conv-rv32f-ilp32.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
calling-conv-rv32f-ilp32e.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
calling-conv-sext-zext.ll
…
calling-conv-vector-float.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
calling-conv-vector-on-stack.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
calls.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
clear-cache.ll
[RISCV] Lower llvm.clear_cache to __riscv_flush_icache for glibc targets (#93481)
2024-06-20 07:27:07 +02:00
cm_mvas_mvsa.ll
…
cm_mvas_mvsa.mir
…
cmov-branch-opt.ll
…
cmp-bool.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
codemodel-lowering.ll
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
compress-double.ll
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
2023-12-14 22:42:11 -08:00
compress-float.ll
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
2023-12-14 22:42:11 -08:00
compress-inline-asm.ll
[RISCV] Remove blank lines at the end of testcases. NFC.
2024-01-02 13:13:04 +08:00
compress-opt-branch.ll
…
compress-opt-select.ll
[RISCV] Autogenerate compress-opt-select.ll
2024-09-17 08:47:20 -07:00
compress.ll
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
2023-12-14 22:42:11 -08:00
condbinops.ll
[RISCV] Graduate Zicond to non-experimental (#79811)
2024-01-29 15:58:54 +00:00
condops.ll
[RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)
2024-07-27 17:26:32 -07:00
convert-highly-predictable-select-to-branch.ll
[RISCV] Add FeaturePredictableSelectIsExpensive
2024-07-05 11:29:42 +08:00
copy-frameindex.mir
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
copyprop.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
copysign-casts.ll
[RISCV] Custom legalize f16/bf16 FCOPYSIGN with Zfhmin/Zbfmin. (#107039)
2024-09-02 22:04:09 -07:00
ctlz-cttz-ctpop.ll
[RISCV] Simplify (srl (and X, Mask), Const) to TH_EXTU (#102802)
2024-08-16 14:23:00 +08:00
ctz_zero_return_test.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
disable-tail-calls.ll
[RISCV] Lower the tail pseudoinstruction
2018-05-23 22:44:08 +00:00
disjoint.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
div_minsize.ll
[RISCV] Remove blank lines at the end of testcases. NFC.
2024-01-02 13:13:04 +08:00
div-by-constant.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
div-pow2.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
div.ll
[TargetLowering][AMDGPU][ARM][RISCV][X86] Teach SimplifyDemandedBits to combine (srl (sra X, C1), ShAmt) -> sra(X, C1+ShAmt) (#101751)
2024-08-14 08:44:57 -07:00
double_reduct.ll
[RISCV] Remove unecessary early exit in transferBefore (#74040)
2023-12-12 17:25:19 +09:00
double-arith-strict.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-arith.ll
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)
2024-09-06 15:50:29 -07:00
double-bitmanip-dagcombines.ll
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)
2024-09-06 15:50:29 -07:00
double-br-fcmp.ll
…
double-calling-conv.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
double-convert-strict.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
double-convert.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
double-fcmp-strict.ll
[RISCV] Enable floating point CSR alias mnemonics for Zfinx. (#108464)
2024-09-12 18:40:52 -07:00
double-fcmp.ll
…
double-frem.ll
…
double-imm.ll
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)
2024-09-06 15:50:29 -07:00
double-intrinsics-strict.ll
[Test] Fix usage of constrained intrinsics (#113523)
2024-10-28 14:07:32 +07:00
double-intrinsics.ll
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)
2024-09-06 15:50:29 -07:00
double-isnan.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-maximum-minimum.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-mem.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-previous-failure.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-round-conv-sat.ll
[DAGCombiner] Push freeze through SETCC and SELECT_CC (#64718)
2024-07-22 16:01:59 +02:00
double-round-conv.ll
[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (#107361)
2024-09-05 08:42:13 -07:00
double-select-fcmp.ll
…
double-select-icmp.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-stack-spill-restore.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
double-zfa.ll
[RISCV] Move the rest of Zfa FLI instruction handling to lowerConstantFP. (#109217)
2024-09-19 15:16:10 -07:00
dso_local_equivalent.ll
[MC][CodeGen] Define R_RISCV_PLT32 and lower dso_local_equivalent to it
2023-02-23 01:26:27 +00:00
dwarf-eh.ll
[test] Change llc -march= to -mtriple= & llvm-mc -arch= to -triple=
2023-09-11 15:11:01 -07:00
early-clobber-tied-def-subreg-liveness.ll
[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)
2024-09-30 11:44:23 -07:00
eh-dwarf-cfa.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
elf-preemption.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
emutls.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
exception-pointer-register.ll
…
fastcc-bf16.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
fastcc-float.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
fastcc-half.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
fastcc-int.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
fastcc-without-f-reg.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
fixups-diff.ll
[MC] Rename temporary symbols of empty name to ".L0 " (#89693)
2024-04-26 08:30:27 -07:00
fli-licm.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
float-arith-strict.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
float-arith.ll
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
float-bit-preserving-dagcombines.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
float-bitmanip-dagcombines.ll
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
float-br-fcmp.ll
…
float-convert-strict.ll
[RISCV] Add some Zfinx instructions to hasAllNBitUsers.
2024-08-08 17:33:54 -07:00
float-convert.ll
[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (#107361)
2024-09-05 08:42:13 -07:00
float-fcmp-strict.ll
[RISCV] Enable floating point CSR alias mnemonics for Zfinx. (#108464)
2024-09-12 18:40:52 -07:00
float-fcmp.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
float-frem.ll
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
float-imm.ll
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
float-intrinsics-strict.ll
[Test] Fix usage of constrained intrinsics (#113523)
2024-10-28 14:07:32 +07:00
float-intrinsics.ll
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
float-isnan.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-maximum-minimum.ll
[RISCV] Add no NaN support to lowerFMAXIMUM_FMINIMUM.
2023-08-01 09:51:24 -07:00
float-mem.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
float-round-conv-sat.ll
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)
2024-09-06 15:50:29 -07:00
float-round-conv.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
float-select-fcmp.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-select-icmp.ll
[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
2023-06-17 10:10:20 +08:00
float-select-verify.ll
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
2024-02-01 22:10:52 +08:00
float-zfa.ll
[RISCV] Move the rest of Zfa FLI instruction handling to lowerConstantFP. (#109217)
2024-09-19 15:16:10 -07:00
flt-rounds.ll
[Intrinsic] Rename flt.rounds intrinsic to get.rounding
2022-12-19 15:22:39 +08:00
fmax-fmin.ll
…
fold-addi-loadstore.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
fold-binop-into-select-return-constant.ll
[RISCV] Add a check in lowerSELECT after foldBinOpIntoSelectIfProfitable (#97391)
2024-07-05 10:55:36 +08:00
fold-binop-into-select.ll
Reapply [RISCV] Fold binary op into select if profitable.
2023-07-14 15:30:54 -04:00
forced-atomics.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
fp16-promote.ll
…
fp128.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
fp-fcanonicalize.ll
RISC-V: Select FCANONICALIZE (#112083)
2024-10-14 14:12:36 +08:00
fpclamptosat.ll
[RISCV] Enable load clustering by default (#73789)
2024-10-01 13:45:30 +01:00
fpenv.ll
[RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressibility
2022-12-22 14:19:26 -08:00
frame-info.ll
…
frame.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
frameaddr-returnaddr.ll
…
frm-dependency.ll
[RISCV] Update some tests to use floating point ABI where it makes sense.
2022-02-24 09:27:57 -08:00
get-register-invalid.ll
…
get-register-noreserve.ll
…
get-register-reserve.ll
…
get-setcc-result-type.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
ghccc-nest.ll
[RISCV] Add support for static chain
2022-11-09 16:10:32 +08:00
ghccc-rv32.ll
…
ghccc-rv64.ll
…
ghccc-without-f-reg.ll
…
global-merge-minsize-smalldata-nonzero.ll
[GlobalMerge] Add MinSize feature to the GlobalMerge Pass. (#93686)
2024-06-03 09:10:56 -04:00
global-merge-minsize-smalldata-zero.ll
[GlobalMerge] Add MinSize feature to the GlobalMerge Pass. (#93686)
2024-06-03 09:10:56 -04:00
global-merge-minsize.ll
[GlobalMerge] Add MinSize feature to the GlobalMerge Pass. (#93686)
2024-06-03 09:10:56 -04:00
global-merge-offset.ll
…
global-merge.ll
…
graalcc.ll
[IR] Add GraalVM calling conventions
2023-11-17 16:30:09 +00:00
half-arith-strict.ll
[RISCV] Custom legalize f16/bf16 FNEG/FABS with Zfhmin/Zbfmin. (#106886)
2024-08-31 23:57:40 -07:00
half-arith.ll
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
half-bitmanip-dagcombines.ll
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
half-br-fcmp.ll
…
half-convert-strict.ll
[RISCV] Support STRICT_UINT_TO_FP and STRICT_SINT_TO_FP (#102503)
2024-09-17 11:21:52 -03:00
half-convert.ll
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
half-fcmp-strict.ll
[RISCV] Enable floating point CSR alias mnemonics for Zfinx. (#108464)
2024-09-12 18:40:52 -07:00
half-fcmp.ll
…
half-frem.ll
…
half-imm.ll
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
half-intrinsics.ll
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
half-isnan.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-maximum-minimum.ll
[RISCV] Add no NaN support to lowerFMAXIMUM_FMINIMUM.
2023-08-01 09:51:24 -07:00
half-mem.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
half-round-conv-sat.ll
[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)
2024-09-06 15:50:29 -07:00
half-round-conv.ll
[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (#107361)
2024-09-05 08:42:13 -07:00
half-select-fcmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
half-select-icmp.ll
[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)
2024-09-03 16:04:51 -07:00
half-zfa-fli.ll
…
half-zfa.ll
[RISCV] Move the rest of Zfa FLI instruction handling to lowerConstantFP. (#109217)
2024-09-19 15:16:10 -07:00
hoist-global-addr-base.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
hwasan-check-memaccess.ll
[RISCV] Use RISCVAsmPrinter::EmitToStreamer for EmitHwasanMemaccessSymbols. (#111792)
2024-10-10 08:43:30 -07:00
i32-icmp.ll
…
i64-icmp.ll
…
iabs.ll
Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..."
2024-04-29 13:08:52 +02:00
idiv_large.ll
[CodeGen] Always expand division larger than i128
2023-03-01 15:33:45 +01:00
imm-cse.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
imm.ll
[RISCV] Improve hasAllNBitUsers for users of SLLI.
2024-08-03 18:19:40 -07:00
indirectbr.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
init-array.ll
[RISCV] Remove blank lines at the end of testcases. NFC.
2024-01-02 13:13:04 +08:00
inline-asm-abi-names.ll
[RISCV] Remove gp and tp from callee saved register lists. (#76483)
2023-12-27 21:36:03 -08:00
inline-asm-clobbers.ll
…
inline-asm-d-abi-names.ll
[RISCV][NFC] Regenerate RISCV CodeGen tests
2020-12-09 19:42:49 +00:00
inline-asm-d-constraint-f.ll
[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)
2024-10-18 10:40:38 +01:00
inline-asm-d-modifier-N.ll
[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)
2024-10-18 10:40:38 +01:00
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)
2024-10-18 10:40:38 +01:00
inline-asm-f-modifier-N.ll
[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)
2024-10-18 10:40:38 +01:00
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)
2024-10-18 10:40:38 +01:00
inline-asm-mem-constraint-2.ll
[test][RISCV] Precommit inline asm tests for #104925
2024-08-26 13:30:23 +03:00
inline-asm-mem-constraint.ll
[RISCV] Support the large code model. (#70308)
2024-09-09 09:15:07 +08:00
inline-asm-s-constraint-error.ll
[RISCV] Support constraint "s" (#80201)
2024-02-01 10:18:42 -08:00
inline-asm-s-constraint.ll
[RISCV] Support constraint "s" (#80201)
2024-02-01 10:18:42 -08:00
inline-asm-v-constraint.ll
[RISCV] Add support for inline asm constraint vd (#111653)
2024-10-14 10:47:59 +08:00
inline-asm-xsfvcp.ll
[RISCV][VCIX] Add vcix_state to GNU inline assembly register set (#106914)
2024-09-30 23:52:35 -07:00
inline-asm-zdinx-constraint-r.ll
[RISCV] Support inline assembly 'f' constraint for Zfinx. (#112986)
2024-10-18 18:17:23 -07:00
inline-asm-zfh-constraint-f.ll
[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)
2024-10-18 10:40:38 +01:00
inline-asm-zfh-modifier-N.ll
[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)
2024-10-18 10:40:38 +01:00
inline-asm-zfinx-constraint-r.ll
[RISCV] Support inline assembly 'f' constraint for Zfinx. (#112986)
2024-10-18 18:17:23 -07:00
inline-asm-zhinx-constraint-r.ll
[RISCV] Support inline assembly 'f' constraint for Zfinx. (#112986)
2024-10-18 18:17:23 -07:00
inline-asm.ll
[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)
2024-10-18 10:40:38 +01:00
inline-option-directive.ll
[RISCV] Support '.option arch' directive
2023-05-26 18:39:41 +08:00
instruction-count-remark.mir
[CodeGen] Fix InstructionCount remarks for MI bundles (#107621)
2024-10-02 13:37:25 -07:00
interrupt-attr-args-error.ll
[RISCV] Update some tests that used "interrupt"="user". NFC
2023-05-31 20:31:24 -07:00
interrupt-attr-callee.ll
…
interrupt-attr-invalid.ll
Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
2020-02-13 10:16:06 -08:00
interrupt-attr-nocall.ll
…
interrupt-attr-ret-error.ll
[RISCV] Update some tests that used "interrupt"="user". NFC
2023-05-31 20:31:24 -07:00
interrupt-attr.ll
[RISCV] Remove interrupt handler special case from RISCVFrameLowering::determineCalleeSaves. (#88069)
2024-04-10 10:28:54 -07:00
intrinsic-cttz-elts-vscale.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
intrinsic-cttz-elts.ll
…
isel-optnone.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
jumptable-swguarded.ll
[RISCV] Insert simple landing pad for taken address labels. (#91855)
2024-08-06 22:04:48 +08:00
jumptable.ll
[RISCV] Add MinimumJumpTableEntries to TuneInfo (#72963)
2023-11-23 14:05:23 +08:00
kcfi-isel-mir.ll
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
kcfi-mir.ll
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
kcfi-patchable-function-prefix.ll
MachineFunction: -fsanitize={function,kcfi}: ensure 4-byte alignment
2023-06-30 09:13:19 -07:00
kcfi.ll
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
lack-of-signed-truncation-check.ll
[RISCV] Select (and (sra x, c2), c1) as (srli (srai x, c2-c3), c3). (#101868)
2024-08-04 22:35:38 -07:00
large-stack.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
legalize-fneg.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
libcall-tail-calls.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
lit.local.cfg
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
live-sp.mir
[MachineFrameInfo] Refactoring around computeMaxcallFrameSize() (NFC) (#78001)
2024-03-18 10:37:59 -04:00
llvm.exp10.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
llvm.frexp.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
load-setcc-combine.ll
[DAGCombiner] Allow tryToFoldExtOfLoad to use a sextload for zext nneg. (#81714)
2024-02-17 11:37:13 -08:00
local-stack-slot-allocation.ll
[RISCV] Don't exlude the frame pointer from the callee saved registers in RISCVRegisterInfo::needsFrameBaseReg.
2024-05-13 12:58:30 -07:00
loop-strength-reduce-add-cheaper-than-mul.ll
…
loop-strength-reduce-loop-invar.ll
[RISCV][LSR] Account for temporary register for base addition (#92296)
2024-05-22 13:38:39 -07:00
lpad.ll
[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)
2024-08-08 13:22:59 +08:00
lsr-legaladdimm.ll
…
machine-combiner-mir.ll
…
machine-combiner-strategies.ll
…
machine-combiner.ll
[RISCV] Model integer min max instructions from Zbb execute in late-B ALU
2024-03-14 06:02:53 -07:00
machine-combiner.mir
[RISCV] Clear kill flags when forming FMA instructions in MachineCombiner.
2023-07-12 08:03:45 -07:00
machine-cp.mir
Revert "[MCP] Enhance MCP copy Instruction removal for special case (#70778)"
2023-11-27 19:39:40 +01:00
machine-cse.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
machine-outliner-and-machine-copy-propagation.ll
…
machine-outliner-cfi.mir
…
machine-outliner-patchable.ll
[MachineOutliner] Don't outline functions starting with PATCHABLE_FUNCTION_ENTER/FENTRL_CALL
2021-12-13 13:24:29 -08:00
machine-outliner-position.mir
…
machine-outliner-throw.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
machine-sink-load-immediate.ll
[RISCV] Add a testcase for an unprofitable machine-sink issue
2024-09-16 14:17:42 -07:00
machinelicm-address-pseudos.ll
…
machinelicm-constant-phys-reg.ll
[MachineLICM] Hoist copies of constant physical register (#93285)
2024-05-29 14:10:01 +08:00
machineoutliner-jumptable.mir
…
machineoutliner-pcrel-lo.mir
[RISCV] Don't outline pcrel_lo when the function has a section prefix (#107943)
2024-09-11 09:53:11 -07:00
machineoutliner.mir
[test] -march -> -mtriple (#67741)
2023-09-29 10:43:23 -07:00
MachineSink-implicit-x0.mir
Fix minor deficiency in machine-sink.
2021-11-12 08:01:13 +01:00
macro-fusion-lui-addi.ll
…
macro-fusions.mir
…
make-compressible-for-store-address.mir
…
make-compressible-rv64.mir
…
make-compressible-zbc-zhinx.mir
[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)
2024-09-26 22:56:12 -07:00
make-compressible-zbc.mir
[RISCV] Fix IR for store_large_offset_no_opt_i16 in make-compressible-zbc.mir. NFC
2024-09-16 12:51:07 -07:00
make-compressible-zfinx.mir
[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)
2024-10-01 22:09:27 -07:00
make-compressible.mir
[RISCV] Teach RISCVMakeCompressible handle Zca/Zcf/Zce/Zcd. (#81844)
2024-02-22 15:51:19 +08:00
mem64.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
mem.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
memcpy-inline.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
memcpy.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
memset-inline.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
min-max.ll
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
mir-target-flags.ll
[RISCV] Merge machine operand flag MO_PLT into MO_CALL (#77253)
2024-01-07 12:43:39 -08:00
misched-load-clustering.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
misched-postra-direction.mir
[CodeGen][MISched] Add misched post-regalloc bidirectional scheduling (#77138)
2024-03-25 10:10:35 -04:00
miss-sp-restore-eh.ll
…
module-elf-flags.ll
Reapply "[RISCV] Remove experimental from Ztso. (#96465)"
2024-07-09 10:45:56 -07:00
module-target-abi2.ll
[RISCV] Generate correct ELF EFlags when .ll file has target-abi attribute
2022-03-24 00:48:52 +08:00
module-target-abi3.ll
[RISCV] Generate correct ELF abi flag when empty .ll file has target-abi attribute
2022-08-26 14:39:39 +08:00
module-target-abi.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
mul.ll
[RISCV] Enable load clustering by default (#73789)
2024-10-01 13:45:30 +01:00
musttail-call.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
naked-fn-with-frame-pointer.ll
[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)
2024-10-18 09:35:42 +04:00
narrow-shl-cst.ll
…
neg-abs.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
nest-register.ll
…
nomerge.ll
…
nontemporal-scalable.ll
…
nontemporal.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
O0-pipeline.ll
[RISCV] Add additional fence for amocas when required by recent ABI change (#101023)
2024-09-19 13:39:56 +01:00
O3-pipeline.ll
[RISCV] Add additional fence for amocas when required by recent ABI change (#101023)
2024-09-19 13:39:56 +01:00
opt-w-instrs.mir
…
option-nopic.ll
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
2023-12-14 22:42:11 -08:00
option-norelax.ll
…
option-norvc.ll
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
2020-03-15 17:46:23 -07:00
option-pic.ll
[RISCV] Support printing immediate of RISCV MCInst in hexadecimal format (#74053)
2023-12-14 22:42:11 -08:00
option-relax-relocation.ll
[RISCV] Force relocations if initial MCSubtargetInfo contains FeatureRelax (#77436)
2024-01-09 11:24:21 -08:00
option-relax.ll
[llvm-objdump] -d: print 00000000 <foo>: instead of 00000000 foo:
2020-03-05 18:05:28 -08:00
option-rvc.ll
…
optnone-store-no-combine.ll
…
or-is-add.ll
[RISCV] Use disjoint flag in or_is_add.
2024-01-30 22:12:28 -08:00
orc-b-patterns.ll
[RISCV] Re-generate orc-b-patterns.ll for store clustering. NFC
2024-10-11 14:28:51 -07:00
out-of-reach-emergency-slot.mir
[RISCV] fix SP recovery in a function epilogue (#110809)
2024-10-04 12:22:11 +03:00
overflow-intrinsic-optimizations.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
overflow-intrinsics.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
patchable-function-entry.ll
[MC] Parse SHF_LINK_ORDER argument before section group name (#77407)
2024-01-09 10:42:34 -08:00
pei-crash.ll
[RISCV] Fix crash in PEI with empty entry block with Zcmp (#72117)
2023-11-17 16:18:44 +01:00
pic-models.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
pr40333.ll
[RISCV] Custom-legalise 32-bit variable shifts on RV64
2019-01-25 05:04:00 +00:00
pr51206.ll
[CGP] Permit tail call optimization on undefined return value
2024-02-22 10:09:15 +01:00
pr53662.mir
[RISCV] Don't getDebugLoc for the end node of MBB iterator
2022-04-30 16:00:20 +08:00
pr55201.ll
[DAGCombiner] When matching a disguised rotate by constant don't forget to apply LHSMask/RHSMask.
2022-04-30 11:02:30 -07:00
pr56110.ll
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
2024-04-16 15:40:32 -07:00
pr56457.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
pr58025.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
pr58286.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
pr58511.ll
[DAGCombine] Make sure combined nodes are added back to the worklist in topological order.
2023-06-13 09:14:37 +00:00
pr63365.ll
[CodeGenPrepare][RISCV] Remove asserting VH references before erasing the dead GEP
2023-06-18 23:40:47 +08:00
pr63816.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
pr64503.ll
[DAG] FoldSetCC - add missing icmp(X,undef) -> isTrueWhenEqual case (REAPPLIED)
2023-09-13 12:33:39 +01:00
pr64645.ll
[RISCV] Use REG_SEQUENCE/EXTRACT_SUBREG to move between individual GPRs and GPRPair. (#85887)
2024-03-20 08:44:24 -07:00
pr64772.ll
[DAGCombiner][RISCV] Return SDValue(N, 0) instead of SDValue() after 2 calls to CombineTo in visitSTORE.
2023-08-17 15:13:36 -07:00
pr64935.ll
[SDAG][RISCV] Avoid folding setcc (xor C1, -1), C2, cond into setcc (xor C2, -1), C1, cond
2023-08-24 04:18:17 +08:00
pr65025.ll
[RISCV] Prevent tryToFoldBNEOnCmpXchgResult from deleting AND if it has others users.
2023-08-28 10:11:12 -07:00
pr66603.ll
[DAG] canCreateUndefOrPoison - remove AssertSext/AssertZext assumption that they never create undef/poison
2023-10-19 13:28:53 +01:00
pr68855.ll
[RISCV][SDAG] Fix constant narrowing when narrowing loads (#69015)
2023-10-14 06:38:17 +08:00
pr69586.ll
[RISCV] Support postRA vsetvl insertion pass (#70549)
2024-05-21 14:42:55 +08:00
pr80052.mir
[StackSlotColoring] Ignore non-spill objects in RemoveDeadStores. (#80242)
2024-02-01 13:25:15 -08:00
pr84200.ll
[RISCV] Insert a freeze before converting select to AND/OR. (#84232)
2024-03-07 15:03:51 -08:00
pr84653_pr85190.ll
[DAGCombiner] Freeze maybe poison operands when folding select to logic (#84924)
2024-07-22 17:19:46 +02:00
pr88365.ll
[LLVM] [MC] Update frame layout & CFI generation to handle frames larger than 2gb (#99263)
2024-07-23 09:43:30 -07:00
pr90652.ll
[RISCV][ISel] Fix types in tryFoldSelectIntoOp (#90659)
2024-05-01 06:51:36 +08:00
pr90730.ll
[RISCV][ISel] Allow opaque constants in hasAndNotCompare (#92926)
2024-05-22 00:48:26 +08:00
pr92193.ll
[DAGCombiner] Mark vectors as not AllAddOne/AllSubOne on type mismatch (#92195)
2024-05-15 12:39:28 -07:00
pr94145.ll
[DAG] canCreateUndefOrPoison - fix missing argument typo
2024-06-02 10:34:48 +01:00
pr94265.ll
[RISCV] Replace hasStdExtV with hasVInstructions in isTruncateFree.
2024-07-29 17:15:02 -07:00
pr95271.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
pr95284.ll
[DAG] SimplifyMultipleUseDemandedBits - ignore SRL node if we're just demanding known sign bits (#114389)
2024-10-31 16:40:29 +00:00
pr96366.ll
[SDAG] Intersect poison-generating flags after CSE (#97434)
2024-07-03 20:32:46 +08:00
pr97304.ll
[RISCV] Add correct MachinePointerInfo when putting arguments on the stack. (#110140)
2024-09-27 13:48:01 -07:00
prefer-w-inst.ll
[RISCV] Generate more W instructons
2024-04-16 15:37:31 +08:00
prefer-w-inst.mir
…
prefetch.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
prolog-epilogue.ll
…
push-pop-opt-crash.ll
…
push-pop-popret.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
readcyclecounter.ll
[RISCV] Support @llvm.readcyclecounter() Intrinsic
2019-07-05 12:35:21 +00:00
readsteadycounter.ll
[RISCV] Support llvm.readsteadycounter intrinsic
2024-02-21 13:12:14 +08:00
reduce-unnecessary-extension.ll
…
reduction-formation.ll
[RISCV] Enable load clustering by default (#73789)
2024-10-01 13:45:30 +01:00
redundant-copy-from-tail-duplicate.ll
[RISCV] Add reductions to list of roots in tryToReduceVL (#107595)
2024-09-10 18:47:20 -07:00
regalloc-last-chance-recoloring-failure.ll
[InitUndef] Enable the InitUndef pass on non-AMDGPU targets (#108353)
2024-09-16 09:48:25 +02:00
relax-per-target-feature.ll
…
rem.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
remat.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
renamable-copy.mir
[TII][RISCV] Add renamable bit to copyPhysReg (#91179)
2024-08-27 10:08:43 +08:00
repeated-fp-divisors.ll
…
reserved-reg-errors.ll
[RISCV] Add support for -ffixed-xX flags
2019-10-22 21:25:01 +01:00
reserved-regs.ll
[CodeGen][RISCV] Change Shadow Call Stack Register to X3
2023-04-12 21:06:22 +00:00
riscv-codegen-prepare-atp.ll
[RISCV] Implement RISCVTTIImpl::shouldConsiderAddressTypePromotion for RISCV (#102560)
2024-08-15 10:37:04 +08:00
riscv-codegenprepare-asm.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
riscv-codegenprepare.ll
[RISCV] Don't look for sext in RISCVCodeGenPrepare::visitAnd.
2024-01-19 14:44:47 -08:00
riscv-func-target-feature.ll
…
riscv-shifted-extend.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
riscv-tail-dup-size.ll
[RISCV] Increase default tail duplication threshold to 6 at -O3 (#98873)
2024-08-01 12:24:25 +08:00
rotl-rotr.ll
…
rv32-fuchsia.ll
…
rv32e.ll
[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)
2024-01-16 20:44:30 +08:00
rv32i-rv64i-float-double.ll
…
rv32i-rv64i-half.ll
…
rv32xtheadba.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
rv32xtheadbb.ll
[RISCV] Make (sext_inreg X, i1) legal for XTHeadBb to cover the existing isel pattern.
2024-10-11 16:16:07 -07:00
rv32xtheadbs.ll
[RISCV] Remove blank lines at the end of testcases. NFC.
2024-01-02 13:13:04 +08:00
rv32zba.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
rv32zbb-intrinsic.ll
…
rv32zbb-zbkb.ll
…
rv32zbb.ll
Reland [CodeGenPrepare] Convert ctpop(X) ==/!= 1 into ctpop(X) u</u> 2/1 (#111284) (#111998)
2024-10-15 08:17:50 +08:00
rv32zbc-intrinsic.ll
…
rv32zbc-zbkc-intrinsic.ll
…
rv32zbkb-intrinsic.ll
…
rv32zbkb.ll
[RISCV] Support zext.h mnemonic with Zbkb. (#96821)
2024-06-27 09:31:26 -07:00
rv32zbkx-intrinsic.ll
…
rv32zbs.ll
[RISCV][ISel] Select binvi for pattern icmp eq/ne X, pow2 (#110957)
2024-10-03 15:13:02 +08:00
rv32zimop-intrinsic.ll
…
rv32zknd-intrinsic-autoupgrade.ll
…
rv32zknd-intrinsic.ll
…
rv32zkne-intrinsic-autoupgrade.ll
…
rv32zkne-intrinsic.ll
…
rv32zknh-intrinsic.ll
…
rv32zksed-intrinsic-autoupgrade.ll
…
rv32zksed-intrinsic.ll
…
rv32zksh-intrinsic.ll
…
rv64-large-stack.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
rv64-patchpoint.ll
[RISCV] Implement Statepoint and Patchpoint lowering to call instructions (#77337)
2024-04-11 12:19:56 +08:00
rv64-stackmap-frame-setup.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
rv64-stackmap-nops.ll
[RISCV] Add Stackmap/Statepoint/Patchpoint support without targets
2023-10-11 09:18:55 +05:30
rv64-stackmap.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
rv64-statepoint-call-lowering-x1.ll
…
rv64-statepoint-call-lowering-x2.ll
…
rv64-statepoint-call-lowering.ll
…
rv64-trampoline.ll
[RISCV] Implement trampolines for rv64 (#96309)
2024-10-18 08:06:47 +02:00
rv64-typepromotion.ll
…
rv64d-double-convert-strict.ll
…
rv64d-double-convert.ll
…
rv64e.ll
[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)
2024-01-16 20:44:30 +08:00
rv64f-float-convert-strict.ll
[RISCV] Set target-abi explicitly to reduce codegen results
2022-06-01 13:49:23 +08:00
rv64f-float-convert.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
rv64i-complex-float.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
rv64i-demanded-bits.ll
[RISCV][ISel] Eliminate andi rd, rs1, -1 instructions (#89976)
2024-04-25 14:22:14 +08:00
rv64i-double-softfloat.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
rv64i-exhaustive-w-insts.ll
…
rv64i-shift-sext.ll
[RISCV] Enable load clustering by default (#73789)
2024-10-01 13:45:30 +01:00
rv64i-single-softfloat.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
…
rv64m-exhaustive-w-insts.ll
…
rv64m-w-insts-legalization.ll
…
rv64xtheadba.ll
[RISCV] Strength reduce mul by 2^N - 2^M (#88983)
2024-06-20 07:36:48 -07:00
rv64xtheadbb.ll
[RISCV] Make (sext_inreg X, i1) legal for XTHeadBb to cover the existing isel pattern.
2024-10-11 16:16:07 -07:00
rv64xtheadbs.ll
[RISCV] Remove blank lines at the end of testcases. NFC.
2024-01-02 13:13:04 +08:00
rv64zba.ll
[RISCV][ISel] Allow emitting addiw with u32simm12 rhs (#111116)
2024-10-05 09:23:29 +08:00
rv64zbb-intrinsic.ll
…
rv64zbb-zbkb.ll
…
rv64zbb.ll
Reland [CodeGenPrepare] Convert ctpop(X) ==/!= 1 into ctpop(X) u</u> 2/1 (#111284) (#111998)
2024-10-15 08:17:50 +08:00
rv64zbc-intrinsic.ll
…
rv64zbc-zbkc-intrinsic.ll
…
rv64zbkb-intrinsic.ll
…
rv64zbkb.ll
[RISCV] Support zext.h mnemonic with Zbkb. (#96821)
2024-06-27 09:31:26 -07:00
rv64zbkx-intrinsic.ll
…
rv64zbs.ll
[RISCV][DAGCombine] Combine sext_inreg (shl X, Y), i32 into sllw X, Y (#111101)
2024-10-04 16:03:09 +08:00
rv64zfh-half-convert-strict.ll
…
rv64zfh-half-convert.ll
[RISCV] Don't combine (sext_inreg (fmv_x_anyexth X), i16) with Zhinx.
2024-08-14 15:18:10 -07:00
rv64zfh-half-intrinsics.ll
…
rv64zfhmin-half-convert-strict.ll
[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)
2024-09-03 13:33:14 -07:00
rv64zfhmin-half-convert.ll
[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)
2024-09-03 13:33:14 -07:00
rv64zfhmin-half-intrinsics.ll
…
rv64zimop-intrinsic.ll
…
rv64zknd-intrinsic.ll
…
rv64zknd-zkne-intrinsic.ll
…
rv64zkne-intrinsic.ll
…
rv64zknh-intrinsic-autoupgrade.ll
…
rv64zknh-intrinsic.ll
…
rv64zksed-intrinsic-autoupgrade2.ll
…
rv64zksed-intrinsic-autoupgrade.ll
…
rv64zksed-intrinsic.ll
…
rv64zksh-intrinsic-autoupgrade.ll
…
rv64zksh-intrinsic.ll
…
rvv-cfi-info.ll
[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)
2024-09-30 11:44:23 -07:00
sadd_sat_plus.ll
[RISCV] Custom type legalize i32 SADDSAT/SSUBSAT without Zbb.
2024-02-04 23:15:58 -08:00
sadd_sat.ll
[RISCV] Custom type legalize i32 SADDSAT/SSUBSAT without Zbb.
2024-02-04 23:15:58 -08:00
saverestore-scs.ll
…
saverestore.ll
[RISCV] Update some tests that used "interrupt"="user". NFC
2023-05-31 20:31:24 -07:00
scmp.ll
[RISCV] Enable load clustering by default (#73789)
2024-10-01 13:45:30 +01:00
sdata-limit-0.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdata-limit-4.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdata-limit-8.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdata-local-sym.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdata-sections.ll
[RISCV] Let -data-sections also work on sbss/sdata sections (#87040)
2024-08-23 14:06:12 +01:00
sdiv-pow2-cmov.ll
…
select-and.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
select-bare.ll
[RISCV] Remove support for the unratified Zbt extension.
2022-09-20 20:26:48 -07:00
select-binop-identity.ll
[RISCV] Graduate Zicond to non-experimental (#79811)
2024-01-29 15:58:54 +00:00
select-cc.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
select-const.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
select-constant-xor.ll
[RISCV] Add RISCV::XORI to RISCVDAGToDAGISel::hasAllNBitUsers.
2022-12-28 15:17:41 -08:00
select-optimize-multiple.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
select-optimize-multiple.mir
[NewPM][CodeGen] Port finalize-isel to new pass manager (#94214)
2024-06-04 09:23:52 +08:00
select-or.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
select-to-and-zext.ll
…
select.ll
[RISCV] Add coverage for select C, C1, C2 where (C1-C2)*[0,1] is cheap
2024-09-16 12:46:43 -07:00
selectcc-to-shiftand.ll
[RISCV] Limit (and (sra x, c2), c1) -> (srli (srai x, c2-c3), c3) isel in some cases. (#102034)
2024-08-06 20:27:14 -07:00
setcc-logic.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
sext-zext-trunc.ll
…
sextw-removal-debug.mir
[RISCV] Ignore debug instructions in hasAllNBitUsers in RISCVOptWInstrs.
2023-12-03 21:27:50 -08:00
sextw-removal.ll
Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)
2024-08-03 01:51:26 +03:00
shadowcallstack.ll
[RISCV] Add Zicfiss support to the shadow call stack implementation. (#68075)
2024-02-10 22:18:46 +08:00
shift-amount-mod.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
shift-and.ll
[RISCV] Make sure we always call tryShrinkShlLogicImm for ISD:AND during isel.
2022-10-22 14:30:13 -07:00
shift-masked-shamt.ll
…
shifts.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
shl-cttz.ll
[RISCV] Remove riscv-experimental-rv64-legal-i32. (#102509)
2024-08-09 11:48:48 -07:00
shl-demanded.ll
[RISCV] Strip W suffix from ADDIW (#68425)
2023-10-06 10:28:01 -07:00
shlimm-addimm.ll
…
short-forward-branch-opt.ll
…
shrinkwrap-jump-table.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
shrinkwrap.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
sifive7-enable-intervals.mir
…
signbit-test.ll
[RISCV] Enable the TypePromotion pass from AArch64/ARM.
2024-02-13 09:57:48 -08:00
signed-truncation-check.ll
[RISCV] Select (and (sra x, c2), c1) as (srli (srai x, c2-c3), c3). (#101868)
2024-08-04 22:35:38 -07:00
sink-and-fold-crash.mir
[MachineSink][RISCV] Only call isConstantPhysReg or isIgnorableUse for uses. (#99363)
2024-07-17 13:06:58 -07:00
sink-icmp.ll
…
spill-fill-fold.ll
…
spill-fpr-scalar.ll
…
spir-kernel-cc.ll
[OpenCL][RISCV] Support SPIR_KERNEL calling convention (#69282)
2023-10-19 11:00:39 +08:00
split-offsets.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
split-sp-adjust.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
split-store.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
split-udiv-by-constant.ll
…
split-urem-by-constant.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
srem-lkk.ll
…
srem-seteq-illegal-types.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
srem-vector-lkk.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
srodata.ll
[RISCV] Place mergeable small read only data into srodata section (#82214)
2024-03-11 13:57:06 +08:00
ssub_sat_plus.ll
[RISCV] Custom type legalize i32 SADDSAT/SSUBSAT without Zbb.
2024-02-04 23:15:58 -08:00
ssub_sat.ll
[RISCV] Custom type legalize i32 SADDSAT/SSUBSAT without Zbb.
2024-02-04 23:15:58 -08:00
stack-folding.ll
[RISCV] Remove gp and tp from callee saved register lists. (#76483)
2023-12-27 21:36:03 -08:00
stack-guard-global.ll
[RISCV] Support -mstack-protector-guard=tls (#108942)
2024-10-02 16:33:31 -07:00
stack-guard-tls.ll
[RISCV] Support -mstack-protector-guard=tls (#108942)
2024-10-02 16:33:31 -07:00
stack-inst-compress.mir
[MachineFrameInfo] Refactoring around computeMaxcallFrameSize() (NFC) (#78001)
2024-03-18 10:37:59 -04:00
stack-offset.ll
[RISCV] Exploit sh3add/sh2add for stack offsets by shifted 12-bit constants (#87950)
2024-04-08 14:53:21 -07:00
stack-protector-target.ll
[RISCV] Use the thread local stack protector for Android targets (#87672)
2024-05-13 08:52:59 -07:00
stack-realignment-with-variable-sized-objects.ll
[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)
2024-01-16 20:44:30 +08:00
stack-realignment.ll
[RISCV] fix SP recovery in a function epilogue (#110809)
2024-10-04 12:22:11 +03:00
stack-slot-coloring.mir
…
stack-slot-size.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
stack-store-check.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
subtarget-features-std-ext.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
switch-width.ll
[RISCV] Remove blank lines at the end of testcases. NFC.
2024-01-02 13:13:04 +08:00
tagged-globals.ll
…
tail-calls.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
target-abi-invalid.ll
[RISCV] Support -target-abi at the MC layer and for codegen
2019-03-09 09:28:06 +00:00
target-abi-valid.ll
[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)
2024-01-16 20:44:30 +08:00
thread-pointer.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
tls-models.ll
[RISCV] Support TLSDESC in the RISC-V backend (#66915)
2024-01-23 16:16:07 -08:00
tlsdesc-symbol.ll
…
trunc-free.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
typepromotion-overflow.ll
…
uadd_sat_plus.ll
[LegalizeTypes][RISCV] Use signed promotion for UADDSAT if that's what the target prefers. (#102842)
2024-08-12 09:34:51 -07:00
uadd_sat.ll
…
ucmp.ll
[RISCV] Enable load clustering by default (#73789)
2024-10-01 13:45:30 +01:00
umulo-128-legalisation-lowering.ll
[RISCV] Enable load clustering by default (#73789)
2024-10-01 13:45:30 +01:00
unaligned-load-store.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
unfold-masked-merge-scalar-variablemask.ll
…
unroll-loop-cse.ll
[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)
2024-05-28 15:05:23 -07:00
urem-lkk.ll
…
urem-seteq-illegal-types.ll
[DAG] SimplifyMultipleUseDemandedBits - ignore SRL node if we're just demanding known sign bits (#114389)
2024-10-31 16:40:29 +00:00
urem-vector-lkk.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
usub_sat_plus.ll
[LegalizeTypes][RISCV] Use SExtOrZExtPromotedOperands to promote operands for USUBSAT. (#102781)
2024-08-11 10:22:31 -07:00
usub_sat.ll
[MachineCombiner] Use default latency model when no detailed model available
2023-01-20 09:28:20 -08:00
vararg-ilp32e.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
vararg.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
vector-abi.ll
[RISCV] Merge machine operand flag MO_PLT into MO_CALL (#77253)
2024-01-07 12:43:39 -08:00
verify-instr.mir
[CodeGen][NewPM] Port MachineVerifier to new pass manager (#98628)
2024-07-15 12:42:44 +08:00
vlenb.ll
[MachineLICM] Hoist copies of constant physical register (#93285)
2024-05-29 14:10:01 +08:00
vscale-demanded-bits.ll
Move stepvector intrinsic out of experimental namespace (#98043)
2024-08-28 12:48:20 +01:00
wide-mem.ll
[RISCV] Convert some tests to opaque pointers (NFC)
2022-12-19 13:01:08 +01:00
wide-scalar-shift-by-byte-multiple-legalization.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
wide-scalar-shift-legalization.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
xaluo.ll
…
xcvalu.ll
[RISCV] Implement Clang Builtins for XCValu Extension in CV32E40P (#100684)
2024-10-01 11:22:02 +10:00
xcvbi.ll
[RISCV] Codegen support for XCVbi extension (#89719)
2024-05-08 11:22:16 +08:00
xcvbitmanip.ll
[RISCV] Implement intrinsics for XCVbitmanip extension in CV32E40P (#74993)
2023-12-17 19:29:40 +08:00
xcvmac.ll
[RISCV] Implement Intrinsics for XCVmac Extension in CV32E40P (#83112)
2024-07-15 10:25:25 +10:00
xcvmem.ll
[RISCV] Codegen support for XCVmem extension (#76916)
2024-06-07 21:45:49 +08:00
xtheadfmemidx.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
xtheadmac.ll
[RISCV] xtheadmac: fix commutativity issue for the in/out register
2023-02-17 19:45:22 +01:00
xtheadmemidx.ll
[CodeGen] Convert tests to opaque pointers (NFC)
2024-02-05 14:07:09 +01:00
xtheadmempair.ll
[RISCV] Enable store clustering by default (#73796)
2024-10-11 20:25:53 +01:00
zbb-cmp-combine.ll
[RISCV] Omit "@plt" in assembly output "call foo@plt" (#72467)
2024-01-07 12:09:44 -08:00
zcb-regalloc-hints.ll
[RISCV] Add regalloc hints for Zcb instructions. (#78949)
2024-01-23 09:33:06 -08:00
zcmp-additional-stack.ll
[RISCV] Align stack size down to a multiple of 16 before using cm.push/pop. (#86073)
2024-03-26 21:37:19 -07:00
zcmp-cm-popretz.mir
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zcmp-cm-push-pop.mir
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zcmp-prolog-epilog-crash.mir
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zcmp-with-float.ll
[RISCV] Remove stale comment from test. NFC (#81098)
2024-02-12 09:19:28 -08:00
zdinx-asm-constraint.ll
[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)
2024-10-18 10:40:38 +01:00
zdinx-boundary-check.ll
[RISCV] Fix another RV32 Zdinx load/store addressing corner case.
2024-09-04 23:26:40 -07:00
zdinx-large-spill.mir
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zext-with-load-is-free.ll
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zfh-half-intrinsics-strict.ll
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zfh-half-intrinsics.ll
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zfhmin-half-intrinsics-strict.ll
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zfhmin-half-intrinsics.ll
[RISCV] Add test for llvm.round.i32.f16 RV64+Zfhmin/Zhinxmin. NFC
2024-09-01 12:15:00 -07:00
zfhmin-imm.ll
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zicfilp-indirect-branch.ll
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zmmul.ll
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