cba70550cc
The "topological" sorting was behaving incorrectly in some cases: the exit of a loop could have a lower rank than a node in the loop. This causes issues when structurizing some patterns, and also codegen issues as we could generate BBs in the incorrect order in regard to the SPIR-V spec. Fixing this ordering alone broke other parts of the structurizer, which by luck worked. Had to fix those. Added more test cases, especially to test basic patterns. I also needed to tweak/disable some tests for 2 reasons: - SPIR-V now required reg2mem/mem2reg to run. Meaning dead stores are optimized away. Some tests require tweaks to avoid having the whole function removed. - Mem2Reg will generate variable & load/stores. This generates G_BITCAST in several cases. And there is currently something wrong we do with G_BITCAST which causes MIR verifier to complain. Until this is resolved, I disabled -verify-machineinstrs flag on those tests. --------- Signed-off-by: Nathan Gauër <brioche@google.com>
163 lines
5.4 KiB
LLVM
163 lines
5.4 KiB
LLVM
; RUN: llc -mtriple=spirv-unknown-vulkan-compute -O0 %s -o - | FileCheck %s
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; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-unknown-vulkan-compute %s -o - -filetype=obj | spirv-val %}
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;
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; int process() {
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; int c1 = 0;
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; int c2 = 1;
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; int c3 = 0;
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; int c4 = 1;
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; int val = 0;
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;
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; if (c1) {
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; if (c2)
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; val = 1;
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; } else {
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; if (c3) {
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; val = 2;
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; } else {
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; if (c4) {
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; val = 3;
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; }
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; }
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; }
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; return val;
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; }
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;
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; [numthreads(1, 1, 1)]
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; void main() {
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; process();
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; }
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; CHECK: %[[#func_11:]] = OpFunction %[[#uint:]] DontInline %[[#]]
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; CHECK: %[[#bb30:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb31:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb32:]] %[[#bb33:]]
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; CHECK: %[[#bb32:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb34:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb35:]] %[[#bb34:]]
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; CHECK: %[[#bb33:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb36:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb37:]] %[[#bb38:]]
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; CHECK: %[[#bb35:]] = OpLabel
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; CHECK: OpBranch %[[#bb34:]]
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; CHECK: %[[#bb37:]] = OpLabel
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; CHECK: OpBranch %[[#bb36:]]
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; CHECK: %[[#bb38:]] = OpLabel
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; CHECK: OpSelectionMerge %[[#bb39:]] None
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; CHECK: OpBranchConditional %[[#]] %[[#bb40:]] %[[#bb39:]]
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; CHECK: %[[#bb34:]] = OpLabel
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; CHECK: OpBranch %[[#bb31:]]
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; CHECK: %[[#bb40:]] = OpLabel
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; CHECK: OpBranch %[[#bb39:]]
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; CHECK: %[[#bb39:]] = OpLabel
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; CHECK: OpBranch %[[#bb36:]]
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; CHECK: %[[#bb36:]] = OpLabel
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; CHECK: OpBranch %[[#bb31:]]
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; CHECK: %[[#bb31:]] = OpLabel
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; CHECK: OpReturnValue %[[#]]
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; CHECK: OpFunctionEnd
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; CHECK: %[[#func_26:]] = OpFunction %[[#void:]] DontInline %[[#]]
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; CHECK: %[[#bb41:]] = OpLabel
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; CHECK: OpReturn
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; CHECK: OpFunctionEnd
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; CHECK: %[[#func_28:]] = OpFunction %[[#void:]] None %[[#]]
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; CHECK: %[[#bb42:]] = OpLabel
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; CHECK: OpReturn
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; CHECK: OpFunctionEnd
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target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-G1"
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target triple = "spirv-unknown-vulkan1.3-compute"
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; Function Attrs: convergent noinline norecurse nounwind optnone
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define spir_func noundef i32 @_Z7processv() #0 {
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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%c1 = alloca i32, align 4
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%c2 = alloca i32, align 4
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%c3 = alloca i32, align 4
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%c4 = alloca i32, align 4
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%val = alloca i32, align 4
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store i32 0, ptr %c1, align 4
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store i32 1, ptr %c2, align 4
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store i32 0, ptr %c3, align 4
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store i32 1, ptr %c4, align 4
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store i32 0, ptr %val, align 4
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%1 = load i32, ptr %c1, align 4
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%tobool = icmp ne i32 %1, 0
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br i1 %tobool, label %if.then, label %if.else
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if.then: ; preds = %entry
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%2 = load i32, ptr %c2, align 4
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%tobool1 = icmp ne i32 %2, 0
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br i1 %tobool1, label %if.then2, label %if.end
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if.then2: ; preds = %if.then
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store i32 1, ptr %val, align 4
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br label %if.end
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if.end: ; preds = %if.then2, %if.then
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br label %if.end10
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if.else: ; preds = %entry
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%3 = load i32, ptr %c3, align 4
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%tobool3 = icmp ne i32 %3, 0
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br i1 %tobool3, label %if.then4, label %if.else5
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if.then4: ; preds = %if.else
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store i32 2, ptr %val, align 4
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br label %if.end9
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if.else5: ; preds = %if.else
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%4 = load i32, ptr %c4, align 4
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%tobool6 = icmp ne i32 %4, 0
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br i1 %tobool6, label %if.then7, label %if.end8
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if.then7: ; preds = %if.else5
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store i32 3, ptr %val, align 4
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br label %if.end8
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if.end8: ; preds = %if.then7, %if.else5
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br label %if.end9
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if.end9: ; preds = %if.end8, %if.then4
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br label %if.end10
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if.end10: ; preds = %if.end9, %if.end
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%5 = load i32, ptr %val, align 4
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ret i32 %5
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}
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; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)
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declare token @llvm.experimental.convergence.entry() #1
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; Function Attrs: convergent noinline norecurse nounwind optnone
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define internal spir_func void @main() #0 {
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entry:
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%0 = call token @llvm.experimental.convergence.entry()
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%call1 = call spir_func noundef i32 @_Z7processv() #3 [ "convergencectrl"(token %0) ]
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ret void
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}
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; Function Attrs: convergent norecurse
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define void @main.1() #2 {
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entry:
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call void @main()
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ret void
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}
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attributes #0 = { convergent noinline norecurse nounwind optnone "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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attributes #1 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }
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attributes #2 = { convergent norecurse "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
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attributes #3 = { convergent }
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!llvm.module.flags = !{!0, !1, !2}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 4, !"dx.disable_optimizations", i32 1}
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!2 = !{i32 7, !"frame-pointer", i32 2}
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