Luke Lau df96b56b9f [RISCV] Move VMV0 elimination past machine SSA opts (#126850) ...

This is the follow up to #125026 that keeps mask operands in virtual
register form for as long as possible throughout the backend.

The diffs in this patch are from MachineCSE/MachineSink/RISCVVLOptimizer
kicking in.

The invariant that the mask COPY never has a subreg no longer holds
after MachineCSE (it coalesces some copies), so it needed to be relaxed.

2025-02-20 12:41:05 +08:00

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