Files
clang-p2996/llvm/test/CodeGen/SystemZ/vec-cmp-08.ll
Ulrich Weigand e8e406041e Fix sext_in_reg from i1 to i128
The combineSIGN_EXTEND_INREG routine was using
DAG.getConstant(-1, DL, VT), which does not result in
the expected value when VT has more than 64 bits.

Fix this by using DAG.getAllOnesConstant(DL, VT) instead.

Also add test cases for v1i128 comparisons (which triggers
the bug).
2024-07-15 11:26:37 +02:00

12 KiB