Evan Cheng da103bf9ec Model ARM predicated write as read-mod-write. e.g. ...

r0 = mov #0
r0 = moveq #1

Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.

llvm-svn: 146583

2011-12-14 20:00:08 +00:00

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