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clang-p2996/llvm/lib/Target/RISCV
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Jessica Clarke ca606dc988 [RISCV] More whitespace and comment typo fixes in RISCVInstrInfoC.td
2021-02-11 02:32:36 +00:00
..
AsmParser
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
Disassembler
[RISCV] Fix shared libs build
2021-02-09 06:14:25 -06:00
MCTargetDesc
[RISCV] Make scalable vector FMA commutable for register allocation.
2021-02-08 10:05:33 -08:00
TargetInfo
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
CMakeLists.txt
[RISCV] Merge Utils library into MCTargetDesc
2021-01-14 11:47:30 -08:00
RISCV.h
[RISCV] Merge Utils library into MCTargetDesc
2021-01-14 11:47:30 -08:00
RISCV.td
[RISCV] Fix name of Zba extension (NFC)
2021-01-24 21:02:34 +00:00
RISCVAsmPrinter.cpp
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
[GlobalISel] Base implementation for sret demotion.
2021-01-06 10:30:50 +05:30
RISCVCallLowering.h
[GlobalISel] Base implementation for sret demotion.
2021-01-06 10:30:50 +05:30
RISCVCleanupVSETVLI.cpp
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
RISCVFrameLowering.cpp
[RISCV] Do not grow the stack a second time when we need to realign the stack
2021-01-09 16:51:09 +00:00
RISCVFrameLowering.h
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
2020-11-05 11:02:18 +00:00
RISCVInstrFormats.td
[RISCV] Make scalable vector FMA commutable for register allocation.
2021-02-08 10:05:33 -08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
RISCVInstrInfo.cpp
[RISCV] Make scalable vector FMA commutable for register allocation.
2021-02-08 10:05:33 -08:00
RISCVInstrInfo.h
[RISCV] Make scalable vector FMA commutable for register allocation.
2021-02-08 10:05:33 -08:00
RISCVInstrInfo.td
[RISCV] Copy isUnneededShiftMask from X86.
2021-01-27 20:46:10 -08:00
RISCVInstrInfoA.td
…
RISCVInstrInfoB.td
[RISCV] Use OperandTransform field of ImmLeaf to slightly simplify a couple bitmanip patterns. NFC
2021-02-10 17:52:07 -08:00
RISCVInstrInfoC.td
[RISCV] More whitespace and comment typo fixes in RISCVInstrInfoC.td
2021-02-11 02:32:36 +00:00
RISCVInstrInfoD.td
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
RISCVInstrInfoF.td
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
RISCVInstrInfoM.td
[RISCV] Don't remove (and X, 0xffffffff) from inputs when matching RISCVISD::DIVUW/REMUW to 64-bit DIVU/REMU.
2020-11-26 23:15:41 -08:00
RISCVInstrInfoV.td
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
RISCVInstrInfoVPseudos.td
[RISCV] Use whole register load/store for generic load/store.
2021-02-09 15:52:04 +08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Add support for selecting vid.v from build_vector
2021-02-10 10:58:40 +00:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Add support for matching .vf forms of fadd/fsub/fmul/fdiv/fma for fixed vectors.
2021-02-10 10:16:27 -08:00
RISCVInstrInfoZfh.td
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
RISCVInstructionSelector.cpp
…
RISCVISelDAGToDAG.cpp
[RISCV] Remove SRO* and SLO* instructions from bitmanip.
2021-02-09 09:35:05 -08:00
RISCVISelDAGToDAG.h
[RISCV] Remove SRO* and SLO* instructions from bitmanip.
2021-02-09 09:35:05 -08:00
RISCVISelLowering.cpp
[RISCV] Add support for selecting vrgather.vx/vi for fixed vector splat shuffles.
2021-02-10 10:01:56 -08:00
RISCVISelLowering.h
[RISCV] Remove superfluous semicolon. NFC
2021-02-10 11:20:29 -08:00
RISCVLegalizerInfo.cpp
…
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.h
…
RISCVMCInstLower.cpp
[RISCV] Define different pseudo instructions for different FPR.
2021-01-26 15:48:35 +08:00
RISCVMergeBaseOffset.cpp
[RISCV] Support Zfh half-precision floating-point extension.
2020-12-03 09:16:33 +08:00
RISCVRegisterBankInfo.cpp
…
RISCVRegisterBankInfo.h
…
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
[RISCV] Define the remaining vector fixed-point arithmetic intrinsics.
2020-12-20 22:57:07 -08:00
RISCVRegisterInfo.h
…
RISCVRegisterInfo.td
Support a list of CostPerUse values
2021-01-29 10:14:52 +05:30
RISCVSchedRocket.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSchedSiFive7.td
[RISCV] Use the commercial name for scheduling model (NFC)
2020-10-23 16:33:27 -05:00
RISCVSchedule.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSubtarget.cpp
[RISCV] Make the min and max vector width command line options more consistent and check their relationship to each other.
2021-02-09 10:47:23 -08:00
RISCVSubtarget.h
[RISCV] Make the min and max vector width command line options more consistent and check their relationship to each other.
2021-02-09 10:47:23 -08:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp
[RISCV] Merge Utils library into MCTargetDesc
2021-01-14 11:47:30 -08:00
RISCVTargetMachine.h
[RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.
2020-12-18 21:50:55 +00:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Make the min and max vector width command line options more consistent and check their relationship to each other.
2021-02-09 10:47:23 -08:00
RISCVTargetTransformInfo.h
[RISCV] Initial support of LoopVectorizer for RISC-V Vector.
2021-02-09 06:32:18 +08:00