cb161b3a88
fma+neg will come in a different patch since I haven't done it for .vv yet either. Differential Revision: https://reviews.llvm.org/D96375
321 lines
16 KiB
TableGen
321 lines
16 KiB
TableGen
//===- RISCVInstrInfoVVLPatterns.td - RVV VL patterns ------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// This file contains the required infrastructure and VL patterns to
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/// support code generation for the standard 'V' (Vector) extension, version
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/// 0.10. This version is still experimental as the 'V' extension hasn't been
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/// ratified yet.
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///
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/// This file is included from and depends upon RISCVInstrInfoVPseudos.td
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///
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/// Note: the patterns for RVV intrinsics are found in
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/// RISCVInstrInfoVPseudos.td.
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///
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Helpers to define the VL patterns.
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//===----------------------------------------------------------------------===//
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def SDT_RISCVVLE_VL : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisPtrTy<1>,
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SDTCisVT<2, XLenVT>]>;
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def SDT_RISCVVSE_VL : SDTypeProfile<0, 3, [SDTCisVec<0>, SDTCisPtrTy<1>,
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SDTCisVT<2, XLenVT>]>;
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def SDT_RISCVIntBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
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SDTCisSameAs<0, 2>,
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SDTCisVec<0>, SDTCisInt<0>,
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SDTCVecEltisVT<3, i1>,
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SDTCisSameNumEltsAs<0, 3>,
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SDTCisVT<4, XLenVT>]>;
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def SDT_RISCVFPUnOp_VL : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
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SDTCisVec<0>, SDTCisFP<0>,
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SDTCVecEltisVT<2, i1>,
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SDTCisSameNumEltsAs<0, 2>,
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SDTCisVT<3, XLenVT>]>;
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def SDT_RISCVFPBinOp_VL : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
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SDTCisSameAs<0, 2>,
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SDTCisVec<0>, SDTCisFP<0>,
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SDTCVecEltisVT<3, i1>,
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SDTCisSameNumEltsAs<0, 3>,
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SDTCisVT<4, XLenVT>]>;
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def riscv_vle_vl : SDNode<"RISCVISD::VLE_VL", SDT_RISCVVLE_VL,
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[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
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def riscv_vse_vl : SDNode<"RISCVISD::VSE_VL", SDT_RISCVVSE_VL,
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[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
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def riscv_add_vl : SDNode<"RISCVISD::ADD_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
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def riscv_sub_vl : SDNode<"RISCVISD::SUB_VL", SDT_RISCVIntBinOp_VL>;
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def riscv_mul_vl : SDNode<"RISCVISD::MUL_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
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def riscv_and_vl : SDNode<"RISCVISD::AND_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
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def riscv_or_vl : SDNode<"RISCVISD::OR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
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def riscv_xor_vl : SDNode<"RISCVISD::XOR_VL", SDT_RISCVIntBinOp_VL, [SDNPCommutative]>;
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def riscv_sdiv_vl : SDNode<"RISCVISD::SDIV_VL", SDT_RISCVIntBinOp_VL>;
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def riscv_srem_vl : SDNode<"RISCVISD::SREM_VL", SDT_RISCVIntBinOp_VL>;
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def riscv_udiv_vl : SDNode<"RISCVISD::UDIV_VL", SDT_RISCVIntBinOp_VL>;
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def riscv_urem_vl : SDNode<"RISCVISD::UREM_VL", SDT_RISCVIntBinOp_VL>;
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def riscv_shl_vl : SDNode<"RISCVISD::SHL_VL", SDT_RISCVIntBinOp_VL>;
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def riscv_sra_vl : SDNode<"RISCVISD::SRA_VL", SDT_RISCVIntBinOp_VL>;
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def riscv_srl_vl : SDNode<"RISCVISD::SRL_VL", SDT_RISCVIntBinOp_VL>;
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def riscv_fadd_vl : SDNode<"RISCVISD::FADD_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>;
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def riscv_fsub_vl : SDNode<"RISCVISD::FSUB_VL", SDT_RISCVFPBinOp_VL>;
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def riscv_fmul_vl : SDNode<"RISCVISD::FMUL_VL", SDT_RISCVFPBinOp_VL, [SDNPCommutative]>;
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def riscv_fdiv_vl : SDNode<"RISCVISD::FDIV_VL", SDT_RISCVFPBinOp_VL>;
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def riscv_fneg_vl : SDNode<"RISCVISD::FNEG_VL", SDT_RISCVFPUnOp_VL>;
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def SDT_RISCVVecFMA_VL : SDTypeProfile<1, 5, [SDTCisSameAs<0, 1>,
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SDTCisSameAs<0, 2>,
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SDTCisSameAs<0, 3>,
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SDTCisVec<0>, SDTCisFP<0>,
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SDTCVecEltisVT<4, i1>,
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SDTCisSameNumEltsAs<0, 4>,
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SDTCisVT<5, XLenVT>]>;
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def riscv_fma_vl : SDNode<"RISCVISD::FMA_VL", SDT_RISCVVecFMA_VL>;
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def riscv_vrgather_vx_vl : SDNode<"RISCVISD::VRGATHER_VX_VL",
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SDTypeProfile<1, 4, [SDTCisVec<0>,
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SDTCisSameAs<0, 1>,
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SDTCisVT<2, XLenVT>,
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SDTCVecEltisVT<3, i1>,
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SDTCisSameNumEltsAs<0, 3>,
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SDTCisVT<4, XLenVT>]>>;
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def SDT_RISCVVMSETCLR_VL : SDTypeProfile<1, 1, [SDTCisVec<0>,
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SDTCVecEltisVT<0, i1>,
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SDTCisVT<1, XLenVT>]>;
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def riscv_vmclr_vl : SDNode<"RISCVISD::VMCLR_VL", SDT_RISCVVMSETCLR_VL>;
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def riscv_vmset_vl : SDNode<"RISCVISD::VMSET_VL", SDT_RISCVVMSETCLR_VL>;
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def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>;
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def SplatFPOp : PatFrag<(ops node:$op),
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(riscv_vfmv_v_f_vl node:$op, srcvalue)>;
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class VPatBinaryVL_VV<SDNode vop,
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string instruction_name,
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ValueType result_type,
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ValueType op_type,
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ValueType mask_type,
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int sew,
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LMULInfo vlmul,
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VReg RetClass,
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VReg op_reg_class> :
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Pat<(result_type (vop
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(op_type op_reg_class:$rs1),
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(op_type op_reg_class:$rs2),
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(mask_type true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>(instruction_name#"_VV_"# vlmul.MX)
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op_reg_class:$rs1,
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op_reg_class:$rs2,
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GPR:$vl, sew)>;
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multiclass VPatBinaryVL_VV_VX<SDNode vop, string instruction_name> {
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foreach vti = AllIntegerVectors in {
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def : VPatBinaryVL_VV<vop, instruction_name,
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vti.Vector, vti.Vector, vti.Mask, vti.SEW,
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vti.LMul, vti.RegClass, vti.RegClass>;
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// FIXME: Support splats.
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}
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}
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multiclass VPatBinaryVL_VV_VX_VI<SDNode vop, string instruction_name,
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Operand ImmType = simm5> {
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foreach vti = AllIntegerVectors in {
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def : VPatBinaryVL_VV<vop, instruction_name,
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vti.Vector, vti.Vector, vti.Mask, vti.SEW,
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vti.LMul, vti.RegClass, vti.RegClass>;
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// FIXME: Support splats.
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}
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}
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class VPatBinaryVL_VF<SDNode vop,
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string instruction_name,
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ValueType result_type,
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ValueType vop_type,
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ValueType mask_type,
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int sew,
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LMULInfo vlmul,
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VReg RetClass,
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VReg vop_reg_class,
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RegisterClass scalar_reg_class> :
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Pat<(result_type (vop (vop_type vop_reg_class:$rs1),
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(vop_type (SplatFPOp scalar_reg_class:$rs2)),
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(mask_type true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>(instruction_name#"_"#vlmul.MX)
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vop_reg_class:$rs1,
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scalar_reg_class:$rs2,
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GPR:$vl, sew)>;
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multiclass VPatBinaryFPVL_VV_VF<SDNode vop, string instruction_name> {
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foreach vti = AllFloatVectors in {
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def : VPatBinaryVL_VV<vop, instruction_name,
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vti.Vector, vti.Vector, vti.Mask, vti.SEW,
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vti.LMul, vti.RegClass, vti.RegClass>;
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def : VPatBinaryVL_VF<vop, instruction_name#"_V"#vti.ScalarSuffix,
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vti.Vector, vti.Vector, vti.Mask, vti.SEW,
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vti.LMul, vti.RegClass, vti.RegClass,
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vti.ScalarRegClass>;
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}
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}
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multiclass VPatBinaryFPVL_R_VF<SDNode vop, string instruction_name> {
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foreach fvti = AllFloatVectors in
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def : Pat<(fvti.Vector (vop (SplatFPOp fvti.ScalarRegClass:$rs2),
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fvti.RegClass:$rs1,
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(fvti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>(instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX)
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fvti.RegClass:$rs1, fvti.ScalarRegClass:$rs2,
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GPR:$vl, fvti.SEW)>;
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}
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//===----------------------------------------------------------------------===//
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// Patterns.
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtV] in {
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// 7.4. Vector Unit-Stride Instructions
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foreach vti = AllVectors in {
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defvar load_instr = !cast<Instruction>("PseudoVLE"#vti.SEW#"_V_"#vti.LMul.MX);
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defvar store_instr = !cast<Instruction>("PseudoVSE"#vti.SEW#"_V_"#vti.LMul.MX);
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// Load
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def : Pat<(vti.Vector (riscv_vle_vl RVVBaseAddr:$rs1, (XLenVT (VLOp GPR:$vl)))),
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(load_instr RVVBaseAddr:$rs1, GPR:$vl, vti.SEW)>;
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// Store
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def : Pat<(riscv_vse_vl (vti.Vector vti.RegClass:$rs2), RVVBaseAddr:$rs1, (XLenVT (VLOp GPR:$vl))),
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(store_instr vti.RegClass:$rs2, RVVBaseAddr:$rs1, GPR:$vl, vti.SEW)>;
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}
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// 12.1. Vector Single-Width Integer Add and Subtract
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defm "" : VPatBinaryVL_VV_VX_VI<riscv_add_vl, "PseudoVADD">;
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defm "" : VPatBinaryVL_VV_VX<riscv_sub_vl, "PseudoVSUB">;
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// 12.5. Vector Bitwise Logical Instructions
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defm "" : VPatBinaryVL_VV_VX_VI<riscv_and_vl, "PseudoVAND">;
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defm "" : VPatBinaryVL_VV_VX_VI<riscv_or_vl, "PseudoVOR">;
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defm "" : VPatBinaryVL_VV_VX_VI<riscv_xor_vl, "PseudoVXOR">;
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// 12.6. Vector Single-Width Bit Shift Instructions
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defm "" : VPatBinaryVL_VV_VX_VI<riscv_shl_vl, "PseudoVSLL", uimm5>;
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defm "" : VPatBinaryVL_VV_VX_VI<riscv_srl_vl, "PseudoVSRL", uimm5>;
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defm "" : VPatBinaryVL_VV_VX_VI<riscv_sra_vl, "PseudoVSRA", uimm5>;
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// 12.10. Vector Single-Width Integer Multiply Instructions
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defm "" : VPatBinaryVL_VV_VX<riscv_mul_vl, "PseudoVMUL">;
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// 12.11. Vector Integer Divide Instructions
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defm "" : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU">;
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defm "" : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV">;
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defm "" : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">;
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defm "" : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">;
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} // Predicates = [HasStdExtV]
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let Predicates = [HasStdExtV, HasStdExtF] in {
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// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
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defm "" : VPatBinaryFPVL_VV_VF<riscv_fadd_vl, "PseudoVFADD">;
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defm "" : VPatBinaryFPVL_VV_VF<riscv_fsub_vl, "PseudoVFSUB">;
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defm "" : VPatBinaryFPVL_R_VF<riscv_fsub_vl, "PseudoVFRSUB">;
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// 14.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
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defm "" : VPatBinaryFPVL_VV_VF<riscv_fmul_vl, "PseudoVFMUL">;
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defm "" : VPatBinaryFPVL_VV_VF<riscv_fdiv_vl, "PseudoVFDIV">;
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defm "" : VPatBinaryFPVL_R_VF<riscv_fdiv_vl, "PseudoVFRDIV">;
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// 14.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions.
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foreach vti = AllFloatVectors in {
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// NOTE: We choose VFMADD because it has the most commuting freedom. So it
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// works best with how TwoAddressInstructionPass tries commuting.
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defvar suffix = vti.LMul.MX # "_COMMUTABLE";
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def : Pat<(vti.Vector (riscv_fma_vl vti.RegClass:$rd, vti.RegClass:$rs1,
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vti.RegClass:$rs2, (vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVFMADD_VV_"# suffix)
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vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
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GPR:$vl, vti.SEW)>;
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// The choice of VFMADD here is arbitrary, vfmadd.vf and vfmacc.vf are equally
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// commutable.
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def : Pat<(vti.Vector (riscv_fma_vl (SplatFPOp vti.ScalarRegClass:$rs1),
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vti.RegClass:$rd, vti.RegClass:$rs2,
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(vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVFMADD_V" # vti.ScalarSuffix # "_" # suffix)
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vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
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GPR:$vl, vti.SEW)>;
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}
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// 14.12. Vector Floating-Point Sign-Injection Instructions
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// Handle fneg with VFSGNJN using the same input for both operands.
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foreach vti = AllFloatVectors in {
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def : Pat<(riscv_fneg_vl (vti.Vector vti.RegClass:$rs), (vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl))),
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(!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX)
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vti.RegClass:$rs, vti.RegClass:$rs, GPR:$vl, vti.SEW)>;
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}
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} // Predicates = [HasStdExtV, HasStdExtF]
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// 17.4. Vector Register GAther Instruction
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let Predicates = [HasStdExtV] in {
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foreach vti = AllIntegerVectors in {
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def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1,
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(vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX)
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vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.SEW)>;
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def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm,
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(vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX)
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vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.SEW)>;
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}
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} // Predicates = [HasStdExtV]
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let Predicates = [HasStdExtV, HasStdExtF] in {
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foreach vti = AllFloatVectors in {
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def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, GPR:$rs1,
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(vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVRGATHER_VX_"# vti.LMul.MX)
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vti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.SEW)>;
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def : Pat<(vti.Vector (riscv_vrgather_vx_vl vti.RegClass:$rs2, uimm5:$imm,
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(vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVRGATHER_VI_"# vti.LMul.MX)
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vti.RegClass:$rs2, uimm5:$imm, GPR:$vl, vti.SEW)>;
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}
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} // Predicates = [HasStdExtV, HasStdExtF]
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//===----------------------------------------------------------------------===//
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// Miscellaneous RISCVISD SDNodes
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//===----------------------------------------------------------------------===//
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def riscv_vid_vl : SDNode<"RISCVISD::VID_VL", SDTypeProfile<1, 2,
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[SDTCisVec<0>, SDTCisVec<1>, SDTCVecEltisVT<1, i1>,
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SDTCisSameNumEltsAs<0, 1>, SDTCisVT<2, XLenVT>]>, []>;
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let Predicates = [HasStdExtV] in {
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foreach vti = AllIntegerVectors in
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def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask true_mask),
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(XLenVT (VLOp GPR:$vl)))),
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(!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX) GPR:$vl, vti.SEW)>;
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} // Predicates = [HasStdExtV]
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