Tom Stellard a77c3f7010 R600/SI: Fix bug in VGPR spilling ...

AMDGPU::SI_SPILL_V96_RESTORE was missing from a switch statement, which
caused the srsrc and soffset register to not be set correctly.

This commit replaces the switch statement with a SITargetInfo query
to make sure all spill instructions are covered.

Differential Revision: http://reviews.llvm.org/D9582

llvm-svn: 237164

2015-05-12 18:59:17 +00:00

6.8 KiB

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